Asymmetric groove SiC MOSFET device with composite electrode

Abstract

The invention relates to an asymmetric groove SiC MOSFET device with a composite electrode, and belongs to the technical field of semiconductor devices. Aiming at the problems of contradiction between specific on-resistance and breakdown voltage in a traditional SiC MOSFET, large recovery charge and limited high-frequency performance caused by conduction of a body diode during reverse conduction, an N-Drift layer and an N-CSL layer are sequentially constructed on an N + substrate, and an asymmetric trench is formed by integrating a depletion type PMOS structure, a second P well, a P-base region and a floating P + / N + region and combining a trench gate and an auxiliary trench gate; the composite electrode covers the floating region to promote carrier recombination. The invention has the beneficial effects of obviously reducing on-resistance and loss, inhibiting reverse body diode conduction, optimizing breakdown voltage and conduction performance balance, improving high-frequency switching speed and device reliability, and being suitable for high-power and high-frequency application scenes.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor devices and relates to an asymmetric trench SiC MOSFET device with a composite electrode. Background Art

[0002] Power semiconductor devices, as core components of power conversion systems, are widely used in industrial control, renewable energy generation, and electric vehicles. While traditional silicon-based insulated gate bipolar transistors (IGBTs) offer high voltage resistance, they suffer from high switching losses and limited operating frequencies, making them difficult to meet the demands of high-frequency, high-efficiency applications. Silicon carbide (SiC) metal oxide semiconductor field-effect transistors (MOSFETs), with their wide bandgap and high critical breakdown field, demonstrate significant advantages in high-temperature, high-frequency, and high-voltage applications.

[0003] However, existing asymmetric trench silicon carbide MOSFET devices still face key bottlenecks: First, there is an inherent contradiction between the device's specific on-resistance and breakdown voltage. Reducing the on-resistance generally leads to a decrease in breakdown voltage, while reducing it increases conduction losses. Second, under reverse conduction conditions, the body diode easily conducts and triggers bipolar degradation, resulting in increased reverse recovery charge, which limits switching speed and reliability. Furthermore, the traditional device structure's inadequate optimization of gate charge density further restricts improvements in high-frequency performance.

[0004] To address the above issues, a new device structure is urgently needed that can reduce the specific on-resistance while maintaining a high breakdown voltage and effectively suppress the body diode effect during reverse conduction, thereby improving the overall performance and reliability of the device. Summary of the Invention

[0005] In view of this, the object of the present invention is to provide an asymmetric trench SiC MOSFET device with a composite electrode, so as to reduce the specific on-resistance of the device, reduce the conduction loss, and improve the reverse recovery speed of the device.

[0006] In order to achieve the above object, the present invention provides the following technical solutions:

[0007] An asymmetric trench SiC MOSFET device with a composite electrode, the device comprising:

[0008] N+ substrate 19;

[0009] An N-Drift layer 18 formed on a first surface of the N+ substrate 19;

[0010] an N-CSL layer 17 formed on the surface of the N-Drift layer 18;

[0011] a depletion-mode PMOS structure formed on a first side surface of the N-CSL layer 17;

[0012] a second P-well 16 formed on a second side surface of the N-CSL layer 17;

[0013] A trench gate 5 and an auxiliary trench gate 6 are formed on the surface of the depletion-mode PMOS structure and located on both sides thereof, wherein the trench gate 5 and the auxiliary trench gate 6 are respectively surrounded by a first oxide layer 7 and a second oxide layer 8;

[0014] A P-base 13 formed on the surface of the N-CSL layer 17 and located between the second P-well 16 and the trench gate 5;

[0015] A source N+ region 9 formed on the surface of the P-base 13 and located between the second P-well 16 and the trench gate 5;

[0016] A floating P+ region 11 formed on the surface of the second P-well 16;

[0017] A floating N+ region 12 formed on the surface of the N-CSL layer 17;

[0018] A composite electrode 4 formed on the surface of the floating P+ region 11 and the floating N+ region 12;

[0019] A source electrode 2 is formed on the top of the device, and the source electrode 2 is electrically connected to the source N+ region 9 and the second P-well 16;

[0020] A drain electrode 3 is formed on the second surface of the N+ substrate 19 .

[0021] Furthermore, the depletion-mode PMOS structure includes:

[0022] a first P-well 15 formed on a first side surface of the N-CSL layer 17;

[0023] A P-ch layer 14 formed on the surface of the first P-well 15 and located between the trench gate 5 and the auxiliary trench gate 6;

[0024] A source P+ region 10 is formed on the surface of the P-ch layer 14 and connected to the source electrode 2 .

[0025] Furthermore, the thickness of the first oxide layer 7 and the second oxide layer 8 is 50 nm, and the material is silicon dioxide.

[0026] Furthermore, during reverse conduction, electrons recombined with holes at the recombination electrode 4 through the drain electrode 3 , thereby suppressing conduction of the body diode.

[0027] Furthermore, the doping concentration of the floating P+ region 11 is 1×10 20 cm -3, the doping concentration of the floating N+ region 12 is 1×10 20 cm -3 .

[0028] Furthermore, the width of the trench gate 5 and the auxiliary trench gate 6 are both 0.7 μm, the depth is 1.1 μm, and the concentration of phosphorus doped in the polysilicon gate is 1×10 20 cm -3 .

[0029] Furthermore, the doping concentration of the N-CSL layer 17 is 2.5×10 16 cm -3 , with a thickness of 1.6μm.

[0030] Furthermore, the composite electrode 4 forms an ohmic contact with the floating P+ region 11 and the floating N+ region 12 , and is made of aluminum or copper.

[0031] The beneficial effects of the present invention are:

[0032] (1) By integrating a depletion-type PMOS structure, the connection between the P+ source region and the P well is disconnected during forward conduction, effectively reducing the specific on-resistance and increasing the current density, thereby improving the conduction characteristics of the device.

[0033] (2) The design of the composite electrode promotes the rapid recombination of electrons and holes during reverse conduction, inhibits the conduction of the body diode, reduces the reverse recovery charge, and improves the reverse recovery speed and switching reliability.

[0034] (3) The combination of the asymmetric trench structure and the N-type current spreading layer optimizes the electric field distribution, reducing the on-resistance while maintaining a high breakdown voltage, thus breaking the contradiction between breakdown voltage and conduction performance in traditional devices.

[0035] (4) By reducing the gate charge density and optimizing the capacitance characteristics, the energy loss during the switching process is reduced, and the response speed and efficiency of the device in high-frequency applications are enhanced.

[0036] (5) The synergistic effect of the floating region and the composite electrode alleviates the bipolar degradation effect caused by carrier injection, prolongs the device life, and is suitable for harsh working conditions such as high temperature and high pressure.

[0037] Other advantages, objects, and features of the present invention will be described in part in the following description and, in part, will be apparent to those skilled in the art upon examination of the following description or may be learned from practice of the present invention. The objects and other advantages of the present invention may be realized and obtained through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention will be described in detail below with reference to the accompanying drawings, in which:

[0039] Figure 1 The overall structure of a SiC MOSFET device provided by one embodiment of the present invention;

[0040] Figure 2 The IV characteristic curve comparison of the SiC MOSFET of the present invention and the traditional asymmetric trench SiC MOSFET when the gate voltage is 15V and -5V, as well as the IV characteristic curve comparison of the two SiC MOSFETs at I DS =-200A / cm 2 Time-space hole distribution map;

[0041] Figure 3 Figures 2 and 3 show the total current density distribution of a conventional asymmetric trench SiC MOSFET and a SiC MOSFET of the present invention during forward conduction. (a) shows the total current density distribution of a conventional asymmetric trench SiC MOSFET during forward conduction. (b) shows the total current density distribution of a SiC MOSFET of the present invention.

[0042] Figure 4 Graph showing the current distribution of the SiC MOSFET of the present invention during reverse conduction;

[0043] Figure 5 Comparison of the breakdown characteristic curves of the two devices and the breakdown electric field distribution of the two SiC MOSFETs;

[0044] Figure 6 For different N CSL and W to RE-ATMOS V cut-in The influence diagram of different N CSL V for RE-ATMOS cut-in (b) The effect of different W on the V of RE-ATMOS cut-in Influence diagram of

[0045] Figure 7 For different W CSL and N CSL The breakdown voltage (BV), specific on-resistance (R on,sp ) and Q GD The influence of different W CSL The breakdown voltage (BV), specific on-resistance (R on,sp ) and Q GD (b) for different N CSL The breakdown voltage (BV), specific on-resistance (Ron,sp ) and Q GD the impact of;

[0046] Figure 8 A comparison diagram of gate charge characteristics of the SiC MOSFET of the present invention and the traditional asymmetric trench SiC MOSFET;

[0047] Figure 9 A comparison diagram of reverse recovery characteristics of the SiC MOSFET of the present invention and a conventional asymmetric trench SiC MOSFET;

[0048] Figure 10 The switching characteristic curves of the SiC MOSFET of the present invention and the traditional asymmetric trench SiC MOSFET; (a) is the dynamic V DS Changes with test time; (b) dynamic I DS Changes with test time; (c) is the test circuit diagram;

[0049] Figure 11 Schematic diagram of the main process flow of the SiC MOSFET device of the present invention; (a) epitaxial growth; (b) N+ source and P well implantation; (c) trench etching; (d) P base implantation; (e) isolation oxidation; (f) gate oxidation; (g) polysilicon gate deposition; (h) metallization;

[0050] Figure numerals: 1-gate, 2-source, 3-drain, 4-composite electrode, 5-trench gate, 6-auxiliary trench gate, 7-first oxide layer, 8-second oxide layer, 9-source N+ region, 10-source P+ region, 11-floating P+ region, 12-floating N+ region, 13-P-base, 14-P-ch, 15-first P-well, 16-second P-well, 17-N-CSL, 18-N-Drift, 19-N+SUB. DETAILED DESCRIPTION

[0051] The following describes the embodiments of the present invention by means of specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present invention, and the following embodiments and features in the embodiments can be combined with each other without conflict.

[0052] Among them, the accompanying drawings are only for illustrative purposes and represent only schematic diagrams rather than actual pictures, and should not be understood as limiting the present invention. In order to better illustrate the embodiments of the present invention, some parts of the accompanying drawings may be omitted, enlarged or reduced, and do not represent the dimensions of actual products. For those skilled in the art, it is understandable that some well-known structures and their descriptions may be omitted in the accompanying drawings.

[0053] The same or similar numbers in the drawings of the embodiments of the present invention correspond to the same or similar parts; in the description of the present invention, it should be understood that if there are terms such as "upper", "lower", "left", "right", "front", "back", etc. indicating directions or positional relationships, they are based on the directions or positional relationships shown in the drawings. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operate in a specific direction. Therefore, the terms describing the positional relationship in the drawings are only used for illustrative purposes and cannot be understood as limiting the present invention. For ordinary technicians in this field, the specific meanings of the above terms can be understood according to specific circumstances.

[0054] like Figure 1 As shown, an asymmetric trench SiCMOSFET device with low resistance and Miller capacitance provided by an embodiment of the present invention is composed of a gate 1, a source 2, a drain 3, a composite electrode 4, a trench gate 5, an auxiliary trench gate 6, a first oxide layer 7, a second oxide layer 8, a source N+ region 9, a source P+ region 10, a floating P+ region 11, a floating N+ region 12, a P-base 13, a P-ch 14, a first P-well 15, a second P-well 16, an N-CSL 17, an N-Drift 18, and an N+SUB 19.

[0055] The trench gate 5 , the auxiliary trench gate 6 , the source P+ region 10 , the P-ch 14 and the first P-well 15 form a depletion-type PMOS.

[0056] The source P+ region 9 is located on the upper surface of P-ch14 and is connected to the source 2. It has a thickness of 0.25 μm and a width of 0.2 μm. It is doped with P-type impurity aluminum (Al) with a doping concentration of 1×10 20 cm -3 The first P-well 15 is located on the lower surface of the P-ch 12, with a thickness of 1.55 μm and a width of 1.45 μm. It is doped with P-type impurity aluminum (Al) with a doping concentration of 1.0×10 19 cm -3The source P+ region 10, P-ch 12, and first P-well 15 are arranged vertically to form a depletion-mode PMOS. The P-ch 12 has a thickness of 0.5 μm and a width of 0.3 μm. The trench gate 5 and the auxiliary trench gate 6 are located on either side of the source P+ region 10, P-ch 12, and first P-well 15, respectively. The sidewalls and bottom of the trench gate 5 are completely wrapped by the first oxide layer 7, and the sidewalls and bottom of the auxiliary trench gate 6 are completely wrapped by the second oxide layer 8. The thickness of the first oxide layer 7 and the second oxide layer 8 are both 50 nm. They are made of silicon dioxide (SiO2) and serve as gate dielectric layers to isolate the polysilicon gate from the semiconductor region. The lower surfaces of the trench gate 5 and the auxiliary trench gate 6 are adjacent to the first P-well 15. They are both 1.1 μm thick and 0.7 μm wide, respectively. PolySi is doped with N-type impurities phosphorus (P) with a doping concentration of 1×10 20 cm -3 .

[0057] The gate 1 is connected to the trench gate 5 and the auxiliary trench gate 6 . The trench gate 5 and the auxiliary trench gate 6 are located inside the first oxide layer 7 and the second oxide layer 8 , respectively.

[0058] The source 2 is connected to the source N+ region 9, the source P+ region 10 and the second P-well 16, and is located on the upper surface of the source N+ region 9, the source P+ region 10 and the second P-well 16. The source N+ region 9 has a thickness of 0.25 μm and a width of 0.5 μm. It is doped with N-type impurity nitrogen (N) with a doping concentration of 1×10 20 cm -3 The second P-well 16 has a thickness of 1.55 μm and a width of 0.6 μm, and is doped with P-type impurity aluminum (Al) with a doping concentration of 1×10 19 cm -3 .

[0059] The drain 3 is connected to the N+SUB19 and is located on the lower surface of the N+SUB19. The N+SUB19 has a thickness of 5 μm and a width of 3.2 μm. It is doped with N-type impurity nitrogen (N) with a doping concentration of 1×10 20 cm -3 ;

[0060] The composite electrode 4 is connected to the floating P+ region 11 and the floating N+ region 12 and is located on the upper surface of the floating P+ region 11 and the floating N+ region 12. The floating P+ region 11 has a thickness of 0.25 μm and a width of 0.15 μm. It is doped with P-type impurity aluminum (Al) with a doping concentration of 1×10 20 cm -3 The floating N+ region 11 has a thickness of 0.25 μm and a width of 0.25 μm, and is doped with N-type impurity nitrogen (N) with a doping concentration of 1×10 20 cm -3

[0061] In addition, the device includes a source N+ region 9, a P-base 13, a second P-well 16, an N-CSL 17, an N-Drift 18, and an N+SUB 19. The source N+ region 9 is located on the upper surface of the P-base 13, and the left surfaces of the source N+ region 9 and the P-base 13 are adjacent to the right surface of the second P-well 16, and the right surface is adjacent to the left surface of the first oxide layer 7. The source N+ region 8 has a thickness of 0.25 μm and a width of 0.5 μm, and is doped with N-type impurity nitrogen (N) with a doping concentration of 1×10 20 cm -3 N-CSL17 is located between the first and second P-wells on both sides, and its lower surface is adjacent to the upper surface of N-Drift18. N-CSL14 has a thickness of 1.6μm and a width of 3.2μm. It is doped with N-type impurity nitrogen (N) with a doping concentration of 2.5×10 16 cm -3 The upper surface of N-Drift18 is located on the lower surface of N-CSL14, and the lower surface of N-Drift18 is located on the upper surface of N+SUB19. N-Drift18 has a thickness of 11μm and a width of 3.2μm. It is doped with N-type impurity nitrogen (N) with a doping concentration of 7×10 15 cm -3 .

[0062] In the present invention, simulation tests are performed on the proposed SiC MOSFET device to verify the excellent performance of the device proposed in the present invention, as follows:

[0063] like Figure 2 As shown, the comparison of the IV characteristics of the SiC MOSFET device of the present invention and the traditional asymmetric trench SiC MOSFET device in the first and third quadrants when the gate voltage is 15V and -5V, as well as the comparison of the IV characteristics of the two SiC MOSFETs in I DS =-200A / cm 2 From the time-space hole distribution diagram, it can be seen that the device of the present invention has better output characteristics and lower third quadrant turn-on voltage than the traditional asymmetric trench SiC MOSFET device.

[0064] Figure 3 The total current density distribution diagrams of the conventional asymmetric trench SiC MOSFET and the SiC MOSFET of the present invention during the forward conduction process; (a) is the conventional asymmetric trench SiC MOSFET during the forward conduction process; (b) is the total current density distribution diagram of the SiC MOSFET of the present invention; Figure 3It can be seen that compared with the traditional asymmetric trench SiC MOSFET device, the device of the present invention has a larger conduction path. In the J-FET region, the current width of the device of the present invention is 0.44μm, and the current width of the traditional asymmetric trench SiC MOSFET is 0.41μm. This difference is attributed to the integration of the depletion-type PMOS. When the gate is connected to a positive voltage of 15V, the P-ch is depleted, and the source P+ region connected to the source is disconnected from the first P-well, causing the first P-well to float and increase its potential. As a result, the depletion region width is reduced, the JFET resistance is reduced, and the current flowing to the N-Drift is increased. Therefore, compared with the traditional asymmetric trench SiC MOSFET, the device of the present invention has a lower specific on-resistance.

[0065] like Figure 4 The figure shows the total current density distribution under the third quadrant conditions. As can be seen from the figure, during the reverse conduction process, electrons and holes recombine at the recombination electrode, and the electron current flows to the drain through the recombination electrode, indicating that the body diode in this structure is well suppressed and will not conduct.

[0066] like Figure 5 As shown in FIG, a comparison of the breakdown characteristic curves of the two devices is shown. The two devices exhibit similar BV characteristics. Figure 5 The breakdown electric field distribution of the two SiC MOSFETs is also shown. The maximum breakdown electric field of both devices is at P-well, and the gate oxide layer electric field of the SiC MOSFET is less than 3MV / cm, which is conducive to enhancing the long-term reliability of the gate oxide layer.

[0067] Figure 6 For different N CSL and W to RE-ATMOS V cut-in The influence diagram of different N CSL V for RE-ATMOS cut-in (b) The effect of different W on the V of RE-ATMOS cut-in The influence diagram of Figure 6 It can be seen that with the increase of N-CSL concentration and W, V cut-in There is a trend of decreasing.

[0068] Figure 7 For different N-CSL widths (W CSL ) and N-CSL concentration (N CSL ) for the breakdown voltage (BV) and specific on-resistance (R on,sp ) and Q GD The influence of different W CSL The breakdown voltage (BV), specific on-resistance (Ron,sp ) and Q GD (b) for different N CSL The breakdown voltage (BV) and specific on-resistance (R on,sp ) and Q GD The impact of Figure 7 It can be seen that with the W CSL and N CSL With the increase of the device's BV and on-resistance, the device's BV and on-resistance are both decreasing, and Q GD It is on an upward trend.

[0069] like Figure 8 The figure shows a comparison of the gate charge characteristics of the SiC MOSFET device of the present invention and the conventional asymmetric trench SiC MOSFET device. Figure 9 A test circuit is also inserted. Figure 9 It can be seen from the figure that the gate-drain charge (Q GD ) is the same as that of conventional asymmetric trench SiC MOSFET devices.

[0070] like Figure 9 The reverse recovery characteristics of C-ATMOS and RE-ATMOS are shown in Figure 2. The inset shows the double-pulse test circuit used for device simulation. The results show that the reverse recovery charge (Q RR ) is 0.96μC / cm2, and the peak reverse recovery current (I RRM ) is 142A / cm 2 . And the Q of C-ATMOS RR and I RRM and 4.51 μC / cm 2 and 283A / cm 2 This advantage of RE-ATMOS is attributed to the integration of the recombination electrode, which suppresses minority carrier injection and thus alleviates the bipolar degradation effect during the third quadrant conduction process.

[0071] like Figure 10 The following table shows the periodic switching characteristics of C-ATMOSh and RE-ATMOS, including the dynamic drain-source V DS and I DS Waveform. (a) shows the change of dynamic VDS with test time; (b) shows the change of dynamic IDS with test time; (c) shows the test circuit diagram. Bus voltage V bu s is set to 600V (50% of BV). The load inductance L in the power loop M and stray inductance L SSet to 150μH and 10nH respectively. Obviously, during each on-time, the dynamic V DS are lower than C-ATMOS, which indicates that R on,sp This is consistent with Figure 2 The static conduction characteristics are consistent.

[0072] The following table compares the relevant parameters of the device of the present invention and the traditional asymmetric trench SiC MOSFET device.

[0073] Table 1

[0074] Proposed C-ATMOS (traditional device) Ron,sp <![CDATA[1.88mΩ·cm 2 ]]> <![CDATA[1.97mΩ·cm 2 ]]> <![CDATA[Q GD ]]> <![CDATA[106.2nC / cm 2 ]]> <![CDATA[106.2nC / cm 2 <!-- 5 -->]]> BV 1327V 1334V <![CDATA[Ron,sp×Q GD ]]> 200mΩ·nC 209mΩ·nC

[0075] In another embodiment of the present invention, a process flow for the device of the present invention is provided. Considering the feasibility of the process, most of the process steps are compatible with the general manufacturing process of traditional asymmetric trench SiC MOSFET devices. Figure 11 Schematic diagram of the main process flow of the SiC MOSFET device of the present invention; (a) epitaxial growth; (b) N+ source and P well implantation; (c) trench etching; (d) P base implantation; (e) isolation oxidation; (f) gate oxidation; (g) polysilicon gate deposition; (h) metallization. The main process flow of the device proposed in the present invention includes: epitaxial growth, N+ source and P well implantation, trench etching, P base implantation, isolation oxidation, gate oxidation, polysilicon gate deposition and metallization. The difference is that in the process flow of this embodiment, the P-ch needs to be etched and epitaxially filled.

[0076] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not limiting. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present invention can be modified or replaced by equivalents without departing from the purpose and scope of the technical solutions, which should all be included in the scope of the claims of the present invention.

Claims

1. An asymmetric trench SiC MOSFET device with a composite electrode, characterized in that: The device includes: N+ substrate (19); An N-Drift layer (18) formed on a first surface of the N+ substrate (19); an N-CSL layer (17) formed on a surface of the N-Drift layer (18); a depletion-type PMOS structure formed on a first side surface of the N-CSL layer (17); a second P-well (16) formed on a second side surface of the N-CSL layer (17); A trench gate (5) and an auxiliary trench gate (6) are formed on the surface of the depletion-type PMOS structure and located on both sides thereof, wherein the trench gate (5) and the auxiliary trench gate (6) are respectively surrounded by a first oxide layer (7) and a second oxide layer (8); A P-base (13) formed on the surface of the N-CSL layer (17) and located between the second P-well (16) and the trench gate (5); A source N+ region (9) formed on the surface of the P-base (13) and located between the second P-well (16) and the trench gate (5); A floating P+ region (11) formed on the surface of the second P-well (16); A floating N+ region (12) formed on the surface of the N-CSL layer (17); A composite electrode (4) formed on the surface of the floating P+ region (11) and the floating N+ region (12); A source electrode (2) is formed on the top of the device, wherein the source electrode (2) is electrically connected to the source N+ region (9) and the second P-well (16); A drain electrode (3) is formed on the second surface of the N+ substrate (19).

2. The asymmetric trench SiC MOSFET device with a composite electrode according to claim 1, wherein: The depletion-mode PMOS structure comprises: a first P-well (15) formed on a first side surface of the N-CSL layer (17); A P-ch layer (14) formed on the surface of the first P-well (15) and located between the trench gate (5) and the auxiliary trench gate (6); A source P+ region (10) is formed on the surface of the P-ch layer (14) and connected to the source electrode (2).

3. The asymmetric trench SiC MOSFET device with a composite electrode according to claim 1 or 2, characterized in that: The thickness of the first oxide layer (7) and the second oxide layer (8) is 50 nm, and the material is silicon dioxide.

4. The asymmetric trench SiC MOSFET device with a composite electrode according to claim 3, characterized in that: During reverse conduction, electrons pass through the drain electrode (3) and recombine with holes at the recombination electrode (4), thereby suppressing conduction of the body diode.

5. The asymmetric trench SiC MOSFET device with a composite electrode according to claim 1, wherein: The doping concentration of the floating P+ region (11) is 1×10 20 cm -3 The doping concentration of the floating N+ region (12) is 1×10 20 cm -3 .

6. The asymmetric trench SiC MOSFET device with a composite electrode according to claim 1, wherein: The width of the trench gate (5) and the auxiliary trench gate (6) are both 0.7 μm, the depth is 1.1 μm, and the concentration of phosphorus doped in the polysilicon gate is 1×10 20 cm -3 .

7. The asymmetric trench SiC MOSFET device with a composite electrode according to claim 1, characterized in that: The doping concentration of the N-CSL layer (17) is 2.5×10 16 cm -3 , with a thickness of 1.6μm.

8. The asymmetric trench SiC MOSFET device with a composite electrode according to claim 1, wherein: The composite electrode (4) forms an ohmic contact with the floating P+ region (11) and the floating N+ region (12), and is made of aluminum or copper.

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