Trench gate super junction device and manufacturing method thereof

Abstract

The invention provides a trench gate super junction device and a manufacturing method thereof. The method comprises the following steps: forming a first semiconductor epitaxial layer of a first conductive type; forming a first mask layer and a second mask layer, etching the first semiconductor epitaxial layer to form a plurality of deep grooves, and forming first conductive type columns among the deep grooves; the second mask layer is removed, and meanwhile part of the first mask layer is removed in the horizontal direction; filling a second semiconductor epitaxial layer of a second conductive type in the deep trench to form a second conductive type column, and forming a body region between the first mask layers; and removing the first mask layer, and forming a trench gate between the adjacent body regions. Compared with the prior art, a body region photomask and an ion implantation process do not need to be adopted when the body region is formed, a gate trench photomask does not need to be adopted when the gate trench is formed, one ion implantation process, one body region photomask and one gate trench photomask are omitted, and the cost is effectively reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor integrated circuits, and in particular to a trench gate super junction device and a manufacturing method thereof. Background Art

[0002] Superjunction devices are constructed by growing a lightly doped N-type epitaxial layer on a heavily N-type substrate. Trench etching, epitaxial growth, and chemical mechanical polishing are then used to form alternating P-type and N-type pillars on this N-type epitaxial layer. Carrier depletion between the P-type and N-type pillars results in a device with high breakdown voltage and low on-resistance. Trench-gate superjunction devices use trench gates instead of planar gates, further improving the device's dynamic and static performance.

[0003] However, in the existing trench gate super junction device manufacturing process, the formation of the trench gate and the body region both require photolithography process definition, which is not conducive to cost reduction. Summary of the Invention

[0004] The object of the present invention is to provide a trench gate super junction device and a manufacturing method thereof, which reduces the use of masks, reduces the ion implantation process, and effectively reduces costs.

[0005] To solve the above technical problems, according to a first aspect of the present invention, a method for manufacturing a trench gate super junction device is provided, comprising the following steps:

[0006] providing a substrate, and forming a first semiconductor epitaxial layer of a first conductivity type on the substrate;

[0007] forming a first mask layer and a second mask layer on the first semiconductor epitaxial layer, and etching the first semiconductor epitaxial layer using the second mask layer and the first mask layer as masks to form a plurality of deep trenches, wherein the first semiconductor epitaxial layer between the plurality of deep trenches forms a first conductivity type pillar;

[0008] removing the second mask layer and simultaneously removing a portion of the first mask layer in a horizontal direction;

[0009] Filling the deep trench with a second semiconductor epitaxial layer of a second conductivity type to form a second conductivity type pillar, and forming a third semiconductor epitaxial layer of a second conductivity type on the second conductivity type pillar and a portion of the first conductivity type pillar between the first mask layer to form a body region, wherein the second conductivity type is opposite to the first conductivity type;

[0010] removing the first mask layer to form a gate trench between adjacent body regions; and

[0011] A trench gate is formed in the gate trench.

[0012] Optionally, the method of forming the second conductive type pillar and the body region includes:

[0013] filling a second semiconductor epitaxial layer of the second conductivity type in the deep trench by an epitaxial process, wherein the second semiconductor epitaxial layer fills the deep trench and an upper surface of the second semiconductor epitaxial layer is higher than an upper surface of the first mask layer;

[0014] planarizing the second semiconductor epitaxial layer until the first mask layer is exposed, and forming a second conductivity type pillar in the deep trench; and

[0015] A third semiconductor epitaxial layer of the second conductivity type is formed on the second conductivity type pillars and a portion of the first conductivity type pillars between adjacent first mask layers through an epitaxial process to form a body region.

[0016] Optionally, the method of forming the second conductive type pillar and the body region includes:

[0017] Filling the deep trench with a second semiconductor epitaxial layer of the second conductivity type through an epitaxial process, wherein the second semiconductor epitaxial layer fills the deep trench to form a second conductivity type pillar;

[0018] Continuing the epitaxial process to form a third semiconductor epitaxial layer of the second conductivity type on the second conductivity type pillars between adjacent first mask layers and a portion of the first conductivity type pillars, wherein the upper surface of the third semiconductor epitaxial layer is higher than the upper surface of the first mask layer; and

[0019] The third semiconductor epitaxial layer is planarized until the first mask layer is exposed, and a body region is formed between adjacent first mask layers.

[0020] Optionally, a wet etching process is used to remove the second mask layer, and the width of the first mask layer in the horizontal direction is controlled by controlling the wet etching amount, thereby controlling the width of the gate trench.

[0021] Optionally, the first mask layer includes an oxide layer, and the second mask layer includes a nitride layer and an oxide layer sequentially located on the first mask layer.

[0022] Optionally, the method of forming a trench gate in the gate trench includes:

[0023] forming a gate oxide layer, wherein the gate oxide layer covers the sidewalls and the bottom of the gate trench and the upper surface of the body region;

[0024] filling gate polysilicon in the gate trench; and

[0025] The gate oxide layer outside the gate trench is removed.

[0026] Optionally, the gate oxide layer is formed by a thermal oxidation process.

[0027] Optionally, the first conductivity type is N type, and the second conductivity type is P type; or, the first conductivity type is P type, and the second conductivity type is N type.

[0028] To solve the above technical problems, according to a second aspect of the present invention, a trench gate super junction device is provided, which is manufactured using the above-mentioned method for manufacturing a trench gate super junction device. The trench gate super junction device includes:

[0029] substrate;

[0030] A first semiconductor epitaxial layer of a first conductivity type is located on the substrate and has a plurality of deep trenches, wherein the first semiconductor epitaxial layer between the deep trenches forms a first conductivity type pillar;

[0031] A second semiconductor epitaxial layer of a second conductivity type is filled in each of the deep trenches to form a second conductivity type pillar; the second conductivity type is opposite to the first conductivity type;

[0032] A third semiconductor epitaxial layer of the second conductivity type is located on the second conductivity type pillar and a portion of the first conductivity type pillar to form a body region; a gate trench is formed between adjacent body regions; and

[0033] A trench gate is located in the gate trench.

[0034] In the trench-gate superjunction device and its fabrication method provided by the present invention, after a second semiconductor epitaxial layer of a second conductivity type is filled in the deep trench to form a second conductivity type pillar, a third semiconductor epitaxial layer of a second conductivity type is epitaxially formed on the second conductivity type pillars and a portion of the first conductivity type pillars between the first mask layer to form a body region. The first mask layer is then removed to form a gate trench between adjacent body regions. Compared to the prior art, the present invention does not require a body region mask or ion implantation process when forming the body region, nor does it require a gate trench mask when forming the gate trench. This saves an ion implantation process, a body region mask, and a gate trench mask, effectively reducing costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 It is a schematic flow chart of a method for manufacturing a trench gate super junction device provided by one embodiment of the present invention.

[0036] Figures 2 to 11 It is a structural schematic diagram of each step of the method for manufacturing a trench gate super junction device provided in the first embodiment of the present invention.

[0037] Figures 12 to 16It is a structural schematic diagram of each step of the method for manufacturing a trench gate super junction device provided in the second embodiment of the present invention.

[0038] Description of reference numerals:

[0039] 10-first semiconductor epitaxial layer; 11-first mask layer; 12-second mask layer; 13-deep trench; 14-first conductive type column; 15-second semiconductor epitaxial layer; 16-second conductive type column; 17-body region; 18-gate trench; 19-trench gate; 191-gate oxide layer; 192-gate polysilicon; 20-third semiconductor epitaxial layer. DETAILED DESCRIPTION

[0040] In the existing trench gate super junction device manufacturing process, after forming the first conductive type column and the second conductive type column, it is first necessary to use a body region mask to perform ion implantation to form the body region, and then it is necessary to use a gate trench mask to perform etching to form the gate trench. That is, the formation of the body region and the gate trench both require photolithography process definition, and the formation of the body region also requires ion implantation process. Its manufacturing method is not conducive to cost reduction.

[0041] In response to the above problems, the present invention provides a method for manufacturing a trench gate super junction device, comprising the following steps: providing a substrate, forming a first semiconductor epitaxial layer of a first conductivity type on the substrate; forming a first mask layer and a second mask layer on the first semiconductor epitaxial layer, etching the first semiconductor epitaxial layer using the second mask layer and the first mask layer as masks to form a plurality of deep trenches, wherein the first semiconductor epitaxial layer between the plurality of deep trenches forms a first conductivity type column; removing the second mask layer, and at the same time removing a portion of the first mask layer in the horizontal direction; filling the deep trench with a second semiconductor epitaxial layer of a second conductivity type to form a second conductivity type column, forming a third semiconductor epitaxial layer of a second conductivity type on the second conductivity type column between the first mask layer and a portion of the first conductivity type column to form a body region, wherein the second conductivity type is opposite to the first conductivity type; removing the first mask layer to form a gate trench between adjacent body regions; and forming a trench gate in the gate trench.

[0042] Correspondingly, the present invention also provides a trench gate super junction device, which is manufactured using the manufacturing method of the trench gate super junction device as described above, and the trench gate super junction device includes: a substrate; a first semiconductor epitaxial layer of a first conductive type, located on the substrate and having multiple deep trenches, the first semiconductor epitaxial layer between the deep trenches forming a first conductive type column; a second semiconductor epitaxial layer of a second conductive type, filled in each of the deep trenches to form a second conductive type column; the second conductive type is opposite to the first conductive type; a third semiconductor epitaxial layer of the second conductive type, located on the second conductive type column and part of the first conductive type column to form a body region; a gate trench is formed between adjacent body regions; and a trench gate, located in the gate trench.

[0043] In the trench-gate superjunction device and its fabrication method provided by the present invention, after a second semiconductor epitaxial layer of a second conductivity type is filled in the deep trench to form a second conductivity type pillar, a third semiconductor epitaxial layer of a second conductivity type is epitaxially formed on the second conductivity type pillars and a portion of the first conductivity type pillars between the first mask layer to form a body region. The first mask layer is then removed to form a gate trench between adjacent body regions. Compared to the prior art, the present invention does not require a body region mask or ion implantation process when forming the body region, nor does it require a gate trench mask when forming the gate trench. This saves an ion implantation process, a body region mask, and a gate trench mask, effectively reducing costs.

[0044] To make the objects, advantages, and features of the present invention more clearly apparent, the present invention is further described below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale. They are only used to conveniently and clearly assist in illustrating the purposes of the embodiments of the present invention. In addition, the structures shown in the drawings are often part of the actual structure. In particular, different drawings may need to illustrate different focuses and sometimes use different scales.

[0045] As used in the present invention, the singular forms "a", "an" and "the" include plural objects, unless the content clearly indicates otherwise. As used in the present invention, the term "or" is generally used in a sense including "and / or", unless the content clearly indicates otherwise. As used in the present invention, the term "several" is generally used in a sense including "at least one", unless the content clearly indicates otherwise. As used in the present invention, the term "at least two" is generally used in a sense including "two or more", unless the content clearly indicates otherwise. In addition, the terms "first", "second" and "third" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first", "second" and "third" may explicitly or implicitly include one or at least two of the features, unless the content clearly indicates otherwise.

[0046] Figure 1 It is a schematic flow chart of a method for manufacturing a trench gate super junction device provided by one embodiment of the present invention.

[0047] like Figure 1 As shown, the method for manufacturing a trench gate super junction device includes the following steps:

[0048] S1: providing a substrate, and forming a first semiconductor epitaxial layer of a first conductivity type on the substrate;

[0049] S2: forming a first mask layer and a second mask layer on the first semiconductor epitaxial layer, and etching the first semiconductor epitaxial layer using the second mask layer and the first mask layer as masks to form a plurality of deep trenches, wherein the first semiconductor epitaxial layer between the plurality of deep trenches forms first conductivity type pillars;

[0050] S3: removing the second mask layer and simultaneously removing a portion of the first mask layer in a horizontal direction;

[0051] S4: filling a second semiconductor epitaxial layer of a second conductivity type in the deep trench to form a second conductivity type pillar, and forming a third semiconductor epitaxial layer of a second conductivity type on the second conductivity type pillar between the first mask layer and a portion of the first conductivity type pillar to form a body region, wherein the second conductivity type is opposite to the first conductivity type;

[0052] S5: removing the first mask layer to form a gate trench between adjacent body regions; and

[0053] S6: forming a trench gate in the gate trench.

[0054] In the method for manufacturing a trench-gate superjunction device provided by the present invention, after a second semiconductor epitaxial layer of a second conductivity type is filled in the deep trench to form a second conductivity type pillar, a third semiconductor epitaxial layer of a second conductivity type is epitaxially formed on the second conductivity type pillars and a portion of the first conductivity type pillars between the first mask layer to form a body region. The first mask layer is then removed to form a gate trench between adjacent body regions. Compared to the prior art, the present invention does not require a body region mask or ion implantation process when forming the body region, nor does it require a gate trench mask when forming the gate trench. This saves an ion implantation process, a body region mask, and a gate trench mask, effectively reducing costs.

[0055] The following describes this in detail through two embodiments.

[0056] [Example 1]

[0057] Figures 2 to 11 This is a schematic diagram of the steps of the method for manufacturing a trench gate super junction device according to the first embodiment of the present invention. Figure 1 、 Figures 2 to 11 The method for manufacturing the trench gate super junction device provided by the embodiment of the present invention is described in detail.

[0058] In step S1, please refer to Figure 2 As shown, a substrate (not shown) is provided, and a first semiconductor epitaxial layer 10 of a first conductivity type is formed on the substrate.

[0059] The substrate may be made of silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium, or may be silicon-on-insulator (SOI) or germanium-on-insulator (GOI), or other materials such as III-V compounds such as gallium arsenide. In this embodiment, the substrate is a silicon substrate.

[0060] In this embodiment, a first semiconductor epitaxial layer 10 is epitaxially grown on the substrate, and impurity ions of the first conductive type are doped during the epitaxial growth of the first semiconductor epitaxial layer 10 to form a first semiconductor epitaxial layer 10 of the first conductive type having a desired thickness and a desired doping concentration. The first semiconductor epitaxial layer 10 is lightly doped relative to the substrate, that is, when the first semiconductor epitaxial layer 10 and the substrate have the same conductivity type, the doping concentration of the first semiconductor epitaxial layer 10 is lower than the doping concentration of the substrate.

[0061] In another other embodiment, a carrier may be provided first, and a first semiconductor epitaxial layer 10 may be formed on the carrier by a process such as deposition or epitaxial growth, and then the first semiconductor epitaxial layer 10 may be bonded to the substrate by a bonding process, and the carrier wafer may be further removed by a process such as chemical mechanical polishing or carrier wafer peeling, thereby forming the first semiconductor epitaxial layer 10 on the substrate.

[0062] In one embodiment of the present invention, the substrate is an N-type substrate, the first conductivity type is N-type, the first semiconductor epitaxial layer 10 is an N-type epitaxial layer, and the N-type impurity element is, for example, at least one of phosphorus, arsenic, and antimony. Of course, the first conductivity type may also be P-type, the substrate is a P-type substrate, and the first semiconductor epitaxial layer 10 is a P-type epitaxial layer.

[0063] In step S2, please refer to Figures 2 to 4 As shown, a first mask layer 11 and a second mask layer 12 are formed on the first semiconductor epitaxial layer 10, and the first semiconductor epitaxial layer 10 is etched using the second mask layer 12 and the first mask layer 11 as masks to form a plurality of deep trenches 13, and the first semiconductor epitaxial layer 10 between the plurality of deep trenches 13 forms a first conductive type column 14.

[0064] In one embodiment, please refer to Figure 2 As shown, first, a first mask layer 11 and a second mask layer 12 are formed on the first semiconductor epitaxial layer 10, and then a photoresist layer is coated on the second mask layer 12. The photoresist layer is exposed and developed to form a patterned photoresist layer, defining the formation area of ​​each deep trench 13. Then, the patterned photoresist layer is used as a mask to etch the second mask layer 12 and the first mask layer 11. The etching stops on the surface of the first semiconductor epitaxial layer 10 to form a plurality of openings in the second mask layer 12 and the first mask layer 11. The openings define the formation area of ​​the deep trench 13. Then, the patterned photoresist layer is removed to form the following. Figure 3 Then, using the etched second mask layer 12 and the first mask layer 11 as masks, a portion of the thickness of the first semiconductor epitaxial layer 10 is etched to form a plurality of deep trenches 13. The first semiconductor epitaxial layer 10 between adjacent deep trenches 13 forms first conductivity type columns 14. At this time, the first conductivity type columns 14 and the deep trenches 13 between the deep trenches 13 form an alternating structure.

[0065] In one embodiment, a dry etching process is used to etch the second mask layer 12 and the first mask layer 11, and dry etching is used to etch the first semiconductor epitaxial layer 10 to form a deep trench 13. The depth of the deep trench 13 can be between 10μm and 100μm, and the width can be between 1μm and 10μm, but is certainly not limited thereto. It is understandable that the width and depth of the deep trench 13 can be designed according to the performance requirements of the superjunction device. The deeper the depth of the deep trench 13, the higher the breakdown voltage of the device. The smaller the width of the deep trench 13, the smaller the on-resistance that the device can achieve at the same breakdown voltage. In addition, the morphology of the sidewalls of the formed deep trench 13 can be controlled by controlling the etching parameters. It can be an inclined sidewall with an angle of more than 80 degrees or a vertical sidewall of about 90 degrees.

[0066] In one embodiment, the first mask layer 11 includes an oxide layer, and the second mask layer 12 includes a nitride layer and an oxide layer sequentially located on the first mask layer 11. For example, the thickness of the first mask layer 11 may be between The thickness of the nitride layer in the second mask layer 12 can be between The thickness of the oxide layer in the second mask layer 12 can be between between.

[0067] In step S3, please continue to refer to Figure 4 As shown, the second mask layer 12 is removed, and at the same time, a portion of the first mask layer 11 is removed in the horizontal direction.

[0068] In this embodiment, a wet etching process is used to remove the second mask layer 12. When the second mask layer 12 is removed, the first mask layer 11 is formed in the horizontal direction ( Figure 4 The horizontal direction (as shown) will also be partially etched to narrow its width. The width of the first mask layer 11 in the horizontal direction can be controlled by controlling the wet etching amount, thereby controlling the width of the gate trench formed subsequently.

[0069] In step S4, please refer to Figure 7 As shown, a second semiconductor epitaxial layer of a second conductive type is filled in the deep trench 13 to form a second conductive type column 16, and a third semiconductor epitaxial layer of a second conductive type is formed between the second conductive type column 16 and part of the first conductive type column 14 between the first mask layer 11 to form a body region 17, and the second conductive type is opposite to the first conductive type.

[0070] In this embodiment, please first refer to Figure 5As shown, a second semiconductor epitaxial layer 15 of a second conductive type is epitaxially grown in the deep trench 13 by any suitable epitaxial growth process, the second semiconductor epitaxial layer 15 fills the deep trench 13 and the upper surface of the second semiconductor epitaxial layer 15 is higher than the upper surface of the first mask layer 11. Exemplarily, the upper surface of the second semiconductor epitaxial layer 15 is about 1μm to 5μm higher than the upper surface of the first mask layer 11. Then, the second semiconductor epitaxial layer 15 is planarized until the first mask layer 11 is exposed, for example, by chemical mechanical polishing, and the first mask layer 11 serves as a polishing stop layer, thereby forming a second conductive type column 16 in the deep trench 13, forming a structure as shown in FIG. Figure 6 In the structure shown, the second conductivity type pillars 16 (i.e., the second semiconductor epitaxial layer filling the deep trenches 13) and the first conductivity type pillars 14 (i.e., the first semiconductor epitaxial layer between the deep trenches 13) are arranged alternately. It is understood that because the chemical mechanical polishing process cannot accurately stop at the same height as the first mask layer 11, there will generally be a certain amount of over-polishing, which will polish the second semiconductor epitaxial layer 15 adjacent to the first mask layer 11 to below the first mask layer 11. As a result, the upper surface of the second conductivity type pillars 16 is lower than the upper surface of the first mask layer 11.

[0071] When the first conductivity type is N-type and the second conductivity type is P-type, the second semiconductor epitaxial layer 15 filled in the deep trench 13 is a P-type column, and the first semiconductor epitaxial layer 10 between the deep trenches 13 is an N-type column. The P-type columns and the N-type columns are arranged alternately to form a super junction structure. Each N-type column and its adjacent P-type column can form a super junction unit. The carriers between the P-type column and the N-type column are mutually depleted, which can be used to form a device with a higher breakdown voltage.

[0072] Then please refer to Figure 7 As shown, a third semiconductor epitaxial layer of the second conductivity type is formed on the second conductivity type pillars 16 and a portion of the first conductivity type pillars 14 between adjacent first mask layers 11 through an epitaxial process to form a body region 17. The upper surface of the body region 17 is higher than the upper surface of the first mask layer 11. The third semiconductor epitaxial layer of the second conductivity type is grown in the area defined by the first mask layer 11 through any suitable epitaxial growth process. The required depth and concentration of the body region 17 can be achieved by controlling the deposition time and deposition concentration.

[0073] In an embodiment of the present invention, a third semiconductor epitaxial layer of the second conductive type is formed on the second conductive type columns 16 between adjacent first mask layers 11 and a portion of the first conductive type columns 14 to form a body region 17, without the need for a body region mask or ion implantation, thereby saving an ion implantation process and a body region mask.

[0074] In step S5, please refer to Figure 7 and Figure 8 As shown, the first mask layer 11 is removed, and a gate trench 18 is formed between adjacent body regions 17 .

[0075] For example, the first mask layer 11 may be removed by a wet etching process. Of course, any other suitable process may also be used to remove the first mask layer 11. After removing the first mask layer 11, the gate trench 18 is formed between the adjacent body regions 17 (where the first mask layer 11 is located). The width of the gate trench 18 is ( Figure 8 The width in the horizontal direction) is equal to the width of the first mask layer 11, so the width of the first mask layer 11 in the horizontal direction can be controlled by controlling the wet etching amount in step S3, thereby controlling the width of the gate trench 18.

[0076] In an embodiment of the present invention, a body region 17 is formed between adjacent first mask layers 11. After removing the first mask layer 11, a gate trench 18 is formed between the body regions 17. When forming the gate trench 18, there is no need to use a gate trench mask, thereby saving a gate trench mask.

[0077] In step S6, please refer to Figure 11 As shown, a trench gate 19 is formed in the gate trench 18 .

[0078] For example, please refer to Figure 9 As shown, a gate oxide layer 191 is formed, and the gate oxide layer 191 covers the sidewalls and the bottom of the gate trench 18 and the upper surface of the body region 17. In one example, the gate oxide layer 191 can be formed by a thermal oxidation process.

[0079] Then please refer to Figure 10 As shown, a gate polysilicon 192 is filled in the gate trench 18 . The gate polysilicon 192 fills the gate trench 18 and covers the gate oxide layer 191 , and then the gate polysilicon 192 is etched back so that the gate polysilicon 192 is only filled in the gate trench 18 .

[0080] Please refer to Figure 11 As shown, the gate oxide layer 191 outside the gate trench 18 is removed. Exemplarily, a wet etching process can be used to remove the gate oxide layer 191 outside the gate trench 18, that is, to remove the gate oxide layer 191 on the upper surface of the body region 17.

[0081] In the method for manufacturing a trench-gate superjunction device provided by the present invention, after a second semiconductor epitaxial layer 15 of a second conductivity type is filled in the deep trench 13 to form a second conductivity type pillar 16, a third semiconductor epitaxial layer of a second conductivity type is epitaxially formed on the second conductivity type pillars 16 and a portion of the first conductivity type pillars 14 between the first mask layer 11 to form a body region 17. The first mask layer 11 is then removed to form a gate trench 18 between adjacent body regions 17. Compared to the prior art, the present invention does not require a body region mask or ion implantation process when forming the body region 17, nor does it require a gate trench mask when forming the gate trench 18. This saves an ion implantation process, a body region mask, and a gate trench mask, effectively reducing costs.

[0082] [Example 2]

[0083] The difference between this embodiment and embodiment one is that, in this embodiment, after the second semiconductor epitaxial layer 15 of the second conductive type is filled in the deep trench 13 to form the second conductive column 16, the epitaxial process is continued to form a body region 17 on the second conductive type column 16 between the adjacent first mask layers 11 and part of the first conductive type column 14.

[0084] Figures 12 to 16 This is a schematic diagram of the steps of the method for manufacturing a trench gate super junction device according to the second embodiment of the present invention. Figure 1 、 Figures 12 to 16 、 Figures 8 to 11 The method for manufacturing the trench gate super junction device provided by the embodiment of the present invention is described in detail.

[0085] In step S1, please refer to Figure 12 As shown, a substrate (not shown) is provided, and a first semiconductor epitaxial layer 10 of a first conductivity type is formed on the substrate.

[0086] In step S2, please refer to Figures 12 to 14 As shown, a first mask layer 11 and a second mask layer 12 are formed on the first semiconductor epitaxial layer 10, and the first semiconductor epitaxial layer 10 is etched using the second mask layer 12 and the first mask layer 11 as masks to form a plurality of deep trenches 13, and the first semiconductor epitaxial layer 10 between the plurality of deep trenches 13 forms a first conductive type column 14.

[0087] In one embodiment, please refer to Figure 12As shown, first, a first mask layer 11 and a second mask layer 12 are formed on the first semiconductor epitaxial layer 10, and then a photoresist layer is coated on the second mask layer 12. The photoresist layer is exposed and developed to form a patterned photoresist layer, defining the formation area of ​​each deep trench 13. Then, the patterned photoresist layer is used as a mask to etch the second mask layer 12 and the first mask layer 11. The etching stops on the surface of the first semiconductor epitaxial layer 10 to form a plurality of openings in the second mask layer 12 and the first mask layer 11. The openings define the formation area of ​​the deep trench 13. Then, the patterned photoresist layer is removed to form the following. Figure 13 Then, using the etched second mask layer 12 and the first mask layer 11 as masks, a portion of the thickness of the first semiconductor epitaxial layer 10 is etched to form a plurality of deep trenches 13. The first semiconductor epitaxial layer 10 between adjacent deep trenches 13 forms first conductivity type pillars 14. At this time, the deep trenches 13 and the first conductivity type pillars 14 between the deep trenches 13 form an alternating structure.

[0088] In one embodiment, the first mask layer 11 includes an oxide layer, and the second mask layer 12 includes a nitride layer and an oxide layer sequentially located on the first mask layer 11. For example, the thickness of the first mask layer 11 may be between The thickness of the nitride layer in the second mask layer 12 can be between The thickness of the oxide layer in the second mask layer 12 can be between In this embodiment, the thickness of the first mask layer 11 determines the depth of the body region 17 formed subsequently, and thus the thickness of the first mask layer 11 can be determined according to the required depth of the body region 17 .

[0089] In step S3, please continue to refer to Figure 14 As shown, the second mask layer 12 is removed, and at the same time, a portion of the first mask layer 11 is removed in the horizontal direction.

[0090] In this embodiment, a wet etching process is used to remove the second mask layer 12. When the second mask layer 12 is removed, the first mask layer 11 is formed in the horizontal direction ( Figure 14 The horizontal direction (as shown) will also be partially etched to narrow its width. The width of the first mask layer 11 in the horizontal direction can be controlled by controlling the wet etching amount, thereby controlling the width of the gate trench 18 formed subsequently.

[0091] In step S4, please refer to Figure 16As shown, a second semiconductor epitaxial layer of a second conductive type is filled in the deep trench 13 to form a second conductive type column 16, and a third semiconductor epitaxial layer of a second conductive type is formed between the second conductive type column 16 and part of the first conductive type column 14 between the first mask layer 11 to form a body region 17, and the second conductive type is opposite to the first conductive type.

[0092] In this embodiment, please first refer to Figure 15 As shown, a second semiconductor epitaxial layer of the second conductivity type is epitaxially grown in the deep trenches 13 by any appropriate epitaxial growth process, and the second semiconductor epitaxial layer fills the deep trenches 13 to form second conductivity type pillars 16. At this time, the second conductivity type pillars 16 (i.e., the second semiconductor epitaxial layer filled in the deep trenches 13) and the first conductivity type pillars 14 (i.e., the first semiconductor epitaxial layer between the deep trenches 13) are arranged alternately.

[0093] Then please continue to refer to Figure 15 As shown, the epitaxial process is continued to form a second conductive type third semiconductor epitaxial layer 20 on the second conductive type columns 16 between adjacent first conductive type columns 11 and part of the first conductive type columns 14 , and the upper surface of the third semiconductor epitaxial layer 20 is higher than the upper surface of the first mask layer 11 .

[0094] Please refer to Figure 15 and Figure 16 As shown, the third semiconductor epitaxial layer 20 is planarized until the first mask layer 11 is exposed, and a body region 17 is formed between adjacent first mask layers 11. In one embodiment, chemical mechanical polishing is used for planarization, and the first mask layer 11 serves as a polishing stop layer. Of course, in the actual chemical mechanical polishing process, over-polishing may occur so that the upper surface of the body region 17 is slightly lower than the upper surface of the first mask layer 11, that is, the depth of the body region 17 is slightly less than the thickness of the first mask layer 11. In another embodiment, other methods, such as wet etching or dry etching, may also be used for planarization, and the upper surface of the body region 17 may be equal to the upper surface of the first mask layer 11, that is, the depth of the body region 17 is equal to the thickness of the first mask layer 11.

[0095] In an embodiment of the present invention, a third semiconductor epitaxial layer of the second conductive type is formed on the second conductive type columns 16 between adjacent first mask layers 11 and a portion of the first conductive type columns 14 to form a body region 17, without the need for a body region mask or ion implantation, thereby saving an ion implantation process and a body region mask.

[0096] In the first embodiment, the second semiconductor epitaxial layer 15 of the second conductivity type is first formed by epitaxial growth, then planarized to form the second conductivity type pillars 16, and then epitaxially grown to form the body region 17. In this embodiment, the second conductivity type pillars 16 are first formed by epitaxial growth, followed by the formation of the third semiconductor epitaxial layer 20 of the second conductivity type, and then planarized to form the body region 17. Compared to the epitaxial growth followed by planarization in the first embodiment, the planarization followed by epitaxial growth in this embodiment saves fabrication time.

[0097] In step S5, please refer to Figure 16 and Figure 8 As shown, the first mask layer 11 is removed, and a gate trench 18 is formed between adjacent body regions 17 .

[0098] In an embodiment of the present invention, a body region 17 is formed between adjacent first mask layers 11. After removing the first mask layer 11, a gate trench 18 is formed between the body regions 17. When forming the gate trench 18, there is no need to use a gate trench mask, thereby saving a gate trench mask.

[0099] In step S6, please refer to Figure 11 As shown, a trench gate 19 is formed in the gate trench 18 .

[0100] In the method for manufacturing a trench-gate superjunction device provided by the present invention, after a second semiconductor epitaxial layer 15 of a second conductivity type is filled in the deep trench 13 to form a second conductivity type pillar 16, a third semiconductor epitaxial layer of a second conductivity type is epitaxially formed on the second conductivity type pillars 16 and a portion of the first conductivity type pillars 14 between the first mask layer 11 to form a body region 17. The first mask layer 11 is then removed to form a gate trench 18 between adjacent body regions 17. Compared to the prior art, the present invention does not require a body region mask or ion implantation process when forming the body region 17, nor does it require a gate trench mask when forming the gate trench 18. This saves an ion implantation process, a body region mask, and a gate trench mask, effectively reducing costs.

[0101] Correspondingly, the present invention also provides a trench gate super junction device, which is manufactured using the above-mentioned method for manufacturing a trench gate super junction device.

[0102] Please refer to Figure 11 As shown, the trench gate super junction device includes:

[0103] a substrate (not shown);

[0104] A first semiconductor epitaxial layer 10 of a first conductivity type is located on the substrate and has a plurality of deep trenches 13 , wherein the first semiconductor epitaxial layer 10 between the deep trenches 13 forms first conductivity type pillars 14 ;

[0105] A second semiconductor epitaxial layer of a second conductivity type is filled in each of the deep trenches 13 to form a second conductivity type pillar 16 ; the second conductivity type is opposite to the first conductivity type;

[0106] A third semiconductor epitaxial layer of the second conductivity type is located on the second conductivity type pillars 16 and a portion of the first conductivity type pillars 14 to form body regions 17 ; gate trenches 18 are formed between adjacent body regions 17 ; and

[0107] The trench gate 19 is located in the gate trench 18 .

[0108] In one embodiment of the present invention, the first conductivity type is N-type, and the second conductivity type is P-type, that is, the first conductivity type column 14 is an N-type column, the second conductivity type column 16 is a P-type column, and the body region 17 is a P-type body region.

[0109] In summary, in the trench gate superjunction device and its manufacturing method provided by the present invention, after filling the deep trench with a second semiconductor epitaxial layer of the second conductivity type to form a second conductivity type column, a third semiconductor epitaxial layer of the second conductivity type is epitaxially formed on the second conductivity type column and a portion of the first conductivity type column between the first mask layer to form a body region, and then the first mask layer is removed to form a gate trench between adjacent body regions. Compared with the prior art, the present invention does not require a body region mask and ion implantation process when forming the body region, nor does it require a gate trench mask when forming the gate trench, thereby saving an ion implantation process, a body region mask, and a gate trench mask, effectively reducing costs.

[0110] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A method for manufacturing a trench gate super junction device, characterized in that: The following steps are involved: providing a substrate, and forming a first semiconductor epitaxial layer of a first conductivity type on the substrate; forming a first mask layer and a second mask layer on the first semiconductor epitaxial layer, and etching the first semiconductor epitaxial layer using the second mask layer and the first mask layer as masks to form a plurality of deep trenches, wherein the first semiconductor epitaxial layer between the plurality of deep trenches forms a first conductivity type pillar; removing the second mask layer and simultaneously removing a portion of the first mask layer in a horizontal direction; Filling the deep trench with a second semiconductor epitaxial layer of a second conductivity type to form a second conductivity type pillar, and forming a third semiconductor epitaxial layer of a second conductivity type on the second conductivity type pillar and a portion of the first conductivity type pillar between the first mask layer to form a body region, wherein the second conductivity type is opposite to the first conductivity type; removing the first mask layer to form a gate trench between adjacent body regions; as well as A trench gate is formed in the gate trench.

2. The method for manufacturing a trench gate super junction device according to claim 1, wherein: The method of forming the second conductive type column and the body region includes: filling a second semiconductor epitaxial layer of the second conductivity type in the deep trench by an epitaxial process, wherein the second semiconductor epitaxial layer fills the deep trench and an upper surface of the second semiconductor epitaxial layer is higher than an upper surface of the first mask layer; planarizing the second semiconductor epitaxial layer until the first mask layer is exposed, and forming a second conductivity type pillar in the deep trench; and A third semiconductor epitaxial layer of the second conductivity type is formed on the second conductivity type pillars and a portion of the first conductivity type pillars between adjacent first mask layers through an epitaxial process to form a body region.

3. The method for manufacturing a trench gate super junction device according to claim 1, wherein: The method of forming the second conductive type column and the body region includes: Filling the deep trench with a second semiconductor epitaxial layer of the second conductivity type through an epitaxial process, wherein the second semiconductor epitaxial layer fills the deep trench to form a second conductivity type pillar; Continuing the epitaxial process to form a third semiconductor epitaxial layer of the second conductivity type on the second conductivity type pillars between adjacent first mask layers and a portion of the first conductivity type pillars, wherein the upper surface of the third semiconductor epitaxial layer is higher than the upper surface of the first mask layer; and The third semiconductor epitaxial layer is planarized until the first mask layer is exposed, and a body region is formed between adjacent first mask layers.

4. The method for manufacturing a trench gate super junction device according to claim 1, wherein: The second mask layer is removed by a wet etching process, and the width of the first mask layer in the horizontal direction is controlled by controlling the wet etching amount, thereby controlling the width of the gate trench.

5. The method for manufacturing a trench gate super junction device according to claim 1, wherein: The first mask layer includes an oxide layer, and the second mask layer includes a nitride layer and an oxide layer sequentially located on the first mask layer.

6. The method for manufacturing a trench gate super junction device according to claim 1, wherein: The method of forming a trench gate in the gate trench includes: forming a gate oxide layer, wherein the gate oxide layer covers the sidewalls and the bottom of the gate trench and the upper surface of the body region; filling gate polysilicon in the gate trench; and The gate oxide layer outside the gate trench is removed.

7. The method for manufacturing a trench gate super junction device according to claim 6, wherein: The gate oxide layer is formed by a thermal oxidation process.

8. The method for manufacturing a trench gate super junction device according to claim 1, wherein: The first conductivity type is N type, and the second conductivity type is P type; or, the first conductivity type is P type, and the second conductivity type is N type.

9. A trench gate super junction device, characterized in that: The trench gate super junction device is manufactured using the manufacturing method of any one of claims 1 to 8, wherein the trench gate super junction device comprises: substrate; A first semiconductor epitaxial layer of a first conductivity type is located on the substrate and has a plurality of deep trenches, wherein the first semiconductor epitaxial layer between the deep trenches forms a first conductivity type pillar; A second semiconductor epitaxial layer of a second conductivity type is filled in each of the deep trenches to form a second conductivity type pillar; the second conductivity type is opposite to the first conductivity type; A third semiconductor epitaxial layer of the second conductivity type is located on the second conductivity type pillar and a portion of the first conductivity type pillar to form a body region; a gate trench is formed between adjacent body regions; and A trench gate is located in the gate trench.

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