Gallium oxide silicon-based integrated solar-blind ultraviolet image sensor and preparation method thereof

Abstract

The present invention relates to the field of photoelectric detector technology, and discloses a gallium oxide silicon-based integrated solar-blind ultraviolet image sensor and a method for preparing the same. The method comprises the following steps: S100, preparing a silicon base electrode; S200, magnetron sputtering a gallium oxide thin film onto an electrode in a pixel region of the silicon base electrode to achieve low-temperature, substrate-free, selective growth of the gallium oxide thin film, thereby obtaining a device; S300, vacuum annealing the device to improve its photoelectric detection performance; S400, electron beam evaporation coating a thin layer of electrode on the device; S500, spin-coating ultraviolet photoresist on the device, and using maskless photolithography and electron beam evaporation coating technology to prepare conductive grid lines aligned across pixels; S600, stripping excess metal portions using a degumming solution to expose a transparent top electrode, thereby obtaining the gallium oxide silicon-based integrated solar-blind ultraviolet image sensor.

Description

Technical Field

[0001] The present invention relates to the field of photoelectric detector technology, and in particular, to a method for preparing a gallium oxide silicon-based integrated solar-blind ultraviolet image sensor. Furthermore, the present invention also relates to a gallium oxide silicon-based integrated solar-blind ultraviolet image sensor produced using the aforementioned method for preparing a gallium oxide silicon-based integrated solar-blind ultraviolet image sensor. Background Art

[0002] Photodetectors are light-sensitive elements that convert incident light signals into electrical signals using the photovoltaic or photoconductive effects of materials. By integrating an array of photodetectors with a readout system, image sensors capable of imaging luminous or reflective objects can be fabricated. Key performance parameters for image sensors include array size, pixel size, and refresh rate: larger arrays and smaller pixel sizes yield higher imaging accuracy, and higher refresh rates facilitate the capture of dynamic targets.

[0003] In existing technologies, silicon-based field-effect transistors (TFTs) and charge-coupled devices (CCDs) are commonly used readout circuit components, offering advantages such as adjustable array scale, controllable pixel size, and high refresh rate. Chip-level integration of photodetectors with silicon-based readout circuits is a key technological approach for achieving high-speed dynamic target imaging.

[0004] In specific applications, such as rocket engine tail plume detection, solar-blind ultraviolet radiation in the 200nm-300nm range exists. Because background radiation in this wavelength band is extremely low in the atmosphere, this characteristic can be exploited to achieve highly sensitive target detection. Currently, systems utilize this wavelength band for target tracking and photoelectric countermeasures. To achieve effective solar-blind ultraviolet imaging, the photosensitive surface must be fabricated using ultra-wide bandgap semiconductor materials (such as gallium oxide) with a bandgap greater than 4.1eV to avoid interference from visible light and infrared background light. However, existing technologies present the following technical challenges:

[0005] 1. Epitaxial growth of gallium oxide materials usually requires a low-mismatch, high-flatness substrate, and the growth, doping, and etching processes all require high temperature conditions;

[0006] 2. Gallium oxide has a significant lattice mismatch with the silicon substrate, making it difficult to directly grow epitaxially on the silicon readout circuit;

[0007] 3. The high temperature process (over 500°C) during the processing of gallium oxide arrays can cause failure in the junction area of ​​silicon-based devices;

[0008] 4. Existing technologies mostly use bonding interconnection to connect detectors and readout circuits, rather than true chip-level integration, which limits the improvement of imaging accuracy and refresh rate.

[0009] Based on the above technical difficulties, the solutions in the existing technology have obvious shortcomings:

[0010] 1. Wire bonding is used to achieve current collection, which is only suitable for small-scale arrays;

[0011] 2. An additional switch array is required to implement pixel gating, which increases system complexity;

[0012] 3. The routing design on the photosensitive surface reduces the duty cycle of the device;

[0013] 4. It is difficult to achieve dynamic imaging of large-scale arrays such as 256×256.

[0014] Therefore, the development of chip-level integration technology of ultra-wide bandgap semiconductor array detectors and silicon-based readout circuits is of great significance for achieving high-precision and high-speed solar-blind ultraviolet imaging. Summary of the Invention

[0015] The present invention provides a gallium oxide silicon-based integrated solar-blind ultraviolet image sensor and a preparation method thereof, realizing low-temperature, high-precision chip-level integration of a gallium oxide solar-blind ultraviolet detector array and a silicon-based readout circuit, thereby overcoming the technical problems in the prior art of difficulty in epitaxial growth of gallium oxide materials, incompatibility with high-temperature processes, and limitations on imaging accuracy and refresh rate caused by bonding interconnections.

[0016] According to one aspect of the present invention, a method for preparing a gallium oxide silicon-based integrated solar-blind ultraviolet image sensor is provided, comprising the following steps: S100, preparing a silicon base electrode; S200, magnetron sputtering depositing a gallium oxide thin film on an electrode in a pixel area of ​​the silicon base electrode to achieve low-temperature, substrate-free selective growth of the gallium oxide thin film to obtain a device; S300, vacuum annealing the device to improve the photoelectric detection performance of the device; S400, electron beam evaporation coating a thin layer of electrode on the device; S500, spin-coating ultraviolet photoresist on the device, and using maskless lithography and electron beam evaporation coating technology to prepare conductive gate lines aligned across pixels; S600, using a degumming solution to strip off excess metal parts to expose a transparent top electrode to obtain a gallium oxide silicon-based integrated solar-blind ultraviolet image sensor.

[0017] Furthermore, step S100 prepares a silicon base electrode, specifically including: S101, ultrasonically cleaning and drying the TFT current collection chip; S102, spin-coating ultraviolet photoresist on the TFT current collection chip, and preparing a pixel-level aligned Au bottom electrode through maskless ultraviolet photolithography technology and electron beam evaporation coating technology; S103, using a degumming solution to strip off excess metal parts to achieve physical isolation of the bottom electrode.

[0018] Furthermore, the TFT current acquisition chip includes a current acquisition area and a pixel area. The current acquisition area is composed of a polycrystalline Si homogeneous structure with a source, drain and gate three-terminal structure. The gate between the source and drain is controlled by the gate voltage. The pixel area is an exposed ITO electrode, and array imaging is achieved by row scanning and column reading of the common electrode.

[0019] Furthermore, step S200 is specifically: magnetron sputtering is used to deposit a gallium oxide film on the Au bottom electrode of the pixel area of ​​the TFT current acquisition chip on which the electrode preparation is completed; step S300 is specifically: high vacuum annealing treatment is performed on the TFT prepared by the electrode to improve the photoelectric detection performance of the device.

[0020] Furthermore, the TFT chip is placed in a magnetron sputtering coating machine, and a 300nm-600nm thick gallium oxide film is deposited in the pixel area under low vacuum with 60sccm argon supplemented with 2sccm oxygen to achieve effective ultraviolet absorption and extraction and separation of photogenerated carriers. The gallium oxide film deposited in the pixel area should not be too thin, as this will affect gallium oxide's absorption of ultraviolet light, nor too thick, as this will increase the carrier transmission distance and affect performance. The device is placed in a high vacuum annealing furnace, heated to 200℃-300℃ at a rate of 4℃ / min, annealed for 3h, and naturally cooled to room temperature. When the annealing temperature is below 200℃, effective contact optimization and built-in electric field enhancement cannot be achieved, but when the temperature is above 300℃, its performance will be lost due to annealing.

[0021] Furthermore, step S400 involves electron beam evaporation of a thin electrode layer on the device. Specifically, the TFT current collection chip, on which the gallium oxide film has been deposited, is placed in an electron beam evaporation coating machine. A 10nm-15nm semi-transparent Au top electrode is deposited on top of the Ga2O3 film at a rate of 0.2Å / s-0.5Å / s under high vacuum to ensure the continuity of the film and effective UV transmittance. After cooling, a double layer of photoresist is spin-coated according to step S102, and a conductive gate line is drawn and exposed in a maskless UV lithography machine. After development, Au is plated to a thickness of at least 50nm and excess metal is stripped off to ensure sufficient conductivity. Cross-pixel alignment of the gate line and the bottom electrode is achieved to improve the device's conductivity.

[0022] Furthermore, step S102 is to spin-coat ultraviolet photoresist on the TFT current collection chip, specifically: spin-coating at a low speed of 500rpm-1000rpm for 5s-10s (to achieve pre-spin coating of photoresist and avoid the unevenness caused by direct high speed) and then spin-coating at a high speed of 3000rpm-4000rpm for 50s-60s to evenly coat LOR 3A on the chip surface (thinning the photoresist to about 1μm to facilitate the subsequent stripping process); heating at 150℃-160℃ on a heating table for 5min to cure LOR 3A; cooling to room temperature, spin-coating at a low speed of 500rpm-1000rpm for 5s-10s and then spin-coating at a high speed of 3000rpm-4000rpm for 50s-60s to evenly coat photoresist S1805 on LOR 3A. Finally, heat on a heating table at 90℃-120℃ for 1min-2min to cure the photoresist S1805.

[0023] Furthermore, the spin-coated chip is placed in a maskless UV photolithography machine, the bottom electrode pattern is drawn and overlay alignment and cutting are performed, the patterned photoresist is exposed to UV light intensity of 0.2 for 220ms, and finally the exposed photoresist is developed in solution ZX-3038 to expose the TFT current collection chip; the chip is placed in an electron beam evaporation coating machine to prepare an Au electrode of at least 50nm.

[0024] Furthermore, step S103 specifically includes: placing the substrate in a degumming solution N-methylpyrrolidone to remove excess metal parts, thereby achieving pixel-level alignment between the bottom electrode and the TFT current collection terminal.

[0025] According to another aspect of the present invention, a gallium oxide silicon-based integrated solar-blind ultraviolet image sensor is provided, which is manufactured using the above-mentioned method for preparing the gallium oxide silicon-based integrated solar-blind ultraviolet image sensor.

[0026] The present invention has the following beneficial effects:

[0027] 1. Low-temperature compatibility integration: Magnetron sputtering deposition technology is used to achieve low-temperature growth of gallium oxide films, breaking through the limitations of traditional epitaxial processes on high-temperature conditions and substrate matching. This makes it possible to directly integrate gallium oxide detectors with silicon-based readout circuits, avoiding damage to silicon-based devices caused by high-temperature processes.

[0028] 2. Heterogeneous integration: Substrate-free selective growth technology overcomes the interface defect problem caused by lattice mismatch, realizes chip-level integration of gallium oxide detection units and silicon-based readout circuits, and eliminates the parasitic parameter effects brought by traditional bonding interconnections.

[0029] 3. Optimization of photoelectric performance: Vacuum annealing effectively improves the crystallization quality and photoelectric properties of the gallium oxide film, enhancing the detector's responsiveness and signal-to-noise ratio, laying the foundation for high-sensitivity day-blind ultraviolet detection. The transparent electrode structure design improves the device's photoelectric conversion efficiency. The vertical structure design significantly increases the device's effective duty cycle.

[0030] 4. Precision electrode preparation: Thin-layer electrodes are prepared using electron beam evaporation technology, combined with maskless photolithography, to achieve precise control and high-resolution patterning of the electrode structure, ensuring accurate alignment of conductive gate lines across pixels and improving device consistency and reliability.

[0031] 5. Structural integrity assurance: Through spin coating of UV photoresist and selective removal by the stripping process, the transparent top electrode is precisely exposed while ensuring the electrode's conductive performance, optimizing the device's duty cycle and optical transmittance; the stripping process ensures the precise formation of the electrode structure.

[0032] 6. Improved process compatibility: The entire process flow is completed under low-temperature conditions and is compatible with standard silicon-based processes, facilitating the mass production of large-scale arrays and providing a feasible solution for the manufacture of highly integrated image sensors. The entire process has good repeatability and scalability. Process compatibility lays the foundation for large-scale array integration.

[0033] 7. Comprehensive performance improvement: Through chip-level integration, the parasitic parameters and signal delays brought by traditional bonding interconnection are effectively reduced, the signal transmission efficiency and system response speed are improved, and at the same time, the occupation of the effective photosensitive area by the photosensitive surface wiring is avoided, achieving high-resolution and high refresh rate imaging performance.

[0034] In addition to the above-described objects, features and advantages, the present invention has other objects, features and advantages. The present invention will be further described in detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The accompanying drawings, which constitute part of the present invention, are provided to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are provided to explain the present invention and do not constitute an undue limitation of the present invention. In the accompanying drawings:

[0036] Figure 1 This is a flow chart of a method for preparing a gallium oxide silicon-based integrated solar-blind ultraviolet image sensor according to a preferred embodiment of the present invention;

[0037] Figure 2 1 are comparative microscopic images of microelectronic structures, wherein (A) is a schematic diagram of the pixel-level aligned bottom electrode prepared in Example 1; (B) is a schematic diagram of the cross-pixel aligned conductive grid prepared in Example 1;

[0038] Figure 3 256×256 is a schematic diagram of the device structure of the gallium oxide array according to the preferred embodiment 1 of the present invention;

[0039] Figure 4 The performance comparison diagram of the array device before and after annealing of the preferred embodiment of the present invention is shown in Figure (A). Figure (B) to Figure (E) are the dark current, photocurrent, responsivity and specific detectivity of the device before and after annealing (@8 W / m 2 254nm); Figure (F) is a graph showing the response speed of the device after annealing;

[0040] Figure 5 The perovskite FA of the preferred embodiment of the present invention 0.95 Cs 0.05 The imaging effects of the PbI3 array device under sunlight are shown in Figure (A) 254nm, Figure (B) 365nm, and Figure (C); the imaging effects of the gallium oxide array device under sunlight are shown in Figure (D) 254nm, Figure (E) 365nm, and Figure (F);

[0041] Figure 6 The figure (A) is a graph comparing the UV transmittance of the thin Au in Example 1 and the commercially available ITO in Example 4. The figure (B) is a graph comparing the unit device performance R (responsivity) and (Specific Detection Rate) characterization diagram;

[0042] Figure 7 This is a comparison chart of the imaging effects of gallium oxide arrays, where Figure 7 (A) is the imaging effect diagram of 64×64 gallium oxide array. Figure 7 (B) is the imaging effect of a 256×256 gallium oxide array. DETAILED DESCRIPTION

[0043] The following embodiments of the present invention are described in detail with reference to the accompanying drawings, but the present invention can be implemented in a variety of different ways as defined and covered below. Unless otherwise specified, the raw materials and reagents used in the following examples are commercially available or can be prepared by known methods.

[0044] Figure 1 This is a flow chart of a method for preparing a gallium oxide silicon-based integrated solar-blind ultraviolet image sensor according to a preferred embodiment of the present invention; Figure 2 are comparative microscopic images of microelectronic structures, wherein Figure (A) is a schematic diagram of the pixel-level aligned bottom electrode prepared in Example 1; Figure (B) is a schematic diagram of the cross-pixel aligned conductive grid prepared in Example 1; Figure 3 Schematic diagram of the device structure of a 256×256 gallium oxide array according to a preferred embodiment 1 of the present invention; Figure 4The performance comparison diagram of the array device before and after annealing of the preferred embodiment of the present invention is shown in Figure (A). Figure (B) to Figure (E) are the dark current, photocurrent, responsivity and specific detectivity of the device before and after annealing (@8 W / m 2 254nm); Figure (F) is a graph showing the response speed of the device after annealing; Figure 5 The perovskite FA of the preferred embodiment of the present invention 0.95 Cs 0.05 Imaging effects of the PbI3 array device at (A) 254nm, (B) 365nm, and (C) sunlight; imaging effects of the gallium oxide array device at (D) 254nm, (E) 365nm, and (F) sunlight; Figure 6 The graph is a correlation analysis of optoelectronic materials and device performance, wherein FIG (A) compares the ultraviolet transmittance of thin Au in Example 1 and commercially available ITO in Example 4, and FIG (B) is a graph showing the unit device performance R (responsivity) and (Specific Detection Rate) characterization diagram; Figure 7 This is a comparison chart of the imaging effects of gallium oxide arrays, where Figure 7 (A) is a 64×64 gallium oxide array imaging image, Figure 7 (B) is a comparison chart of the imaging effects of a 256×256 gallium oxide array.

[0045] The preparation method of the gallium oxide silicon-based integrated solar-blind ultraviolet image sensor of this embodiment includes the following steps: S100, preparing a silicon base electrode; S200, magnetron sputtering depositing a gallium oxide thin film on the electrode in the pixel area of ​​the silicon base electrode to achieve low-temperature, substrate-free selective growth of the gallium oxide thin film to obtain a device; S300, vacuum annealing the device to improve the photoelectric detection performance of the device; S400, electron beam evaporation coating a thin layer of electrode on the device; S500, spin-coating ultraviolet photoresist on the device, and using maskless lithography and electron beam evaporation coating technology to prepare conductive gate lines aligned across pixels; S600, using a degumming solution to strip off excess metal parts to expose the transparent top electrode, thereby preparing a gallium oxide silicon-based integrated solar-blind ultraviolet image sensor. The preparation method of the gallium oxide silicon-based integrated day-blind ultraviolet image sensor of the present invention adopts magnetron sputtering deposition technology to realize low-temperature growth of gallium oxide film, breaking through the limitations of traditional epitaxial process on high temperature conditions and substrate matching, making direct integration of gallium oxide detectors and silicon-based readout circuits possible, and avoiding damage to silicon-based devices caused by high-temperature processes; substrate-free selective growth technology overcomes the interface defect problem caused by lattice mismatch, realizes chip-level integration of gallium oxide detection units and silicon-based readout circuits, and eliminates the parasitic parameter influence caused by traditional bonding interconnection; vacuum annealing treatment effectively improves the crystallization quality and photoelectric properties of gallium oxide film, improves the responsiveness and signal-to-noise ratio of the detector, and lays the foundation for high-sensitivity day-blind ultraviolet detection; transparent electrode structure design improves the photoelectric conversion efficiency of the device; vertical structure design significantly improves the effective duty cycle of the device; electron beam evaporation coating technology is used to prepare thin-layer electrodes, combined with maskless photolithography process, to realize electrode Precise structural control and high-resolution patterning ensure accurate cross-pixel conductive gate line alignment, improving device consistency and reliability. Spin-coating UV photoresist and selective removal via a lift-off process allow precise exposure of the transparent top electrode while maintaining electrode conductivity, optimizing the device's duty cycle and optical transmittance. The lift-off process ensures precise electrode structure formation. The entire process is completed at low temperatures and is compatible with standard silicon-based processes, facilitating the mass production of large-scale arrays and providing a viable solution for the manufacture of highly integrated image sensors. The entire process exhibits excellent repeatability and scalability, laying the foundation for large-scale array integration. Chip-level integration effectively reduces parasitic parameters and signal delays associated with traditional bonding interconnects, improving signal transmission efficiency and system response speed. It also avoids the occupation of the effective photosensitive area by photosensitive surface routing, achieving high-resolution, high-refresh-rate imaging performance. Through the synergistic effect of the overall process, this approach effectively addresses key challenges in existing technologies, such as the difficulty of integrating gallium oxide with silicon-based circuits, high-temperature process incompatibility, and performance limitations caused by bonding interconnects. This provides a reliable technical solution for high-performance imaging applications in the solar-blind ultraviolet band.

[0046] In this embodiment, step S100, which prepares a silicon substrate electrode, specifically includes: S101, ultrasonically cleaning and drying the TFT current acquisition chip; S102, spin-coating UV photoresist on the TFT current acquisition chip, and fabricating a pixel-level aligned Au bottom electrode using maskless UV lithography and electron beam evaporation; S103, using a degumming solution to remove excess metal, achieving physical isolation of the bottom electrode. Ultrasonic cleaning and drying of the TFT current acquisition chip effectively removes organic contaminants, particulate impurities, and oxide layers from the chip surface, providing a clean and stable interface environment for subsequent electrode fabrication. This significantly reduces the contact resistance between the electrode and the chip, decreases the interface defect density, and avoids the impact of contaminants on the photolithography process, laying the foundation for high-precision electrode fabrication. The process combination of spin-coating UV photoresist and maskless UV lithography achieves high-resolution pattern transfer and precise pixel-level alignment. Maskless photolithography avoids the alignment errors associated with traditional masking, making it particularly suitable for fabricating large-scale arrays. Combined with electron beam evaporation, Au electrodes are deposited under a precisely controlled vacuum environment, ensuring not only high purity and density of the electrode film but also excellent thickness uniformity and edge sharpness. This combination of processes allows precise control of electrode size and morphology, providing a precise positional reference and a good ohmic contact interface for subsequent low-temperature integration of gallium oxide thin films. A selective stripping process using a debonding solution removes excess metal, achieving physical isolation and patterning of the bottom electrode. A wet stripping process removes unwanted metal areas by dissolving the photoresist layer, avoiding electrode damage and interface contamination associated with dry etching. The selective control of the stripping process ensures complete isolation between pixel electrodes, effectively preventing inter-pixel shorts and signal crosstalk, while maintaining electrode structural integrity and surface flatness. This physical isolation provides the necessary conditions for constructing independently addressable pixel cell arrays and facilitates thin film deposition and device integration in subsequent process steps.

[0047] In this embodiment, the TFT current acquisition chip includes a current acquisition region and a pixel region. The current acquisition region is composed of a polycrystalline Si homostructure with a source, drain, and gate three-terminal structure. The gate voltage controls the gating between the source and drain. The pixel region is a bare ITO electrode, and array imaging is achieved through row scanning and column reading of the common electrode. The TFT current acquisition chip uses a partitioned design to functionally separate the current acquisition region from the pixel region. The source, drain, and gate three-terminal structure constructed with the polycrystalline Si homostructure forms a precisely controllable gating switch in the current acquisition region. The gate voltage regulation mechanism achieves precise control of the conduction state between the source and drain, ensuring both reliable signal acquisition and independent addressing of the pixel units through gate control. The choice of polycrystalline silicon material provides excellent carrier mobility and stable electrical properties, enabling fast response and low power consumption for the switching device. The pixel region utilizes a bare ITO electrode design. The high light transmittance of the ITO material ensures effective entry of day-blind ultraviolet light, and its excellent conductivity provides an efficient collection path for photogenerated carriers. The row-scanning and column-reading architecture of the common electrode realizes matrix addressing of array imaging, significantly reduces the number of peripheral leads, and improves the integration. The ITO electrode and the subsequently deposited gallium oxide film can form a good ohmic contact, optimizing the injection and collection efficiency of carriers. The coordinated work of the current collection area and the pixel area realizes the functional integration of signal acquisition and photoelectric conversion. The high switching ratio characteristics of the polysilicon switching device ensure the accuracy of signal reading, while the row and column common electrode design greatly simplifies the wiring complexity of large-scale arrays. This structural design provides an ideal signal acquisition platform for the subsequent integration of gallium oxide detectors, so that the entire image sensor system has the characteristics of high sensitivity and high resolution. Another advantage of the partition design is that it can achieve optimal integration of signal processing circuits and photosensitive units without sacrificing the pixel fill factor.

[0048] In this embodiment, step S200 specifically comprises: depositing a gallium oxide thin film by magnetron sputtering on the Au bottom electrode of the pixel area of ​​the TFT current acquisition chip on which the electrode preparation is completed; and step S300 specifically comprises: performing a high vacuum annealing treatment on the TFT prepared by the electrode to improve the photoelectric detection performance of the device. In step S200, the process design of directly depositing a gallium oxide film on the Au bottom electrode using magnetron sputtering technology has significant advantages; the low-temperature characteristics of magnetron sputtering (usually below 300°C) perfectly match the temperature resistance limit of TFT chips, avoiding damage to silicon-based circuits caused by high-temperature processes; epitaxial growth of gallium oxide on the Au electrode is achieved without the need for a lattice-matched substrate required for traditional epitaxy, breaking through the key bottleneck of material integration; by precisely controlling parameters such as sputtering power, gas atmosphere and substrate temperature, a gallium oxide film with good crystallization quality and accurate stoichiometric ratio can be obtained; the direct deposition method forms an ideal semiconductor-metal interface, reduces interface defects caused by traditional transfer processes, and creates conditions for efficient carrier transport; selective growth of gallium oxide film is achieved, and film is formed only on the Au electrode in the pixel area, avoiding unnecessary material waste and subsequent etching steps, and greatly simplifying the process flow. The high-vacuum annealing treatment in step S300 is a key step in optimizing the performance of gallium oxide films. Annealing in a high-vacuum environment with strictly controlled oxygen partial pressure can effectively eliminate intrinsic defects such as oxygen vacancies in the film, significantly improving the crystallization quality of gallium oxide. It promotes grain growth and grain boundary recombination within the film, enhancing carrier mobility. At the same time, vacuum annealing can also optimize the interface characteristics between gallium oxide and the Au electrode, reduce contact resistance, and improve carrier injection efficiency. Unlike conventional atmospheric annealing that may introduce impurity contamination, the high-vacuum environment ensures the cleanliness of the treatment process and avoids secondary contamination. Without affecting the performance of the prepared TFT circuit, the dark current of the gallium oxide detector is reduced by an order of magnitude, the responsiveness is improved, and the signal-to-noise ratio and detection sensitivity of the device are significantly enhanced. The temperature and time windows of the annealing process have been carefully optimized. While improving the quality of the film, it is still fully compatible with the temperature resistance limitations of silicon-based circuits, reflecting the collaborative design concept of the entire process route. S200 achieves low-temperature heterogeneous integration of gallium oxide, while S300 improves detector performance without damaging silicon-based circuits. This combined process not only maintains the functional integrity of the silicon-based readout circuit, but also fully utilizes the solar-blind ultraviolet detection advantage of gallium oxide, laying a material foundation for subsequent device integration and performance optimization.

[0049] In this embodiment, the TFT chip is placed in a magnetron sputtering coater. Under low vacuum, a 300nm-600nm thick gallium oxide film is deposited on the pixel area using 60sccm of argon supplemented with 2sccm of oxygen to achieve effective UV absorption and extraction and separation of photogenerated carriers. The film should be neither too thin, as this will affect the gallium oxide's UV absorption, nor too thick, as this will increase carrier transport distance and affect performance. The device is then placed in a high-vacuum annealing furnace, heated to 200°C-300°C at a rate of 4°C / min, annealed for 3 hours, and naturally cooled to room temperature. Research has found that annealing temperatures below 200°C prevent effective contact optimization and built-in electric field enhancement, but annealing temperatures above 300°C can compromise performance. The magnetron sputtering deposition process utilizes a precise ratio of argon and oxygen (60 sccm argon + 2 sccm oxygen) to achieve controlled growth of gallium oxide thin films in a low-vacuum environment. Argon, the working gas, maintains a stable plasma discharge, while a carefully controlled small amount of oxygen ensures an ideal stoichiometric ratio in the gallium oxide film, effectively suppressing the formation of oxygen vacancies. The film thickness of 300nm-600nm is optimized to ensure sufficient solar-blind UV absorption efficiency while avoiding carrier recombination losses associated with excessively thick films. The low-temperature deposition process (typically substrate temperatures <300°C) fully complies with the temperature limits of TFT chips, preventing damage to silicon-based circuitry. The selective deposition method forms gallium oxide thin films only on the Au electrodes in the pixel area, eliminating the need for additional patterning and etching steps, simplifying the process. By adjusting parameters such as sputtering power and pressure, gallium oxide films with well-oriented crystals and smooth surfaces are obtained, with a stable bandgap of ~4.9 eV and excellent selectivity in the solar-blind UV band. The high-vacuum annealing process, through precise temperature control (4°C / min ramp rate) and long hold times (200°C-300°C for 3 hours), achieves deep optimization of film properties while avoiding thermal shock. The high vacuum environment (typically <10⁻³Pa) effectively prevents surface oxidation and impurity incorporation at high temperatures. The carefully selected annealing temperature of 200°C promotes atomic rearrangement and defect repair within the film while remaining well below the temperature limit of silicon-based circuits (typically >400°C, where performance degradation occurs). The slow ramp rate prevents thermal stress-induced cracking or delamination, and the 3-hour hold time ensures the complete elimination of bulk defects and interface states. Natural cooling further reduces thermal stress accumulation and maintains the film's structural integrity. The annealing treatment significantly improves the crystalline quality of the gallium oxide film, increasing grain size, reducing grain boundaries, and enhancing carrier mobility. It also optimizes the interface properties of the gallium oxide / Au electrode, reducing contact resistance and improving device response speed.

[0050] In this embodiment, step S400 is to electron beam evaporate a thin layer of electrode on the device. Specifically, the TFT current collection chip on which the gallium oxide thin film is prepared is placed in an electron beam evaporation coating machine, and a 10nm-15nm semi-transparent Au top electrode is prepared on top of the Ga2O3 film at a speed of 0.2Å / s-0.5Å / s under high vacuum to ensure the continuity and effective ultraviolet transmittance of the film; after cooling, a double layer of photoresist is spin-coated according to step S102, and a conductive gate line is drawn and exposed in a maskless ultraviolet lithography machine. After development, Au is plated with a thickness of at least 50nm (with sufficient conductivity) and excess metal is stripped off to achieve cross-pixel alignment of the gate line and the bottom electrode to improve the conductivity of the device. The semi-transparent top electrode is precisely fabricated using high-vacuum electron beam evaporation technology, depositing an ultra-thin Au film of 10nm-15nm at an ultra-slow speed of 0.2Å / s-0.5Å / s. The high vacuum environment (typically <10⁻³Pa) effectively suppresses film oxidation and impurity incorporation, ensuring the high purity of the electrode. The precisely controlled deposition rate achieves an atomically flat, continuous film, ensuring both the conductive continuity of the electrode and sufficient day-blind UV transmittance. The 10nm-15nm thickness design has been rigorously optimized to achieve an optimal balance between conductivity and transmittance, thereby improving the photoelectric conversion efficiency. The semi-transparency allows UV light to penetrate the electrode into the gallium oxide absorption layer, while providing an efficient collection path for photogenerated carriers. The low-temperature characteristics of electron beam evaporation (substrate temperature <80°C) completely avoid damage to the gallium oxide film and silicon-based circuits caused by high-temperature processes. The conductive gate lines are fabricated using a double-layer photoresist structure and maskless lithography, enabling high-precision patterning of Au gate lines at least 50nm thick. The double-layer photoresist design (typically a thick upper layer and a thin lower layer) creates an ideal sidewall tilt angle, improving the success rate of the lift-off process. Maskless direct write exposure technology achieves submicron alignment accuracy, ensuring precise cross-pixel alignment of the gate lines and the bottom electrode. This three-dimensional interconnect structure reduces on-resistance between pixels. The Au thickness of at least 50nm, optimized through electrical simulations, ensures current carrying capacity while keeping the gate line light shielding area below 5%. The selective removal during the lift-off process enables clean and defined electrode patterns, avoiding potential damage to the gallium oxide surface caused by dry etching. The systematic improvement in device performance is achieved through the coordinated design of the top electrode and gate lines, creating an optimized vertical conductive structure. The semi-transparent top electrode enables efficient collection of photogenerated carriers, while the cross-pixel aligned gate line network provides a low-resistance current path, reducing signal transmission delay. The entire process chain maintains low-temperature characteristics (maximum process temperature <300°C), fully compatible with the temperature limits of silicon-based circuits, providing a reliable technical path for the fabrication of large-scale arrays such as 256×256. The resulting device achieves a duty cycle >45% and a refresh rate >2Hz, achieving comprehensive performance that reaches the advanced level of solar-blind UV imaging.

[0051] In this embodiment, step S102 is to spin-coat the ultraviolet photoresist on the TFT current collection chip, specifically: after spinning at a low speed of 500rpm-1000rpm for 5s-10s, pre-spin coating of the photoresist is achieved to avoid the unevenness caused by the direct high speed; then spin-coating at a high speed of 3000rpm-4000rpm for 50s-60s to evenly coat LOR 3A on the chip surface (thinning the photoresist to about 1μm is beneficial to the subsequent stripping process); heating at 150℃-160℃ on a heating table for 5min to cure LOR 3A; cooling to room temperature, spinning at a low speed of 500rpm-1000rpm for 5s-10s, and then spinning at a high speed of 3000rpm-4000rpm for 50s-60s to evenly coat the photoresist S1805 on the LOR 3A. The top layer of photoresist is then cured by heating on a heating platform at 0°C-120°C for 1-2 minutes to cure the S1805 photoresist. A dual-layer photoresist spin-coating process achieves the ideal bondline structure required for high-precision photolithographic pattern transfer. Precision bondline control utilizes a phased, variable-speed spin-coating process (500-1000 rpm for 5-10 seconds, 3000-4000 rpm for 50-60 seconds) to achieve uniform coating of the underlying LOR 3A photoresist. The low-speed phase ensures sufficient spread of the gel on the chip surface, while the high-speed phase precisely controls the gel layer thickness and achieves excellent surface flatness. A moderate-temperature cure at 150-160°C crosslinks the LOR 3A polymer, forming a stable underlying structure. Its unique chemical properties create ideal interfacial conditions for subsequent stripping. This base coater exhibits unique solubility characteristics, resulting in controlled lateral etching during development, enabling the fabrication of steep sidewalls (85°-90°). The dual-layer structure synergistically forms a composite adhesive layer by depositing an upper layer of S1805 photoresist on the cured LOR 3A layer through optimized spin coating parameters (500-1000 rpm / 5s-10s, 3000-4000 rpm / 50s-60s). Low-temperature curing at 100°C prevents secondary flow of the bottom layer, maintaining a clear interface between the two layers. This dual-layer design allows the upper S1805 photoresist to provide high-resolution pattern transfer, while the unique dissolution dynamics of the lower LOR 3A layer create a controlled undercut during development, creating a perfect "cantilever" structure for the subsequent metal lift-off process. The entire coating process is controlled within a low-temperature range, fully compatible with the temperature-resistant characteristics of TFT current acquisition chips. The stepped temperature treatment strategy (150℃-160℃, 90℃-120℃) ensures the independent curing of the two layers of glue without mutual interference; the resulting composite glue layer has excellent resistance to electron beam scattering, achieving sub-micron graphic fidelity in subsequent electron beam exposure.This double-layer structure controls the sidewall angle of the final metal pattern, providing an ideal template for the preparation of high-aspect-ratio electrodes, improving pattern transfer accuracy, and reducing the residual adhesive rate in the stripping process.

[0052] In this example, the spin-coated chip was placed in a maskless UV lithography system to pattern the bottom electrode, perform overlay alignment, and perform cutouts. The photoresist was then patterned using a UV light intensity of 0.2 for 220 ms. Finally, the exposed photoresist was developed in a ZX-3038 solution to expose the TFT current collection chip. The chip was then placed in an electron beam evaporation coating system to deposit an Au electrode at least 50 nm thick. High-precision patterning was achieved using a maskless direct write exposure system (UV light intensity 0.2, exposure time 220 ms), achieving submicron pattern resolution. Dynamically focused laser direct writing technology avoids diffraction errors associated with traditional reticles and, combined with a precision motion platform, enables even higher overlay alignment accuracy. The specific chemical formula of the ZX-3038 developer solution enables anisotropic development, forming an ideal undercut structure in the LOR 3A / S1805 double-layer adhesive, creating a perfect cantilever profile for the subsequent lift-off process. High-quality electrode fabrication involves depositing a minimum of 50nm of Au thin film, achieving excellent electrode performance. The low deposition rate ensures sufficient surface diffusion of Au atoms, forming a dense, continuous film. Precisely controlled thickness ensures the electrode maintains high conductivity while forming ideal interfacial properties with the subsequent gallium oxide film. High-energy electron bombardment via electron beam evaporation removes adsorbed gases from the substrate surface, reducing the contact resistance between the Au electrode and the TFT current collection chip and significantly improving carrier injection efficiency. Maskless exposure avoids mask contamination and overlay accumulation errors associated with traditional photolithography, improving pixel position accuracy in a 256×256 array. A precisely controlled development process creates a gradient dissolution profile within the double-layer resist, increasing the yield of the lift-off process. The low-temperature nature of electron beam evaporation (substrate temperature <80°C) completely avoids thermal damage, maintaining the electrical stability of the TFT device. The resulting Au electrode exhibits an atomically flat surface and exhibits a low interface state density with the subsequent gallium oxide film, providing an ideal charge collection structure for high-performance solar-blind UV detection.

[0053] In this embodiment, step S103 specifically involves placing the substrate in a degumming solution, N-methylpyrrolidone, to remove excess metal, thereby achieving pixel-level alignment between the bottom electrode and the TFT current collector. Selective metal stripping utilizes N-methylpyrrolidone (NMP) as the degumming solution. Leveraging its strong polarity, NMP effectively dissolves the double-layer photoresist (LOR 3A / S1805), rapidly degrading the resist layer through the undercut structure formed by development through penetration. This allows for rapid and complete stripping of excess Au metal covering the photoresist while fully preserving the electrode structure in the patterned area. The unique chemical properties of NMP ensure zero corrosion of the Au electrode, maintaining a surface roughness of <0.5nm. The precision pattern-definition stripping process leverages the interfacial properties of the two layers. The rapid swelling of the upper S1805 photoresist accelerates chemical penetration, while the slow dissolution of the lower LOR 3A layer creates a controlled lateral dissolution front, ultimately producing electrode sidewalls with a steepness of 89±1°. This anisotropic stripping avoids the undercutting issues associated with traditional wet etching. During the interface performance optimization process, NMP does not corrode the ITO electrodes and Si substrate of the TFT current collection chip, fully preserving the original electrical properties. The resulting Au bottom electrode achieves precise pixel-level alignment with the TFT current collection terminal, reducing contact resistance. The exposed electrode surface after stripping exhibits atomically clean surface quality, providing an ideal heterojunction interface for subsequent gallium oxide deposition, thereby reducing interface state density. This low-temperature wet process offers exceptional process compatibility, completely avoiding the potential plasma damage associated with dry etching. The entire process is fully compatible with silicon-based processes, providing a reliable technical path for the mass production of large-scale 256×256 arrays and improving electrode yield. The resulting excellent inter-pixel insulation performance lays a key electrode foundation for high-resolution solar-blind ultraviolet imaging.

[0054] The gallium oxide silicon-based integrated solar-blind ultraviolet image sensor of this embodiment is manufactured using the above-mentioned method for manufacturing the gallium oxide silicon-based integrated solar-blind ultraviolet image sensor.

[0055] During implementation, a method for fabricating a gallium oxide silicon-based integrated solar-blind ultraviolet image sensor was provided. This method utilizes a substrate-independent, low-temperature, and efficient technology. To address the high-temperature and lattice mismatch issues inherent in gallium oxide growth, a magnetron sputtering strategy was employed to selectively grow large-area gallium oxide thin films on silicon-based readout circuits at low temperature and without a substrate. This enabled chip-level integration of gallium oxide array detectors with silicon-based integrated circuits, resulting in a gallium oxide-based solar-blind ultraviolet image sensor with an array size of 256×256, a single pixel as small as 50.8μm, and an image refresh rate of 2Hz. Furthermore, vacuum annealing technology was used to effectively improve the responsivity and specific detectivity of the gallium oxide solar-blind ultraviolet detector. Furthermore, a solar-blind ultraviolet transparent electrode was developed to achieve a vertically structured detector unit, thereby increasing the duty cycle of the gallium oxide-based solar-blind ultraviolet image sensor to 44%.

[0056] The chip-level integration technology of ultra-wide bandgap semiconductor material gallium oxide (Ga2O3) and silicon-based readout circuit has produced a large-array 256×256 solar-blind ultraviolet image sensor, filling the technical gap in high-precision and fast imaging in the solar-blind ultraviolet band.

[0057] The core principle of this invention is to develop a vertical solar-blind UV photodetector by leveraging the highly selective absorption properties of ultra-wide-bandgap semiconductor gallium oxide (GaO) for solar-blind UV radiation and the high solar-blind UV transmittance of thin metal films. Simultaneously, the invention develops low-temperature growth technology for GaO thin films using magnetron sputtering to achieve low-temperature chip-scale integration of GaO array detectors with silicon-based readout circuitry. This invention addresses the integration challenges of ultra-wide-bandgap semiconductor GaO with silicon-based readout circuitry, circumventing the low in-plane transmission efficiency and array fabrication and wiring difficulties of planar detectors, thereby achieving high-precision and rapid solar-blind UV imaging.

[0058] The preparation method of the gallium oxide silicon-based integrated solar-blind ultraviolet image sensor of the present invention is as follows: Figure 1 As shown, the following steps are included:

[0059] S1. Preparation of bottom electrode;

[0060] Preparation of S2 and Ga2O3 thin films;

[0061] S3. Preparation of transparent top electrode and conductive gate line.

[0062] Step S1 includes:

[0063] Ultrasonic cleaning and drying of TFT (array field-effect transistor) current acquisition chips: TFT current acquisition chips are primarily composed of a current acquisition region and a pixel region. The current acquisition region is made of a polycrystalline Si homogeneous structure with a source-drain-gate three-terminal structure. The gate voltage controls the gating between the source and drain. The device pixel region consists of exposed ITO electrodes, and array imaging is achieved through row-scanning and column-reading common electrodes.

[0064] Next, UV photoresist was spin-coated on the TFT current collection chip, and a 50 nm Au bottom electrode with pixel-level alignment was fabricated using maskless UV lithography and electron beam evaporation.

[0065] Finally, the excess metal parts are stripped off using a degumming solution to achieve physical isolation of the bottom electrode.

[0066] Step S2 includes:

[0067] On the TFT current acquisition chip where the bottom electrode has been prepared in step S1, a gallium oxide film is deposited on the Au electrode in the pixel area by magnetron sputtering. The device is then subjected to a high vacuum annealing process to improve the device's photoelectric detection performance.

[0068] Step S3 includes:

[0069] A 10nm thin layer of Au electrode is deposited by electron beam evaporation on the TFT current collection chip, which has already been prepared with the gallium oxide thin film in step S2. UV photoresist is then spin-coated on the chip. Maskless photolithography and electron beam evaporation are then used to form conductive gate lines aligned across the pixels. Finally, a stripping solution is used to remove the excess metal, exposing the transparent top electrode.

[0070] Example 1:

[0071] S1. Preparation of bottom electrode

[0072] Preheat the TFT current collection chip at 150°C for 5 minutes. After cooling, spin-coat a double layer of photoresist as follows:

[0073] (1) Spin coating at a low speed of 1000 rpm for 10 seconds and then at a high speed of 3500 rpm for 50 seconds to evenly coat LOR 3A on the chip surface;

[0074] (2) Heat on a heating table at 160°C for 5 minutes to cure LOR 3A; cool to room temperature, spin-coat at a low speed of 1000 rpm for 10 seconds and then at a high speed of 4000 rpm for 60 seconds to evenly coat the photoresist S1805 on the upper layer of LOR 3A glue;

[0075] (3) Finally, heat on a heating table at 100°C for 1 minute to cure the photoresist S1805. Place the spin-coated chip in a maskless UV lithography machine, draw the bottom electrode pattern and perform overlay alignment and cutting. Expose the patterned photoresist with a UV intensity of 0.2 for 220ms. Finally, develop the exposed photoresist in the solution ZX-3038 to expose the TFT current collection chip. Place the chip in an electron beam evaporation coating machine and prepare a 50nm Au electrode at a speed of 1 Å / s. Then place it in the degumming solution N-methylpyrrolidone (NMP) to remove the excess metal part, so as to achieve pixel-level alignment between the bottom electrode and the TFT current collection end, as shown in Figure 2. Figure 2 shown.

[0076] Figure 2 is a set of contrast microscopic images of microelectronic structures, where Figure 2 (A) shows the pixel-level aligned bottom electrode prepared in Example 1, showing a light green square array, reflecting the electrode alignment structure at the single pixel level; Figure 2 (B) shows a cross-pixel aligned conductive gate fabricated from the same example, shown as an array of golden squares, reflecting the interconnected gate design across pixels. The two structural scales (20μm) indicate the micron-scale nature of these electronic components. This side-by-side comparison visually demonstrates the morphological differences between the two functional structures (electrode / gate) fabricated using the same process, verifying the uniformity of the fabrication process and / or the effectiveness of the functional design.

[0077] Preparation of S2 and Ga2O3 thin films

[0078] The TFT current acquisition chip, with the bottom electrode fabricated in step S1, was placed in a magnetron sputtering coating machine. A 600 nm thick gallium oxide film was deposited on the pixel area using 60 sccm of argon supplemented with 2 sccm of oxygen under low vacuum. The device was then placed in a high vacuum annealing furnace, heated to 200°C at a rate of 4°C / min, annealed for 3 hours, and then naturally cooled to room temperature.

[0079] S3. Preparation of top electrode

[0080] The TFT current collection chip, which had the gallium oxide film deposited in step S2, was placed in an electron beam evaporation coating machine. A 10nm semi-transparent Au top electrode was deposited on top of the Ga2O3 film at a rate of 0.2 Å / s under high vacuum. After cooling, a double-layer photoresist was spin-coated as in step S1. The conductive gate lines were then drawn and exposed using a maskless UV lithography machine. After development, a 50nm thick Au layer was deposited, and the excess metal was stripped off to achieve cross-pixel alignment between the gate lines and the bottom electrode, improving device conductivity.

[0081] The gallium oxide silicon-based integrated solar-blind ultraviolet image sensor prepared in Example 1 is as follows: Figure 3 As shown, the array scale is 256×256, the pixel size is 50.8μm×50.8μm, the duty cycle of the pixel area / substrate is 44%, and the duty cycle of the actual photosensitive area / pixel area is 69%.

[0082] Example 2:

[0083] The difference between Example 2 and Example 1 is that the pixel scale is 64×64, the pixel size is 500×500 μm, and the other steps are the same as Example 1.

[0084] The gallium oxide silicon-based integrated solar-blind ultraviolet image sensor prepared in Example 2 has an array scale of 64×64, a pixel size of 500μm×500μm, a pixel area / substrate duty ratio of 49%, and an actual photosensitive area / pixel area duty ratio of 64%.

[0085] Comparative Example 1:

[0086] The difference between Comparative Example 1 and Example 1 is that the gallium oxide film is not subjected to annealing post-treatment, and the remaining steps are the same as those of Example 1.

[0087] The results show that if the gallium oxide film is not post-annealed, the overall performance of the device will be significantly reduced, that is, post-annealing treatment of the gallium oxide film can significantly improve the overall performance of the device.

[0088] Comparative Example 2:

[0089] The difference between Comparative Example 2 and Example 1 is that commercially available ITO (indium tin oxide) is used instead of thin Au as the top transparent electrode, and the remaining steps are the same as Example 1.

[0090] The results show that the use of commercially available ITO (indium tin oxide) leads to a significant decrease in transmittance in the ultraviolet band, that is, the transmittance of thin Au in the ultraviolet band is much higher than that of ITO, which can achieve more effective ultraviolet imaging.

[0091] Comparative Example 3:

[0092] The difference between Comparative Example 3 and Example 1 is that the perovskite FA is used 0.95 Cs 0.05 PbI3 (band gap approximately 1.5 eV) replaces gallium oxide as the photosensitive layer. The preparation process is as follows: Prepare the bottom electrode according to Example 1. Take 50 μL of perovskite precursor solution (dissolve 1 mol of 95% FAI, 5% CsI, and PbI2 in 1 mL of DMSO and stir for 1 hour. FAI, CsI, and PbI2 were purchased from Yingkou Youxuan Trading Co., Ltd.) and drop it onto the surface of the TFT current collection chip. Spin-coat at 5000 rpm for 35 seconds. At the 10th second before the end, add 100 μL of anisole (99.7%, Sigma-Aldrich) and anneal at 120°C for 15 minutes. Then, prepare the top transparent electrode according to the same steps as Example 1, but do not prepare the conductive gate lines.

[0093] The results show that the detectors made of perovskite have a certain response to the ultraviolet to visible light bands, and the signal-to-noise ratio is relatively low; while the gallium oxide device only responds to solar-blind ultraviolet light, which can effectively avoid the interference of visible and infrared light on target imaging effects under conditions such as missile warning.

[0094] Depend on Figure 4 It can be seen that the performance of the device is significantly improved after annealing, and a responsivity of more than 100 A / W and a sensitivity of 1×10 15 Jones's specific detectivity. Figure 5 It can be seen that gallium oxide as a photosensitive layer can achieve better performance than perovskite FA in the solar-blind ultraviolet band. 0.95 Cs 0.05 The array imaging of PbI3 has a better signal-to-noise ratio and clearer imaging. The device only responds to the solar-blind ultraviolet band and has good spectral selectivity and narrow-band response characteristics. Figure 6 It can be seen that the transparent Au electrode can achieve a transmittance of more than 50% in the range of 200nm-500nm. Its transmittance performance in the day-blind ultraviolet band (200nm-280nm) is far superior to the ITO transparent electrode which is widely used in the visible band.

[0095] The comparison results of the relevant parameters of Examples 1 and 2 with other cutting-edge solar-blind ultraviolet detector arrays are shown in Table 1:

[0096] Table 1: Parameters of Examples 1 and 2 and other cutting-edge solar-blind UV detector arrays

[0097]

[0098] [1]Optics Letters, 2025, Vol. 50(5)

[0099] [2]IEEE Transactions on Electron Devices, 2021, Vol. 68(7)[IEEE Transactions on Electron Devices, 2021, Vol. 68(7)];

[0100] [3] Journal of Semiconductors, 2024, 45(9)

[0101] [4]IEEE ELECTRON DEVICE LETTERS, 2023, Vol. 44 (7)

[0102] [5]2022 IEEE Symposium on VLSI Technology and Circuits;

[0103] As can be seen from Table 1, the 256×256 and 64×64 arrays prepared by the present invention have significant advantages over the existing technology in terms of pixel scale, pixel size and duty cycle, and can achieve better silicon-based integration. Figure 7 It can be seen that the 256×256 array can achieve imaging with higher precision and better signal-to-noise ratio than the 64×64 array.

[0104] The method for preparing the gallium oxide silicon-based integrated solar-blind ultraviolet image sensor of the present invention has the following technical effects:

[0105] 1. This paper develops chip-level integration technology for gallium oxide array detectors and silicon-based readout circuits, and designs and fabricates a solar-blind ultraviolet image sensor with an array size of 256×256, a pixel size as small as 50.8μm, and an image refresh rate of 2 Hz. This is the gallium oxide solar-blind ultraviolet image sensor currently available with the largest pixel size, smallest single pixel, and fastest imaging speed, and it also features a simple process and low cost.

[0106] 2. The present invention has developed a vertically structured solar-blind UV detector using translucent thin Au as the UV-transparent electrode, verifying the potential of thin-layer Au as a transparent electrode in the field of UV photoelectric detection. It can achieve light response and precise imaging in the solar-blind band without the aid of filters or signal amplifiers, reducing the complexity and cost of the imaging system.

[0107] 3. The present invention takes advantage of the solar-blind ultraviolet light response characteristics of the wide-bandgap semiconductor material gallium oxide, avoids the signal interference problem caused by the infrared and visible light response of narrow-bandgap materials, and realizes the characteristic imaging of solar-blind ultraviolet.

[0108] Matters not covered by the present invention are known technologies.

[0109] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0110] The above-described embodiments merely illustrate several implementations of the present invention. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that variations and improvements are possible without departing from the spirit of the present invention, and all such variations and improvements fall within the scope of protection of the present invention.

[0111] The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that the present invention is susceptible to various modifications and variations. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention shall be included within the scope of protection of the present invention.

Claims

1. A method for preparing a gallium oxide silicon-based integrated solar-blind ultraviolet image sensor, characterized in that: The following steps are involved: S100, preparing a silicon substrate electrode; Step S100 is to prepare a silicon base electrode, specifically comprising: S101, ultrasonically cleaning and drying the TFT current collection chip; S102, spin-coating UV photoresist on the TFT current collection chip, and using maskless UV lithography and electron beam evaporation coating technology to achieve precise pixel-level alignment of the Au bottom electrode formed with the TFT current collection terminal, thereby fabricating a pixel-level aligned Au bottom electrode; S103, using a degumming solution to remove excess metal parts to achieve physical isolation of the bottom electrode; the TFT current collection chip includes a current collection area and a pixel area; S200, depositing a gallium oxide film on an electrode in a pixel region of a silicon substrate electrode by magnetron sputtering to achieve low-temperature, substrate-free, selective growth of the gallium oxide film to obtain a device; The low temperature characteristic of magnetron sputtering is below 300°C; S300, the device is subjected to vacuum annealing treatment to improve the photoelectric detection performance of the device; S400, depositing a thin layer of electrode on the device by electron beam evaporation; S500, spin-coating ultraviolet photoresist on the device, and using maskless photolithography and electron beam evaporation coating technology to prepare conductive gate lines aligned across pixels; The conductive gate lines are fabricated using a double-layer photoresist structure and maskless lithography, enabling high-precision patterning of Au gate lines at least 50nm thick. The double-layer photoresist design creates an ideal sidewall tilt angle, improving the success rate of the lift-off process. Maskless direct write exposure technology achieves submicron alignment accuracy, ensuring precise cross-pixel alignment between the gate lines and the bottom electrode. This three-dimensional interconnect structure reduces on-resistance between pixels. S600: Use a degumming solution to peel off excess metal parts to expose the transparent top electrode, thereby producing a gallium oxide silicon-based integrated solar-blind ultraviolet image sensor.

2. The method for preparing the gallium oxide silicon-based integrated solar-blind ultraviolet image sensor according to claim 1, characterized in that: The current collection area is composed of a polycrystalline Si homogeneous structure with a source, drain and gate three-terminal structure. The gate voltage is used to control the selection between the source and drain. The pixel area is an exposed ITO electrode, and array imaging is achieved by row scanning and column reading of the common electrode.

3. The method for preparing the gallium oxide silicon-based integrated solar-blind ultraviolet image sensor according to claim 1, characterized in that: Step S200 is specifically as follows: A gallium oxide film is deposited by magnetron sputtering on the Au bottom electrode of the pixel area of ​​the TFT current collection chip on which the electrode preparation is completed; Step S300 is specifically as follows: The TFT prepared by the electrode is subjected to high vacuum annealing treatment to improve the photoelectric detection performance of the device.

4. The method for preparing the gallium oxide silicon-based integrated solar-blind ultraviolet image sensor according to claim 3, characterized in that: The TFT chip is placed in a magnetron sputtering coater, and a 300nm-600nm thick gallium oxide film is deposited on the pixel area using 60sccm argon supplemented with 2sccm oxygen under low vacuum; The device was placed in a high vacuum annealing furnace, heated to 200°C-300°C at a rate of 4°C / min, annealed for 3 hours, and naturally cooled to room temperature.

5. The method for preparing the gallium oxide silicon-based integrated solar-blind ultraviolet image sensor according to claim 3, characterized in that: Step S400 is to deposit a thin layer of electrode on the device by electron beam evaporation, specifically: The TFT current collection chip with the gallium oxide film prepared was placed in an electron beam evaporation coating machine, and a 10nm-15nm semi-transparent Au top electrode was deposited on the top of the gallium oxide film at a speed of 0.2Å / s-0.5Å / s under high vacuum; After cooling, a double-layer photoresist is spin-coated according to step S102, and the conductive gate lines are drawn and exposed in a maskless UV lithography machine. After development, Au is plated with a thickness of at least 50 nm and excess metal is stripped off to achieve cross-pixel alignment between the gate lines and the bottom electrodes to improve the conductivity of the device.

6. The method for preparing a gallium oxide silicon-based integrated solar-blind ultraviolet image sensor according to any one of claims 1 to 5, characterized in that: Step S102 is to spin-coat ultraviolet photoresist on the TFT current acquisition chip, specifically: Spin coating at a low speed of 500-1000 rpm for 5-10 seconds, then spin coating at a high speed of 3000-4000 rpm for 50-60 seconds to evenly coat LOR 3A on the chip surface; Heat on a heating table at 150-160°C for 5 minutes to cure LOR 3A; cool to room temperature, spin-coat at a low speed of 500-1000 rpm for 5-10 seconds, and then spin-coat at a high speed of 3000-4000 rpm for 50-60 seconds to evenly coat the photoresist S1805 on the upper layer of LOR 3A glue; Finally, heat on a heating table at 90° C.-120° C. for 1 min-2 min to cure the photoresist S1805.

7. The method for preparing the gallium oxide silicon-based integrated solar-blind ultraviolet image sensor according to claim 6, characterized in that: The spin-coated chip was placed in a maskless UV lithography machine to draw the bottom electrode pattern and perform overlay alignment and cutting. The patterned photoresist was exposed to UV light with an intensity of 0.2 for 220ms. Finally, the exposed photoresist was developed in a solution of ZX-3038 to expose the TFT current collection chip. The chip was placed in an electron beam evaporation coating machine to prepare an Au electrode at least 50 nm thick.

8. The method for preparing the gallium oxide silicon-based integrated solar-blind ultraviolet image sensor according to claim 7, characterized in that: Step S103 is specifically as follows: The excess metal part is removed by placing it in the degumming liquid N-methylpyrrolidone to achieve pixel-level alignment between the bottom electrode and the TFT current collection end.

9. A gallium oxide silicon-based integrated solar-blind ultraviolet image sensor, characterized in that: The method for preparing the gallium oxide silicon-based integrated solar-blind ultraviolet image sensor according to any one of claims 1 to 8 is used to prepare the sensor.

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