Inspection system and temperature control method

Abstract

The invention provides an inspection system and a temperature control method for inspecting a substrate while properly performing temperature control. An inspection system for inspecting a substrate while temperature control is performed by a temperature adjustment mechanism, the inspection system comprising: a substrate holding unit for holding the substrate; a detection unit that supplies inspection power to the electrode unit of the substrate; and a control unit, in which the detection unit has a temperature estimation unit that estimates the bonding portion temperature of the bonding portion provided on the substrate, the control unit including: a step of supplying the inspection power to the substrate; a step for acquiring information on the temperature of the bonding portion after the supply of the inspection power is stopped; a step of determining an offset temperature of the substrate holding portion on the basis of information on the temperature of the bonding portion; a step for adjusting the temperature of the substrate holding unit on the basis of the control temperature shifted using the shift temperature; and a step in which the substrate is inspected by supplying the inspection power to the substrate after the temperature of the substrate holding unit has been adjusted.

Description

Technical Field

[0001] The present disclosure relates to an inspection system and a temperature control method. Background Art

[0002] Patent Document 1 discloses a power conversion device capable of detecting the voltage between the source and drain terminals of a power transistor during its on-period and estimating the junction temperature of the power transistor with high accuracy.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2019-122107 Summary of the Invention

[0006] Technical problem to be solved by the invention

[0007] One aspect of the present disclosure provides an inspection system and a temperature control method for inspecting a substrate while appropriately performing temperature control.

[0008] Technical means to solve the problem

[0009] In order to solve the above-mentioned problem, according to one method, an inspection system can be provided, which inspects a substrate while controlling the temperature through a temperature adjustment mechanism, including: a substrate holding portion that holds the substrate; a detection portion that supplies inspection power to the electrode portion of the substrate; and a control portion, wherein the detection portion has a temperature estimating portion that estimates the joint temperature of the joint provided at the substrate, and the control portion includes: a process of supplying the inspection power to the substrate; a process of obtaining information about the joint temperature after stopping the supply of the inspection power; a process of determining an offset temperature of the substrate holding portion based on the information about the joint temperature; a process of adjusting the temperature of the substrate holding portion based on the control temperature after using the offset temperature; and a process of supplying the inspection power to the substrate and inspecting the substrate after adjusting the temperature of the substrate holding portion.

[0010] Effects of the Invention

[0011] According to one aspect, an inspection system and a temperature control method for inspecting a substrate while appropriately controlling the temperature can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 This is an example of a perspective view of an inspection system.

[0013] Figure 2 This is an example of a structural diagram of an inspection system.

[0014] Figure 3 This is an example of a plan view schematically showing the structure of a substrate.

[0015] Figure 4 This is an example of a flow chart explaining temperature control in an inspection system.

[0016] Figure 5 This is an example of a graph showing the temporal transition of offset temperature of an inspection electric and electronic device.

[0017] Figure 6 This is an example of a graph showing the temporal transition of the inspection power and the offset temperature of the electronic device before and after the completion of the inspection of the electronic device. DETAILED DESCRIPTION

[0018] Hereinafter, various exemplary embodiments will be described in detail with reference to the accompanying drawings. In addition, the same reference numerals are given to the same or corresponding parts in each of the drawings.

[0019] use Figure 1 An inspection system 1 as an example of an inspection system according to this embodiment will be described. Figure 1 This is an example of a perspective view of the inspection system 1 . Figure 2 is an example of a structural diagram of the inspection system 1. Figure 2 , the components built into the inspection system 1 are schematically shown as a partial cross-sectional view.

[0020] In the semiconductor manufacturing process, a large number of electronic devices D having a predetermined circuit pattern are formed on a substrate W such as a semiconductor wafer (see the following). Figure 3 The formed electronic devices D are inspected for electrical characteristics and the like and sorted into acceptable and unacceptable products. The inspection of the electronic devices D is performed using the inspection system 1 on the substrate W before each electronic device D is diced, for example.

[0021] The inspection system 1 performs temperature control while inspecting a plurality of electronic devices D (see the following) formed on a substrate W. Figure 3 That is, the inspection system 1 supplies inspection power to the electronic device D when the electronic device D is at a predetermined inspection temperature or above, and performs an inspection of the electrical characteristics and the like at that time.

[0022] The inspection system 1 includes a storage chamber 2 , a loader 3 , and a tester 4 .

[0023] The storage chamber 2 has a shell 11 with a hollow interior. The storage chamber 2 has a mounting table (also called a "chuck") 10 for mounting the substrate W inside the shell 11. The mounting table 10 has an adsorption and holding portion (not shown) for adsorbing and holding the substrate W in such a manner that the relative position of the substrate W with respect to the mounting table 10 does not deviate. In addition, the storage chamber 2 is provided with a moving mechanism (not shown) inside the shell 11 for moving the mounting table 10 in the horizontal direction and the vertical direction. Through this moving mechanism, the relative position of the probe card 12 described later and the substrate W can be adjusted so that the required electrode portion E (see the later-described electrode portion E) on the surface of the substrate W is aligned with the substrate W. Figure 3 ) contacts the probes 12 a of the probe card 12 .

[0024] The storage chamber 2 has a probe card 12 inside the housing 11. The probe card 12 is arranged above the stage 10 so as to be opposite to the stage 10. The probe card 12 includes a plurality of needle-shaped probes 12a arranged corresponding to the electrode pads or solder bumps provided corresponding to the electrode portions E of the electronic devices D of the substrate W. The probe card 12 is connected to the tester 4 via the interface 13. Each probe 12a contacts the electrode portion E of each electronic device D of the substrate W during the electrical characteristics inspection, supplies power from the tester 4 to the electronic device D via the interface 13, and transmits signals from the electronic device D to the tester 4 via the interface 13.

[0025] The loader 3 is equipped with a FOUP (Front Opening Unify Pod) serving as a transport container for storing substrates W. The loader 3 also includes a transport mechanism (not shown) for transporting substrates W. The transport mechanism removes substrates W stored in the FOUP and transports them to the mounting table 10 in the storage chamber 2. Furthermore, the transport mechanism receives substrates W from the mounting table 10 after electrical characteristics testing of electronic devices D has been completed and stores them in the FOUP.

[0026] The tester 4 includes a test board (not shown) that can reproduce a portion of the circuit structure of the motherboard on which the electronic device D is to be mounted. Furthermore, the test board of the tester 4 is connected to a tester computer 15 that determines whether the electronic device D is qualified based on signals from the electronic device D. By replacing the test board, the tester 4 can reproduce the circuit structures of various motherboards. Furthermore, the probe card 12 includes multiple probes 12a that contact multiple electrode portions E of the electronic device D. Furthermore, the tester 4 includes multiple detection units for detecting the electrical characteristics of the electronic device D. Thus, the tester 4 can detect various electrical characteristics of the electronic device D.

[0027] The inspection system 1 also includes a user interface 16 for displaying information to the user or for the user to input instructions. The user interface 16 is composed of, for example, an input unit such as a touch panel or a keyboard, and a display such as a liquid crystal display.

[0028] Thus, the inspection system 1 includes the stage 10 as a substrate holding portion that holds the substrate W. Furthermore, the inspection system 1 includes a probe card 12 having probes 12 a, an interface 13 , and a tester 4 as a testing portion that tests the electrical characteristics of the electronic device D by supplying test power to the electrode portion E of the electronic device D provided on the substrate W.

[0029] Furthermore, the loader 3 includes a temperature control unit 14 . The temperature control unit 14 includes a power supply 25 , a cooler 26 , and a control unit 90 .

[0030] A heater 20 for heating the mounting table 10 is provided on the mounting table 10. A power supply 25 supplies power to the heater 20 provided on the mounting table 10. In addition, a cooling medium flow path 10a for circulating a heat transfer medium (antifreeze, etc.) is formed inside the mounting table 10. The cooler 26 circulates the temperature-adjusted heat transfer medium in the cooling medium flow path 10a. Thus, in the inspection system 1, the temperature adjustment mechanism for adjusting the temperature of the substrate holding portion includes the heater 20, the power supply 25, the cooling medium flow path 10a, and the cooler 26. In addition, the structure of the temperature adjustment mechanism is not limited to this.

[0031] The temperature adjustment mechanism also includes a temperature detection unit 30 for detecting the temperature of the substrate holding portion. The temperature detection unit 30 is provided on the mounting stage 10 and detects the temperature Tstage of the mounting stage 10. The temperature Tstage of the mounting stage 10 detected by the temperature detection unit 30 is input to the control unit 90.

[0032] The tester 4 also includes a power detection unit 41 that detects test power (current and voltage) supplied from the tester 4 to the electronic device D via the interface 13 and the probe card 12 . The test power detected by the power detection unit 41 is input to the control unit 90 .

[0033] The tester 4 also includes a temperature estimation unit 42 that detects the junction temperature (junction temperature) Tj of the electronic device D based on the correlation between the electromotive force generated by passing a current through a PN junction (junction, such as a transistor) formed in the electronic device D. The junction temperature Tj detected by the temperature estimation unit 42 is input to the control unit 90.

[0034] The control unit 90 includes a holding unit temperature control unit 91 and an offset temperature determination unit 92. The control unit 90 controls the temperature adjustment mechanism so that the junction temperature Tj of the electronic device D (the temperature of the substrate W) becomes the inspection temperature.

[0035] The holding unit temperature control unit 91 controls the temperature adjustment mechanism so that the substrate holding unit temperature Tstage detected by the temperature detection unit 30 reaches the control temperature or the offset control temperature. Specifically, the holding unit temperature control unit 91 controls the heating amount of the heater 20 by controlling the power supply 25, thereby controlling the temperature Tstage of the mounting table 10. Alternatively, the holding unit temperature control unit 91 can also control the temperature Tstage of the mounting table 10 by controlling the cooler 26 to control the temperature of the heat transfer medium supplied by the cooler 26 to the cooling medium flow path 10a.

[0036] The offset temperature determination unit 92 determines an offset temperature of the control temperature corresponding to the test pattern and / or the test power. Thus, during testing, the holding unit temperature control unit 91 controls the temperature adjustment mechanism so that the temperature Tstage of the substrate holding unit detected by the temperature detection unit 30 becomes the offset control temperature.

[0037] Furthermore, the offset temperature determination unit 92 obtains the test power supplied to the electronic device D. For example, the offset temperature determination unit 92 obtains the test power supplied to the electronic device D by inputting the test power detected by the power detection unit 41. Alternatively, the offset temperature determination unit 92 may obtain the test power supplied to the electronic device D by inputting the test power of the test pattern recorded on the electronic device D from the tester computer 15.

[0038] Next, use Figure 3 The substrate W inspected in the above-mentioned inspection system 1 will be described. Figure 3 It is a plan view schematically showing the structure of the substrate W.

[0039] On the substrate W, etching and wiring are performed on a roughly disk-shaped silicon substrate, such as Figure 3 As shown, multiple electronic devices D are formed on the surface at predetermined intervals. Electrode portions E are formed on the surface of a substrate W, which is an electronic device D. These electrodes E are electrically connected to the circuit elements within the electronic device D. By applying a voltage to the electrode portions E, current can flow through the circuit elements within each electronic device D.

[0040] Here, for example, when testing electronic devices D such as logic ICs, the temperature estimation unit 42 that detects the junction temperature Tj may not be able to appropriately detect the junction temperature Tj due to the influence of noise or the like under the condition that a clock is generated.

[0041] Furthermore, when inspecting electronic devices D, a temperature difference occurs between the temperature Tstage of the mounting table 10 and the junction temperature Tj of the electronic devices D due to the thermal resistance between the mounting table 10 and the substrate W (electronic devices D). Therefore, when inspecting electronic devices D by controlling the temperature Tstage of the mounting table 10 so that it reaches the inspection temperature, the junction temperature Tj of the electronic devices D may become higher than the inspection temperature. This means that the electronic devices D are inspected at a temperature higher than the inspection temperature, potentially reducing the yield of the electronic devices D.

[0042] Next, use Figures 4 to 6 The temperature control in the inspection system 1 of this embodiment will be described. Figure 4 This is an example of a flowchart for explaining temperature control in the inspection system 1 .

[0043] First, the offset temperature determination process will be described using steps S101 to S107. In the offset temperature determination process, an offset temperature of the control temperature of the substrate holding portion is determined.

[0044] In step S101, the substrate holding unit temperature control unit 91 controls the substrate holding unit temperature Tstage at an initial control temperature. Specifically, the substrate holding unit temperature control unit 91 controls the temperature adjustment mechanism so that the substrate holding unit temperature Tstage detected by the temperature detection unit 30 approaches the control temperature. The initial control temperature may be, for example, a test temperature.

[0045] In step S102, the holding unit temperature control unit 91 determines whether the substrate holding unit temperature Tstage detected by the temperature detection unit 30 is within a predetermined control temperature range including the initial control temperature. If temperature Tstage is not within the control temperature range (S102: No), the process of step S102 is repeated. If temperature Tstage is within the control temperature range (S102: Yes), the control unit 90 proceeds to step S103. In the subsequent processes (steps S103 and S104), the holding unit temperature control unit 91 controls the temperature adjustment mechanism to maintain temperature Tstage within the predetermined control temperature range.

[0046] In step S103 , the tester 4 supplies inspection power to the electrode portion E of the electronic device D based on the test pattern, and inspects the electrical characteristics of the electronic device D, etc.

[0047] Figure 5 This is an example of a graph showing the time transition of the offset temperature Tjoffset of the inspection electric and electronic device D. Figure 5In the figure, the upper graph shows an example of a test pattern for the test power supplied to electronic device D. The vertical axis represents the test power supplied to electronic device D. The horizontal axis represents time. The lower graph shows an example of an offset temperature Tjoffset of electronic device D. The vertical axis represents the offset temperature Tjoffset of electronic device D. The horizontal axis represents time. Here, the offset temperature Tjoffset of electronic device D is the offset temperature of the junction temperature Tj of electronic device D relative to the test temperature. In other words, the offset temperature Tjoffset of electronic device D is the temperature obtained by subtracting the test temperature from the junction temperature Tj of electronic device D.

[0048] The test pattern includes multiple checks with different power levels. Figure 5 In the example shown, the test pattern includes a first inspection performed at inspection power P1, a second inspection performed at inspection power P2, a third inspection performed at inspection power P3, ... an i-th inspection (i is an arbitrary integer) performed at inspection power Pi.

[0049] Supplying test power to electronic device D generates heat, causing the temperature of electronic device D to rise. Specifically, the junction temperature Tj of electronic device D rises, and the offset temperature Tjoffset of electronic device D also rises. Furthermore, stopping the supply of test power after the test is complete causes the temperature of electronic device D to drop. Specifically, the junction temperature Tj of electronic device D drops, and the offset temperature Tjoffset of electronic device D also drops.

[0050] Here, during the inspection of the electronic device D, the junction temperature Tj of the electronic device D cannot be detected by the temperature estimation unit 42. Figure 5 In FIG. 1 , the offset temperature Tjoffset of the electronic device D in the range where the junction temperature Tj cannot be detected is indicated by a dotted line.

[0051] In step S103, the tester 4 supplies test power P1 to the electronic device D based on the test pattern, thereby inspecting the electrical characteristics of the electronic device D. Furthermore, the offset temperature determination unit 92 obtains the test power P1 supplied to the electronic device D during the inspection of the electronic device D shown in step S103. When the inspection of the electrical characteristics of the electronic device D is completed, the tester 4 stops supplying the test power P1.

[0052] In step S104, the offset temperature determination unit 92 obtains information regarding the junction temperature Tj after the delay time tdelay. Specifically, the offset temperature determination unit 92 detects (obtains) the change in the junction temperature Tj from the temperature estimation unit 42 after the delay time tdelay. Thus, the offset temperature determination unit 92 detects (obtains) the change in the offset temperature Tjoffset of the electronic device D after the delay time tdelay.

[0053] Figure 6 This is an example of a graph showing the time transition of the inspection power and the offset temperature Tjoffset of the electronic device D before and after the inspection of the electronic device D is completed. Figure 6 In FIG, the vertical axis represents the offset temperature Tjoffset of the electronic device D and the test power supplied to the electronic device D. The horizontal axis represents time. Figure 6 In the figure, the offset temperature Tjoffset of the electronic device D in the detected range (after the delay time tdelay) is indicated by a solid line. The offset temperature Tjoffset of the electronic device D in the undetected range (before the delay time tdelay) is indicated by a two-dot chain line. The test power supplied to the electronic device D is indicated by a dotted line.

[0054] After the delay time tdelay has elapsed since the supply of the test power was stopped, the offset temperature determination unit 92 uses the temperature estimation unit 42 to detect the change in the junction temperature Tj of the electronic device D. Then, the offset temperature determination unit 92 detects the change in the offset temperature Tjoffset of the electronic device D based on the difference between the junction temperature Tj and the test temperature. Figure 6 As shown, it is detected that the offset temperature Tjoffset of the electronic device D decreases over time.

[0055] In step S105, the offset temperature determination unit 92 calculates the peak temperature TEMPpeak during inspection. Here, the peak temperature TEMPpeak is the offset temperature Tjoffset of the electronic device D during inspection. In other words, the peak temperature TEMPpeak is the temperature increase of the junction temperature Tj of the electronic device D during inspection relative to the inspection temperature. Specifically, the peak temperature TEMPpeak is the temperature obtained by subtracting the inspection temperature from the junction temperature Tj of the electronic device D during inspection.

[0056] Here, the offset temperature Tjoffset at the time the test power supply is stopped is calculated as the peak temperature TEMPpeak. Assuming that the offset temperature Tjoffset of the electronic device D decreases over time after the test power supply is stopped, the system can be represented by a first-order delay system. The offset temperature determination unit 92 calculates the time constant T using a least squares method or other method based on the change in the offset temperature Tjoffset of the electronic device D detected in step S104.

[0057] Then, the offset temperature determination unit 92 calculates the peak temperature TEMPpeak using the following equation based on the delay time tdelay, the calculated time constant T, and the temperature TEMPob observed at the delay time.

[0058] TEMPpeak=TEMPob·exp(tdelay / T)

[0059] In step S105, the power P1 (refer to Figure 5 ) The peak temperature TEMPpeak1 when the electronic device D is inspected (refer to Figure 5 ).

[0060] In step S106 , the offset temperature determination unit 92 stores the peak temperature TEMPpeak in a storage unit (not shown).

[0061] In step S106, the offset temperature determination unit 92 determines the peak temperature TEMPpeak1 to be the peak temperature at the test power P1 (see Figure 5 ) is used to determine the offset temperature of the substrate holding portion when inspecting the electronic device D, and the inspection power P1 is associated with the peak temperature TEMPpeak1 (offset temperature of the substrate holding portion) and stored in the storage portion.

[0062] In step S107, the control unit 90 determines whether all test patterns have been completed. If all test patterns have not been completed (S107: No), the control unit 90 returns to step S102 and repeats the processing from step S102 to step S106. Thus, for the second and subsequent inspections performed at the test power P2, the test power is similarly stored in the storage unit in association with the peak temperature TEMPpeak (the offset temperature of the substrate holding unit).

[0063] When all the test patterns have been completed ( S107 : YES), the control unit 90 ends the offset temperature determination process (from step S101 to step S107 ).

[0064] Alternatively, the test power and the peak temperature TEMPpeak (offset temperature of the substrate holding unit) may be stored in the storage unit as a table. Alternatively, the offset temperature determination unit 92 may generate a function representing the relationship between the test power and the peak temperature TEMPpeak (offset temperature of the substrate holding unit) based on the information stored in the table, and store the generated function in the storage unit.

[0065] Next, the inspection process will be described using steps S108 to S111. In the inspection process, the electronic device D is inspected by offsetting the controlled temperature of the substrate holding portion using the offset temperature determined in the offset temperature determination process.

[0066] In step S108, the holding unit temperature control unit 91 controls the substrate holding unit temperature Tstage at the shifted control temperature. That is, the holding unit temperature control unit 91 controls the temperature adjustment mechanism so that the substrate holding unit temperature Tstage detected by the temperature detection unit 30 approaches the shifted control temperature.

[0067] For example, the following describes a configuration in which the tester 4 issues a command to the control unit 90. The tester 4 transmits the offset temperature of the substrate holder (the peak temperature TEMPpeak stored in step S106) corresponding to the test power for the next test to be performed according to the test pattern to the control unit 90. The control unit 90 controls the temperature adjustment mechanism using the temperature obtained by subtracting the offset temperature of the substrate holder from the control temperature, which is the initial value.

[0068] Alternatively, the tester 4 may be configured to transmit the test power for the next test to be performed according to the test pattern to the control unit 90. In this case, the control unit 90 determines the offset temperature of the substrate holding unit (the peak temperature TEMPpeak stored in step S106) corresponding to the test power, and controls the temperature adjustment mechanism using the temperature obtained by subtracting the offset temperature from the control temperature, which is the initial value.

[0069] Alternatively, a configuration may be employed in which the test power detected by the power detection unit 41 is transmitted to the control unit 90. In this case, the control unit 90 determines the offset temperature of the substrate holding unit corresponding to the test power (the peak temperature TEMPpeak stored in step S106), and controls the temperature adjustment mechanism using the temperature obtained by subtracting the offset temperature from the control temperature, which is the initial value.

[0070] In step S109, the holding portion temperature control portion 91 determines whether the temperature Tstage of the substrate holding portion detected by the temperature detection portion 30 is within the prescribed control temperature range including the offset control temperature. When the temperature Tstage is not within the control temperature range (S109: "No"), the process of step S109 is repeated. When the temperature Tstage is within the control temperature range (S109: "Yes"), the process of the control portion 90 proceeds to step S110. In the subsequent process (step S110), the holding portion temperature control portion 91 controls the temperature adjustment mechanism so that the temperature Tstage is maintained within the prescribed control temperature range. In the subsequent process (step S109), the holding portion temperature control portion 91 controls the temperature adjustment mechanism so that the temperature Tstage is maintained within the prescribed control temperature range.

[0071] In step S110 , the tester 4 supplies inspection power to the electronic device D based on the test pattern, and inspects the electrical characteristics and the like of the electronic device D.

[0072] Here, in the inspection shown in step S110 , by shifting the temperature Tstage of the substrate holding portion, the temperature of the electronic device D during the inspection can be brought close to the inspection temperature.

[0073] In step S111, the control unit 90 determines whether all test patterns have been completed. If all test patterns have not been completed (S111: No), the control unit 90 returns to step S108 and repeats the processes from step S108 to step S110. If all test patterns have been completed (S111: Yes), the control unit 90 ends the inspection process (from step S108 to step S111).

[0074] As described above, the control unit 90 can estimate the peak temperature TEMPpeak during inspection based on the temperature change of the inspected electronic device D. Thus, the junction temperature Tj during inspection can be estimated.

[0075] Furthermore, during the offset temperature determination step, the control unit 90 estimates the peak temperature TEMPpeak during inspection and stores it as the offset temperature of the substrate holder. Then, during the inspection step, the control unit 90 controls the temperature of the substrate holder using the control temperature offset by the offset temperature. This allows the electronic device D to be brought to the inspection temperature during inspection, enabling appropriate inspection. Furthermore, a decrease in the yield of the electronic device D can be prevented.

[0076] In addition, compared with a configuration in which the electronic device is provided with the electrode portion E only for detecting the junction temperature Tj, it is possible to reduce the packaging cost of the electronic device D. Furthermore, the number of probes 12 a provided on the probe card 12 can be reduced.

[0077] The inspection system 1 has been described above, but the present disclosure is not limited to the above-described embodiment and the like, and various modifications and improvements are possible within the scope of the gist of the present disclosure as described in the claims.

[0078] In addition, this application claims priority based on Japanese Patent Application No. 2023-4559 for which it applied on January 16, 2023, and incorporates the entire content of this Japanese Patent Application into this application by reference.

[0079] Description of Reference Numerals

[0080] W substrate

[0081] D Electronic devices

[0082] E electrode part

[0083] 1. Check the system

[0084] 2 Storage Room

[0085] 3 Loader

[0086] 4 tester

[0087] 10 loading platforms

[0088] 10a Cooling medium flow path

[0089] 12 probe cards

[0090] 12a probe

[0091] 13 interfaces

[0092] 14 Temperature control unit

[0093] 20 heaters

[0094] 25 Power Supply

[0095] 26. Chiller

[0096] 30 Temperature detection unit

[0097] 41 Power Detection Department

[0098] 42 Temperature estimation unit

[0099] 50 temperature control mechanism

[0100] 55 Power Supply

[0101] 90 Control Department

[0102] 91 Maintaining unit temperature control unit

[0103] 92: offset temperature determination unit.

Claims

1. An inspection system for inspecting a substrate while controlling the temperature using a temperature adjustment mechanism, comprising: a substrate holding portion for holding the substrate; a detection unit for supplying test power to the electrode portion of the substrate; and Control unit, wherein The detection unit includes a temperature estimation unit that estimates a junction temperature of a junction provided on the substrate. The control unit includes: supplying the inspection power to the substrate; a step of acquiring information on the temperature of the junction portion after stopping the supply of the inspection power; a step of determining an offset temperature of the substrate holding portion based on information on the temperature of the bonding portion; a step of adjusting the temperature of the substrate holding portion based on the controlled temperature after shifting using the offset temperature; and A step of supplying the inspection power to the substrate to inspect the substrate after adjusting the temperature of the substrate holding portion.

2. The inspection system according to claim 1, wherein: In the step of obtaining information on the temperature of the junction, A transition of an offset temperature of the bonding portion temperature is obtained, wherein the offset temperature of the bonding portion temperature is a difference between the bonding portion temperature and an inspection temperature of the substrate.

3. The inspection system according to claim 2, wherein: In the step of determining the offset temperature of the substrate holding portion, estimating the offset temperature of the junction temperature when the supply of the test power is stopped based on the change in the offset temperature of the junction temperature, The offset temperature of the substrate holding portion is determined based on the estimated offset temperature of the bonding portion temperature when the supply of the test power is stopped.

4. The inspection system according to claim 1, wherein: The temperature adjustment mechanism detects the temperature of the substrate holding portion and adjusts the temperature of the substrate holding portion.

5. The inspection system according to claim 1, wherein: The detection section includes detection units for detecting a plurality of electrical characteristics.

6. The inspection system according to claim 1, wherein: The substrate has the electrode portion and an electronic device connected to the electrode portion. The detection unit detects electrical characteristics of the electronic device to which the test power is supplied.

7. A temperature control method for an inspection system, wherein: The inspection system inspects a substrate while controlling the temperature through a temperature regulating mechanism, and includes: a substrate holding portion for holding the substrate; and a detection portion for supplying inspection power to an electrode portion of the substrate, wherein the detection portion includes a temperature estimating portion for estimating a junction temperature provided at a junction portion of the substrate. The temperature control method comprises: supplying the inspection power to the substrate; a step of acquiring information on the temperature of the junction portion after stopping the supply of the inspection power; a step of determining an offset temperature of the substrate holding portion based on information on the temperature of the bonding portion; a step of adjusting the temperature of the substrate holding portion based on the controlled temperature after shifting using the offset temperature; and A step of supplying the inspection power to the substrate to inspect the substrate after adjusting the temperature of the substrate holding portion.

8. The temperature control method according to claim 7, wherein: In the step of obtaining information on the temperature of the junction, A transition of an offset temperature of the bonding portion temperature is obtained, wherein the offset temperature of the bonding portion temperature is a difference between the bonding portion temperature and an inspection temperature of the substrate.

9. The temperature control method according to claim 8, wherein: In the step of determining the offset temperature of the substrate holding portion, estimating the offset temperature of the junction temperature when the supply of the test power is stopped based on the change in the offset temperature of the junction temperature, The offset temperature of the substrate holding portion is determined based on the estimated offset temperature of the bonding portion temperature when the supply of the test power is stopped.

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