Nonvolatile memory, sensitive amplification circuit thereof and electronic equipment
By adding a fifth transistor in series with the third transistor and the fourth transistor in the amplification module, the problem of slow pre-charge speed of nonvolatile memory bit lines is solved, and fast charging and stability improvement is achieved.
Patent Information
- Application Number
- CN202410232967.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-02-29
- Publication Date
- 2025-09-02
AI Technical Summary
In the prior art, the bit line precharge speed of nonvolatile memory is slow because the bit line parasitic capacitance is large and the reference current supply module is limited, so it is impossible to charge quickly.
A fifth transistor connected in series with the third transistor and the fourth transistor is added to the amplification module. The conduction and turn-off of the fifth transistor are affected by the bit line voltage, ensuring that the amplifier control terminal node voltage does not affect the stable state during the precharge process and increase the precharge current.
The pre-charge speed is accelerated, the stability and readout accuracy of the loop are ensured, and the bit line pre-charge time is shortened.
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Figure CN120581052A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of memory technology, and in particular to a non-volatile memory and a sensitive amplifier circuit and electronic equipment thereof. Background Art
[0002] During the memory read operation, the precharge operation generally has the greatest impact on the read speed. The reason is that the parasitic capacitance CL of the bit line (BL) path of the memory array is large (hundreds or even thousands of CELL drain capacitance and BL line capacitance, the capacitance can reach several pF). Precharging the bit line (BL) to the preset voltage requires a large amount of power; however, simply increasing the voltage VCLAMP during the precharge phase cannot guarantee fast precharging. The reason is that the reference current providing module can only provide a limited current (its current value is between the erase and programming currents of the CELL), which cannot provide sufficient drive for the amplifier tube. To solve this problem, a precharge signal is introduced. This signal controls the precharge current providing module, and the external controller divides the read cycle into two parts:
[0003] 1) Precharge phase: During this phase, PREC is at a low level, controlling the precharge current supply module to provide sufficient drive current for the precharge phase, precharging the bit line (BL) to the required voltage. During this phase, regardless of the current size of the cell, the voltage of the VSPA node is always at a high level (close to VCC);
[0004] 2) Amplification stage: During this stage, PREC becomes high, controlling the pre-charge current providing module to stop providing driving current. The reference current provided by the reference current providing module and the CELL current flowing through the amplifier tube will determine the voltage of the VSPA node, thereby determining the output. Summary of the Invention
[0005] The present application provides a non-volatile memory and a sensitive amplifier circuit and electronic device thereof, which can increase the charging speed of the bit line in the pre-charging stage.
[0006] In a first aspect, the present application provides a sensitive amplifier circuit suitable for a non-volatile memory, the sensitive amplifier circuit comprising: a reference current providing module for providing a reference current; a pre-charge current providing module for providing a charging current for a bit line in a pre-charge stage, the bit line being used to couple a memory cell; an amplifier tube, wherein a first end of the amplifier tube is coupled to the bit line, and a second end of the amplifier tube is used to couple an output end of the pre-charge current providing module and an output end of the reference current providing module; an amplifier module, the amplifier module comprising: a first transistor, wherein a first end of the first transistor is coupled to a power supply voltage end; a second transistor, wherein a first end of the second transistor is coupled to a second end of the first transistor, the second end of the second transistor is grounded, and a control end of the second transistor is coupled to the first end of the amplifier tube; a first coupling point between the second transistor and the first transistor is coupled to the control end of the amplifier tube; a third transistor, wherein a first end and a control end of the third transistor are coupled to a first coupling point; a fourth transistor, wherein a first end and a control end of the fourth transistor are coupled to the second end of the third transistor; a fifth transistor, wherein a first end of the fifth transistor is coupled to the second end of the fourth transistor, the second end of the fifth transistor is grounded, and a control end of the fifth transistor is coupled to the control end of the second transistor.
[0007] Among them, in response to the bit line voltage of the bit line being less than the threshold voltage of the fifth transistor during the pre-charging process, the fifth transistor is in a cut-off state, so that no current flows through the third transistor, the fourth transistor and the fifth transistor, thereby increasing the charging current of the bit line.
[0008] In which, in response to the bit line voltage of the bit line being greater than the threshold voltage of the fifth transistor during the pre-charging process, the fifth transistor is in a turned-on state.
[0009] In response to the fifth transistor being in the on state, the fourth transistor and the fifth transistor are turned on, so as to reduce the impedance of the first coupling point in a stable state.
[0010] When the third transistor, the fourth transistor, and the fifth transistor are all turned on, the pole frequency corresponding to the first coupling point in the frequency domain is higher than the pole frequency corresponding to the node of the bit line in the frequency domain.
[0011] The first transistor is a PMOS transistor, and the second transistor is an NMOS transistor.
[0012] The third transistor is an Nmos transistor, the fourth transistor is an Nmos transistor, and the fifth transistor is an Nmos transistor.
[0013] The fifth transistor and the second transistor are of the same device type, and a size of the fifth transistor is larger than a preset size.
[0014] The reference current providing module includes a sixth transistor, the pre-charge current providing module includes a seventh transistor, and both the sixth transistor and the seventh transistor are PMOS transistors.
[0015] In a second aspect, the present application provides a non-volatile memory, which includes the sensitive amplifier circuit provided in the first aspect.
[0016] In a third aspect, the present application provides an electronic device comprising the non-volatile memory provided in the second aspect.
[0017] The beneficial effect of the present application is that, different from the prior art, the non-volatile memory and its sensitive amplifier circuit and electronic device provided by the present application add a fifth transistor in series with the third transistor and the fourth transistor in the amplifier module. The conduction and cutoff of the fifth transistor are affected by the bit line voltage. Therefore, the fifth transistor can increase the node voltage of the control end of the amplifier tube in the pre-charging stage without basically affecting the node impedance of the control end of the amplifier tube in the stable state, thereby accelerating the pre-charging speed. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without inventive efforts. Among them:
[0019] Figure 1 This is a structural diagram of an embodiment of a sensitive amplifier circuit provided by the present application;
[0020] Figure 2 is a structural diagram of another embodiment of the sensitive amplifier circuit provided by the present application;
[0021] Figure 3 is a structural diagram of another embodiment of the sensitive amplifier circuit provided by the present application;
[0022] Figure 4 This application provides Figure 2 Schematic diagram of simulation effect of sensitive amplifier circuit;
[0023] Figure 5 This application provides Figure 3 Schematic diagram of simulation effect of sensitive amplifier circuit;
[0024] Figure 6 1 is a schematic structural diagram of an embodiment of a non-volatile memory provided by the present application;
[0025] Figure 7It is a structural diagram of an embodiment of an electronic device provided by this application. DETAILED DESCRIPTION
[0026] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. It will be understood that the specific embodiments described herein are only used to explain the present application, rather than to limit the present application. It should also be noted that, for ease of description, only some, rather than all, structures related to the present application are shown in the drawings. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.
[0027] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.
[0028] See Figure 1 , Figure 1 FIG1 is a schematic diagram of a structure of an embodiment of a sensitive amplifier circuit for non-volatile memory provided by the present application. The sensitive amplifier circuit 100 includes: a reference current providing module 10, a pre-charge current providing module 20, an amplifier transistor MN1, an amplifier module 30 and a comparison module 40.
[0029] Specifically, the sense amplifier is a common module in non-volatile memory (NVM) used to read data stored in a memory cell (CELL). It mainly consists of the following parts:
[0030] The amplifier transistor MN1 is an NMOS transistor with a common gate structure, and its source end is connected to the bit line (BL) of the memory array, serving as the input end of the amplifier MN1.
[0031] The reference current providing module 10 provides a reference current. After the bit line (BL) is precharged and the voltage stabilizes, the reference current is compared with the bit line current (CELL current) on the bit line (BL) to determine the voltage input to the comparison module 40. This is the voltage at the VSPA node. The reference current is generally set between the erased current and the programmed current of the memory cell. If the memory cell is in the erased state, its current is greater than the reference current, and the VSPA node has a lower voltage (close to the BL voltage). If the memory cell is in the programmed state, its current is less than the reference current, and the VSPA node has a higher voltage (close to the power supply voltage VCC). The reference current providing module 10 can be composed of a transistor MP1 (a sixth transistor). A first terminal of the transistor MP1 is coupled to the power supply voltage VCC, and a second terminal of the transistor MP1 is coupled to the drain terminal of the amplifier MN1. The control terminal of the transistor MP1 is turned on under the control of the control signal IREF_BIAS to provide the reference current.
[0032] The pre-charge current providing module 20 provides a current for charging the bit line (BL) during the pre-charge phase. The pre-charge current providing module 20 may be composed of a pre-charge transistor MP4 (the seventh transistor), wherein the first end of the pre-charge transistor MP4 is coupled to the power supply voltage terminal VCC, and the second end of the pre-charge transistor MP4 is coupled to the drain terminal of the amplifier MN1. The control end of the pre-charge transistor MP4 is turned on under the control of the pre-charge signal PREC to provide a pre-charge current. The pre-charge signal PREC is provided by an external controller. Both the sixth and seventh transistors are PMOS transistors.
[0033] The amplifier module 30 is a single-stage amplifier with inverting amplification, comprising a first transistor MP2 and a second transistor MN2. The first transistor MP2 acts as a current mirror to provide a bias current. The first amplifier module 30 has two functions. First, it forms a negative feedback structure with the amplifier transistor MN1 to reduce the input impedance of the sensitive amplifier circuit 100, thereby reducing the variation in the bit line voltage (BL voltage) under different CELL (memory cell) currents. Second, compared to a solution with a fixed gate bias voltage for the amplifier transistor MN1, the inverting amplification characteristics of the first amplifier module 30 can be used to provide a higher gate voltage for the amplifier transistor MN1 during the pre-charge phase, thereby accelerating pre-charge.
[0034] Comparison module 40 is used to compare the voltage of VSPA node with reference voltage VREF and output the final signal SA_OUT. Reference voltage VREF is set between the voltages corresponding to the erase state and the program state of the cell to ensure that the data stored in the cell can be correctly identified.
[0035] The working process of the sensitive amplifier circuit 100 is as follows:
[0036] 1) The bit line (BL) to be read is discharged to ground level, the word line (WL) of the cell is biased with a suitable voltage to obtain a suitable cell current, the column select signal YSEL is valid, and the column select switch MSW is turned on, so that the input end of the sensitive amplifier circuit 100 is connected to the cell to be read.
[0037] 2) Enable the sensitive amplifier circuit 100. Since there is generally a large parasitic capacitance on the bit line (BL) path, the capacitance is discharged in the above step 1), so the initial level of the input terminal of the sensitive amplifier circuit 100 is 0.
[0038] 3) Due to the inverting amplification characteristic of the first amplifying module 30, the voltage VCLAMP at the node A increases, and the amplifier MN1 is turned on to charge the bit line (BL), and the voltage of the bit line (BL) increases. This process is the pre-charge operation.
[0039] 4) When the bit line (BL) voltage reaches the threshold voltage of the second transistor MN2, the second transistor MN2 turns on, and the voltage VCLAMP at node A begins to decrease. The voltage VCLAMP and the stable voltage of the bit line (BL) are determined by the characteristics of the first amplifier module 30, the amplifier transistor MN1, and the current of the cell.
[0040] 5) After the bit line (BL) is fully charged, the current flowing through amplifier MN1 is determined by the CELL current. This current is compared with the reference current provided by reference current providing module 10 to determine the voltage at node VSPA. Comparison module 40 then outputs the final signal SA_OUT, which reflects the data stored in the CELL.
[0041] In the above process, the pre-charge operation generally has the greatest impact on the read speed. This is because the parasitic capacitance CL of the bit line (BL) path of the memory array is large (hundreds or even thousands of CELL drain capacitance and BL line capacitance, the capacitance can reach several pF). Pre-charging the bit line (BL) to a preset voltage requires a large amount of power. However, simply increasing the voltage VCLAMP of node A during the pre-charge phase cannot guarantee fast pre-charging. This is because the reference current providing module 10 can only provide a limited current (its current value is between the erase and programming currents of the CELL) and cannot provide sufficient drive for the amplifier MN1. To solve this problem, a pre-charge signal PREC is introduced. This signal controls the pre-charge current providing module 20. The external controller divides the read cycle into two parts:
[0042] 1) Precharge phase: During this phase, the precharge signal PREC is at a low level, controlling the precharge current providing module 20 to provide sufficient drive current for the precharge phase to precharge the bit line (BL) to the required voltage. During this phase, regardless of the current size of the CELL, the voltage of the VSPA node is always at a high level (close to VCC).
[0043] 2) Amplification stage: During this stage, the precharge signal PREC becomes high, controlling the precharge current providing module 20 to stop providing the driving current. The reference current provided by the reference current providing module 10 and the CELL current flowing through the amplifier MN1 will determine the voltage of the VSPA node, thereby determining the output.
[0044] The disadvantage is that the BL node is connected to the memory array BL, so the parasitic capacitance is often large (a large-capacity memory array causes the BL node to connect to the drain capacitance of hundreds or even thousands of cells and the capacitance of the BL connection, and the capacitance can reach the pF level). This makes BL a low-resistance, high-capacitance node; node A is a high-resistance, low-capacitance node (the resistance is the channel resistance of MN2 and MP2. When both MOS tubes are saturated, the resistance is very large, while the capacitance is mainly the gate capacitance of MN1 and the connection capacitance of the node, which is generally in the femtofarad level, which is very small). The corresponding pole frequencies of the low-resistance, high-capacitance bit line (BL) node and the high-resistance, low-capacitance node A in the frequency domain may be very close. According to feedback theory, the phase margin of this negative feedback loop may be very low, and there is a possibility of instability. Long-term oscillations may occur in the transient response, thereby affecting the settling speed and readout accuracy.
[0045] Based on this, the present application proposes adding two transistors (a third transistor MN3 and a fourth transistor MN4) to the amplification module. Node A is equivalent to an additional resistor connected in parallel, and both are gate-drain connections. Their equivalent resistance is very small, on the same order of magnitude as the bitline (BL) node resistance, making node A a low-resistance, low-capacitance node. The corresponding frequency in the frequency domain is much higher than the frequency in the frequency domain of the bitline (BL) node, thereby ensuring loop stability. When the current is low due to the non-erased state of the cell being read, the bitline (BL) node impedance is higher, and the difference in the frequency between the two nodes is larger, resulting in greater stability.
[0046] Specific reference Figure 2 , Figure 2 FIG1 is a schematic diagram of a structure of an embodiment of a sensitive amplifier circuit for non-volatile memory provided by the present application. The sensitive amplifier circuit 100 includes: a reference current providing module 10, a pre-charge current providing module 20, an amplifier transistor MN1 and an amplifier module 30.
[0047] The reference current providing module 10 is used to provide a reference current.
[0048] The pre-charge current providing module 20 is used to provide a charging current to the bit line during the pre-charge phase, where the bit line is used to couple to the memory cell.
[0049] A first terminal of the amplifier MN1 is coupled to the bit line (BL), and a second terminal of the amplifier MN1 is coupled to an output terminal of the pre-charge current providing module 20 and an output terminal of the reference current providing module 10 .
[0050] The amplifying module 30 includes a first transistor MP2 , a second transistor MN2 , a third transistor MN3 , and a fourth transistor MN4 .
[0051] A first terminal of the first transistor MP2 is coupled to a power supply voltage terminal;
[0052] The first terminal of the second transistor MN2 is coupled to the second terminal of the first transistor MP2. The second terminal of the second transistor MN2 is grounded. The control terminal of the second transistor MN2 is coupled to the first terminal of the amplifier. A first coupling point between the second transistor MN2 and the first transistor MP2 is coupled to the control terminal of the amplifier. The voltage at the first coupling point (node A) is VCLAMP.
[0053] The first terminal and the control terminal of the third transistor MN3 are coupled to the first coupling point.
[0054] A first terminal and a control terminal of the fourth transistor MN4 are coupled to the second terminal of the third transistor MN3 ; and a second terminal of the fourth transistor MN4 is grounded.
[0055] See Figure 2 The amplifier module 30, the amplifier tube MN1, and the bit line (BL) path together form a negative feedback structure. According to feedback theory, this negative feedback structure can effectively reduce the input resistance of the sense amplifier compared to the open-loop structure, thereby reducing the change of the BL voltage under different cell currents and improving the accuracy of the sense amplifier.
[0056] Figure 2 The working process of the sensitive amplifier circuit 100 is as follows:
[0057] 1) The bit line (BL) to be read is discharged to ground level, the word line (WL) of the cell is biased with an appropriate voltage to obtain an appropriate cell current, the column select signal YSEL is valid, and the column select switch MSW is turned on, so that the input of the sensitive amplifier circuit 100 is connected to the cell to be read.
[0058] 2) Enable the sensitive amplifier circuit 100. Since there is generally a large parasitic capacitance on the bit line (BL) path, the capacitance is discharged in the above step 1), so the initial level of the input terminal of the sensitive amplifier circuit 100 is 0.
[0059] 3) Due to the inverting amplification characteristic of the amplifier module 30, the voltage VCLAMP at the node A increases, and the amplifier tube MN1 is turned on to charge the bit line (BL), and the voltage of the bit line (BL) increases. This process is the pre-charge operation.
[0060] 4) When the bitline (BL) voltage reaches the threshold voltage of the second transistor MN2, the second transistor MN2 turns on, and the voltage VCLAMP begins to decrease. The final voltage VCLAMP and the stable voltage of the bitline (BL) are determined by the characteristics of the amplifier module 30, the amplifier transistor MN1, and the current in the cell. In a typical design, the stable voltage of the bitline (BL) is slightly higher than the threshold voltage of the second transistor MN2, while the stable voltage of the voltage VCLAMP is higher than the bitline (BL) voltage by the gate-source voltage of the amplifier transistor MN1.
[0061] 5) After the bit line (BL) is fully charged, the current flowing through amplifier MN1 is determined by the cell current. This current is compared with the reference current provided by reference current providing module 10 to determine the voltage at node VSPA. Comparison module 40 then outputs the final signal SA_OUT, which reflects the data stored in the cell, thereby completing the cell data readout.
[0062] The third transistor MN3 and the fourth transistor MN4 in the amplifier module 30 are connected in series with the gate and drain shorted, and their function is to reduce the impedance of the voltage VCLAMP of the node A in the stable state, thereby ensuring the stability of the negative feedback loop. The negative feedback loop has two main nodes, namely the bit line (BL) and the voltage VCLAMP. When the CELL being read is a deeply erased cell, the path current is large, causing the bit line (BL) node to become a low-resistance node (the large current causes the BL path and MN1 to be in a low-resistance state). Since the BL node is connected to the memory array BL, the parasitic capacitance is often large (the large-capacity memory array causes the BL node to connect to the drain capacitance of hundreds or even thousands of cells and the capacitance of the BL connection, and the capacitance can reach the pF level). This makes BL a low-resistance and high-capacitance node. With the addition of the third and fourth transistors MN3 and MN4, node A is equivalent to an additional resistor connected in parallel. Both transistors are gate-drain connected, resulting in a very low equivalent resistance, on the same order of magnitude as the bitline (BL) node resistance. This makes node A a low-resistance, low-capacitance node, with a frequency-domain pole frequency significantly higher than that of the bitline (BL) node, thus ensuring loop stability. When reading from the non-erased cell state, resulting in low current, the bitline (BL) node impedance is higher, and the difference in the pole frequencies corresponding to the two nodes is greater, resulting in greater stability.
[0063] In summary, the addition of the third transistor MN3 and the fourth transistor MN4 in the amplifying module 30 can ensure that the feedback loop of the sensitive amplifier circuit 100 has good stability when reading cells in different states.
[0064] The inventors of the present application have discovered through long-term research that, while the addition of the third transistor MN3 and the fourth transistor MN4 improves the stability of the feedback loop, it also limits the maximum voltage at node A to no more than the sum of the gate-source voltages of the third transistor MN3 and the fourth transistor MN4 (this voltage is determined by the sizes of the third transistor MN3 and the fourth transistor MN4 and the current of MP2). This reduces the precharge current of the amplifier tube MN1 during the precharge phase, thereby lowering the precharge speed.
[0065] Based on this, this application proposes Figure 2 A fifth transistor MN5 connected in series with the third transistor MN3 and the fourth transistor MN4 is added to the amplifier module 30. The conduction and cutoff of the fifth transistor MN5 are affected by the bit line voltage. Therefore, the fifth transistor MN5 can be in a cutoff state when the bit line voltage of the bit line is less than the threshold voltage of the fifth transistor MN5 during the pre-charging process, without basically affecting the node impedance of the control end of the amplifier tube MN1 in the stable state, so that no current flows through the third transistor MN3, the fourth transistor MN4 and the fifth transistor MN5, thereby increasing the node voltage of the control end of the amplifier tube in the pre-charging stage, increasing the charging current of the bit line provided by the pre-charging current providing module 20, and thus accelerating the pre-charging speed.
[0066] Specific reference Figure 3 The sensitive amplifier circuit 100 includes: a reference current providing module 10, a pre-charge current providing module 20, an amplifier tube MN1 and an amplifier module 30.
[0067] The reference current providing module 10 is used to provide a reference current.
[0068] The pre-charge current providing module 20 is used to provide a charging current to the bit line during the pre-charge phase, where the bit line is used to couple to the memory cell.
[0069] A first terminal of the amplifier MN1 is coupled to the bit line (BL), and a second terminal of the amplifier MN1 is coupled to an output terminal of the pre-charge current providing module 20 and an output terminal of the reference current providing module 10 .
[0070] The amplifying module 30 includes a first transistor MP2 , a second transistor MN2 , a third transistor MN3 , a fourth transistor MN4 , and a fifth transistor MN5 .
[0071] A first terminal of the first transistor MP2 is coupled to the power voltage terminal.
[0072] The first terminal of the second transistor MN2 is coupled to the second terminal of the first transistor MP2. The second terminal of the second transistor MN2 is grounded. The control terminal of the second transistor MN2 is coupled to the first terminal of the amplifier. A first coupling point between the second transistor MN2 and the first transistor MP2 is coupled to the control terminal of the amplifier. The voltage at the first coupling point (node A) is VCLAMP. The first transistor MP2 is a PMOS transistor, and the second transistor MN2 is an NMOS transistor.
[0073] The first terminal and the control terminal of the third transistor MN3 are coupled to the first coupling point.
[0074] The first terminal and the control terminal of the fourth transistor MN4 are coupled to the second terminal of the third transistor MN3 .
[0075] A first terminal of the fifth transistor MN5 is coupled to the second terminal of the fourth transistor MN4, a second terminal of the fifth transistor MN5 is grounded, and a control terminal of the fifth transistor MN5 is coupled to the control terminal of the second transistor MN2. The third transistor MN3 is an NMOS transistor, the fourth transistor MN4 is an NMOS transistor, and the fifth transistor MN5 is an NMOS transistor.
[0076] In response to the bit line voltage of the bit line being less than the threshold voltage of the fifth transistor MN5 during the precharging process, the fifth transistor MN5 is turned off, thereby preventing current from flowing through the third transistor MN3, the fourth transistor MN4, and the fifth transistor MN5, thereby increasing the charging current of the bit line. In some embodiments, the fifth transistor MN5 is of the same device type as the second transistor MN2, and the size of the fifth transistor MN5 is larger than a predetermined size.
[0077] Figure 3 The working process of the sensitive amplifier circuit 100 is as follows:
[0078] 1) The bit line (BL) to be read is discharged to ground level, the word line (WL) of the cell is biased with an appropriate voltage to obtain an appropriate cell current, the column select signal YSEL is valid, and the column select switch MSW is turned on, so that the input of the sensitive amplifier circuit 100 is connected to the cell to be read.
[0079] 2) Enable the sensitive amplifier circuit 100. Since there is generally a large parasitic capacitance on the bit line (BL) path, the capacitance is discharged in the above step 1), so the initial level of the input terminal of the sensitive amplifier circuit 100 is 0.
[0080] 3) Due to the inverting amplification characteristics of amplifier module 30, voltage VCLAMP increases, turning on amplifier transistor MN1 to charge the bit line (BL), increasing the voltage on the bit line (BL). This process is known as the precharge operation. In response to the bit line voltage being less than its threshold voltage during the precharge process (at the start of the precharge phase), fifth transistor MN5 is turned off, preventing current from flowing through third transistor MN3, fourth transistor MN4, and fifth transistor MN5, thereby increasing the charging current on the bit line.
[0081] 4) After the bit line (BL) voltage reaches the threshold voltage of the second transistor MN2, the second transistor MN2 turns on, and the voltage VCLAMP at node A begins to decrease. The final voltage VCLAMP and the stable voltage of the bit line (BL) are determined by the characteristics of the amplifier module 30, the amplifier MN1, and the current of the CELL. In a general design, the stable voltage of the bit line (BL) is slightly higher than the threshold voltage of the second transistor MN2, and the stable voltage of node A is higher than the bit line (BL) voltage by the gate-source voltage of the amplifier MN1. In response to the bit line voltage of the bit line being greater than the threshold voltage of the fifth transistor MN5 during the pre-charge process, the fifth transistor MN5 is turned on. In response to the fifth transistor MN5 being turned on, the fourth transistor MN4 and the fifth transistor MN5 are turned on, thereby reducing the impedance of the first coupling point in the stable state.
[0082] 5) After the BL is fully charged, the current flowing through MN1 is determined by the CELL current and compared with the reference current flowing through MP1 to determine the voltage at the VSPA node. The final signal SA_OUT is then output by the comparator CMP. This signal reflects the data stored in the CELL, thereby completing the readout of the CELL data.
[0083] Right now, Figure 3At the beginning of the precharge phase of the sensitive amplifier circuit 100, the bitline (BL) voltage is very low, the fifth transistor MN5 is in the off state, and no current flows through the branch formed by the third transistor MN3, the fourth transistor MN4, and the fifth transistor MN5. The voltage VCLAMP at node A is unaffected by the third and fourth transistors MN3 and MN4, and thus approaches VCC. This significantly increases the current flowing through the amplifier MN1 during the precharge phase, significantly improving the precharge speed. When the bitline (BL) voltage nears completion of precharge and exceeds the threshold voltage of the fifth transistor MN5, the fifth transistor MN5 begins to conduct, entering the on-state MN5. The branch formed by the third, fourth, and fifth transistors MN3, MN4, and MN5 is conductive, allowing current to flow. The fifth transistor MN5 is designed with a large width-to-length ratio, resulting in a very low drain-to-source voltage. This significantly reduces the current flowing through the branch formed by the third and fourth transistors MN3 and MN4, ensuring that the impedance of node A is largely unaffected by the fifth transistor MN5, thereby preventing any impact on the stability of the negative feedback loop.
[0084] In this embodiment, a fifth transistor MN5 is added to the amplifier module 30 and is connected in series with the third transistor MN3 and the fourth transistor MN4. The conduction and cutoff of the fifth transistor MN5 are affected by the bit line voltage. Therefore, the fifth transistor MN5 can be in a cutoff state when the bit line voltage of the bit line is less than the threshold voltage of the fifth transistor MN5 during the pre-charging process, without substantially affecting the node impedance of the control terminal of the amplifier tube MN1 in the stable state. This prevents current from flowing through the third transistor MN3, the fourth transistor MN4, and the fifth transistor MN5, thereby increasing the node voltage of the control terminal of the amplifier tube in the pre-charging stage, increasing the charging current of the bit line, and thus accelerating the pre-charging speed.
[0085] An embodiment of the present application is implemented in a 50nm NOR FLASH process, and the hspice tool is used to simulate the precharging of a BL with a load capacitance of 5pF in a memory array at a power supply voltage of 3V and an ambient temperature of 25°C. Figure 2 The simulation waveform of the sensitive amplifier circuit 100 is as follows Figure 4 As shown, Figure 3 The simulation waveform of the sensitive amplifier circuit 100 is as follows Figure 5 shown.
[0086] Figure 4 and Figure 5 The first row of waveforms is the sense amplifier enable signal (high active), the second row of waveforms is the VCLAMP voltage, the third row of waveforms is the MN1 current, and the fourth row of waveforms is the BL voltage.
[0087] like Figure 4 As shown, Figure 2The sensitive amplifier circuit 100 is limited by MN3 and MN4. At the beginning of pre-charging, the voltage VCLAMP of node A does not exceed 1.96V, the maximum current of MN1 does not exceed 133uA, and it takes 60ns for BL to be pre-charged to an error of less than 3% from the final value.
[0088] like Figure 5 As shown, Figure 3 In the sensitive amplifier circuit 100, due to the effect of MN5, the voltage VCLAMP of node A at the start of pre-charging is not limited and reaches the power supply voltage of 3V. The maximum current of MN1 reaches 274uA. The time for BL to be pre-charged to an error of less than 3% from the final value is shortened to 17ns, which greatly improves the pre-charging speed. In addition, there is no overcharging or oscillation during the BL voltage establishment process, indicating that the loop has sufficient phase margin and the stability is not affected.
[0089] See Figure 6 , Figure 6 FIG1 is a schematic diagram of the structure of an embodiment of a non-volatile memory provided by the present application. The non-volatile memory 1000 includes the sensitive amplifier circuit 100 as described above.
[0090] See Figure 7 , Figure 7 FIG2 is a schematic diagram of the structure of an electronic device according to an embodiment of the present application. The electronic device 2000 includes the non-volatile memory 1000 as described above.
[0091] In summary, the sensitive amplifier circuit 100, non-volatile memory 1000, and electronic device 2000 provided in the present application add a fifth transistor MN5 connected in series with the third transistor MN3 and the fourth transistor MN4 within the amplifier module 30 of the sensitive amplifier circuit 100. The conduction and cutoff states of the fifth transistor MN5 are affected by the bit line voltage. Therefore, the fifth transistor MN5 can be turned off during the precharging process when the bit line voltage of the bit line is less than the threshold voltage of the fifth transistor MN5, without substantially affecting the impedance of the node at the control terminal of the amplifier tube MN1 in the stable state. This prevents current from flowing through the third transistor MN3, the fourth transistor MN4, and the fifth transistor MN5, thereby increasing the node voltage at the control terminal of the amplifier tube during the precharging phase, increasing the charging current for the bit line, and thus accelerating the precharging speed.
[0092] In the several embodiments provided in this application, it should be understood that the disclosed methods and devices can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the modules or units is merely a logical functional division. In actual implementation, other division methods may be used, such as combining or integrating multiple units or components into another system, or ignoring or not implementing certain features.
[0093] If the integrated units in the above other embodiments are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) or a processor to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.
[0094] The above description is only an implementation method of the present application and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the description and drawings of this application, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.
Claims
1. A sensitive amplifier circuit suitable for non-volatile memory, characterized in that: The sensitive amplifier circuit comprises: A reference current providing module, used for providing a reference current; a precharge current providing module, configured to provide a charging current to a bit line in a precharge phase, wherein the bit line is configured to be coupled to a memory cell; an amplifier tube, wherein a first end of the amplifier tube is coupled to the bit line, and a second end of the amplifier tube is used to couple an output end of the pre-charge current providing module and an output end of the reference current providing module; An amplification module, the amplification module comprising: a first transistor, wherein a first terminal of the first transistor is coupled to a power supply voltage terminal; a second transistor, wherein a first terminal of the second transistor is coupled to the second terminal of the first transistor, the second terminal of the second transistor is grounded, and a control terminal of the second transistor is coupled to the first terminal of the amplifier tube; and a first coupling point between the second transistor and the first transistor is coupled to the control terminal of the amplifier tube; a third transistor, wherein a first terminal and a control terminal of the third transistor are coupled to the first coupling point; a fourth transistor, wherein a first terminal and a control terminal of the fourth transistor are coupled to the second terminal of the third transistor; a fifth transistor, wherein a first terminal of the fifth transistor is coupled to the second terminal of the fourth transistor, a second terminal of the fifth transistor is grounded, and a control terminal of the fifth transistor is coupled to the control terminal of the second transistor.
2. The sensitive amplifier circuit according to claim 1, characterized in that: In response to the bit line voltage of the bit line being less than the threshold voltage of the fifth transistor during the pre-charging process, the fifth transistor is in a cut-off state, so that no current flows through the third transistor, the fourth transistor and the fifth transistor, thereby increasing the charging current of the bit line.
3. The sensitive amplifier circuit according to claim 1, characterized in that: In response to the bit line voltage of the bit line being greater than the threshold voltage of the fifth transistor during the precharging process, the fifth transistor is turned on.
4. The sensitive amplifier circuit according to claim 3, characterized in that: In response to the fifth transistor being in the on state, the fourth transistor and the fifth transistor are turned on to reduce the impedance of the first coupling point in a stable state.
5. The sensitive amplifier circuit according to claim 4, characterized in that: When the third transistor, the fourth transistor, and the fifth transistor are all turned on, a pole frequency corresponding to the first coupling point in the frequency domain is higher than a pole frequency corresponding to a node of the bit line in the frequency domain.
6. The sensitive amplifier circuit according to claim 1, characterized in that: The first transistor is a Pmos transistor, the second transistor is an Nmos transistor, the third transistor is an Nmos transistor, the fourth transistor is an Nmos transistor, and the fifth transistor is an Nmos transistor.
7. The sensitive amplifier circuit according to claim 1, characterized in that: The fifth transistor and the second transistor are of the same device type, and a size of the fifth transistor is larger than a preset size.
8. The sensitive amplifier circuit according to claim 1, wherein: The reference current providing module includes a sixth transistor, the pre-charge current providing module includes a seventh transistor, and both the sixth transistor and the seventh transistor are PMOS transistors.
9. A non-volatile memory, characterized in that: The non-volatile memory includes the sensitive amplifier circuit according to any one of claims 1 to 8.
10. An electronic device, characterized in that: The electronic device includes the nonvolatile memory according to claim 9.