Trim circuit with power-on burnout protection mechanism

Abstract

The present invention relates to the field of integrated circuit chip trimming technology, and specifically discloses a trimming circuit with a power-on false burn protection mechanism, comprising: a fuse power supply unit, configured to output a fuse read / write operating voltage signal after a preset delay time when the power supply is connected and the fuse read / write unit array is in the power-on state; a fuse read / write unit array, comprising a plurality of fuse read / write units, each of which is capable of reading data stored in a fuse trim bit according to a first fuse read control signal and writing data stored in the fuse trim bit according to a first fuse write control signal; the preset delay time enables the power supply end of each fuse read / write unit in the power-on state to receive the fuse read / write operating voltage signal later than the start-up time of a logic control unit capable of issuing the first fuse read control signal and the first fuse write control signal. The trimming circuit with a power-on false burn protection mechanism provided by the present invention can prevent false fuses from burning during power-on.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit chip trimming, and in particular to a trimming circuit with a power-on false burn protection mechanism. Background Art

[0002] With the rapid development of microelectronics technology, efuse (electronic fuse) technology has been widely used in integrated circuit design for its one-time programmable nature, enabling applications such as storing calibration values, device parameters, and security authentication. However, in practice, traditional efuses can malfunction during power-up due to sudden overvoltage events and unstable logic control unit operation. This not only impacts efuse reliability but also directly affects the performance and even functionality of the entire circuit system. To address this issue, the industry is exploring more effective power-up malfunction protection mechanisms. Existing efuse circuits use simple current-limiting resistors or voltage regulators to provide basic protection, but these approaches often fail to cope with the complex power supply fluctuations and transient events encountered during power-up. This necessitates a more sophisticated and intelligent circuit design to ensure the safety and stability of the efuse during power-up.

[0003] Therefore, how to provide an efuse trimming circuit with a power-on false burn protection mechanism to improve the efuse's power-on false burn resistance capability has become a technical problem that needs to be solved urgently by those skilled in the art. Summary of the Invention

[0004] The present invention provides a trimming circuit with a power-on false burnout protection mechanism, which solves the problem in the related art that the fuse trimming circuit is prone to false fuse burnout during power-on.

[0005] As one aspect of the present invention, a trimming circuit with a power-on burnout protection mechanism is provided, comprising:

[0006] The fuse power supply unit is used to output a fuse read / write operating voltage signal after a preset delay time when the power supply is turned on and the fuse read / write unit array is in a power-on state;

[0007] A fuse read / write unit array, comprising a plurality of fuse read / write units, wherein a power supply terminal of each fuse read / write unit is configured to receive a fuse read / write operating voltage signal, a control terminal of each fuse read / write unit is configured to receive a first fuse read control signal and a first fuse write control signal, and each fuse read / write unit is capable of reading data stored in a fuse trim bit according to the first fuse read control signal and writing data stored in the fuse trim bit according to the first fuse write control signal;

[0008] Among them, the preset delay time length can make the time when the power supply end of each fuse read / write unit in the power-on state receives the fuse read / write working voltage signal later than the startup time of the logic control unit that can issue the fuse read first control signal and the fuse write first control signal.

[0009] Furthermore, the fuse power supply unit includes: a first power supply stabilization switch module, a first delay module and a power supply output module, the input end of the first power supply stabilization switch module is the input end of the fuse power supply unit, the output end of the first power supply stabilization switch module is connected to the input end of the first delay module, the output end of the first delay module is connected to the input end of the power supply output module, and the output end of the power supply output module is the output end of the fuse power supply unit;

[0010] The first power supply stabilization switch module is used to turn on the first delay module when the voltage of the power supply reaches a preset power supply voltage;

[0011] The first delay module is used to start the delay function when the first power supply stabilization switch module turns on the first delay module, and turn on the power output module when the preset delay time is reached;

[0012] The power supply output module is used to generate a fuse read / write operating voltage signal and output the fuse read / write operating voltage signal when the fuse read / write unit array is in a power-on state and the first delay module turns on the power supply output module.

[0013] Furthermore, the first power supply stabilization switch module includes: a first NOT gate and a first N-type switch tube, the input end of the first NOT gate is the input end of the first power supply stabilization switch module, the output end of the first NOT gate is connected to the control end of the first N-type switch tube, the drain end of the first N-type switch tube is the output end of the first power supply stabilization switch module, and the source end of the first N-type switch tube is connected to the signal ground.

[0014] Furthermore, the first delay module includes: a first resistor and a first capacitor, one end of the first resistor is connected to the power supply, the other end of the first resistor is connected to one end of the first capacitor, the other end of the first capacitor is connected to the signal ground, and the other end of the first resistor is also connected to the output end of the first power supply stabilization switch module.

[0015] Furthermore, the power supply output module includes: a first P-type switch tube, a second P-type switch tube, a third P-type switch tube, a fourth P-type switch tube, a second N-type switch tube, a third N-type switch tube, a fourth N-type switch tube, a second resistor and a third resistor;

[0016] The control end of the first P-type switch is connected to the first delay module, the source end of the first P-type switch is connected to the power supply, the drain end of the first P-type switch is connected to one end of the third resistor, and the other end of the third resistor is connected to the signal ground;

[0017] One end of the second resistor is connected to the power supply, the other end of the second resistor is connected to the control end of the fourth P-type switch tube, the source end of the fourth P-type switch tube is connected to the power supply, and the drain end of the fourth P-type switch tube is connected to the control end of the third P-type switch tube;

[0018] The control terminal of the second P-type switch tube is connected to the control terminal of the first P-type switch tube, the source terminal of the second P-type switch tube is connected to the power supply, and the drain terminal of the second P-type switch tube is connected to the control terminal of the third P-type switch tube;

[0019] The source terminal of the third P-type switch tube is connected to the power supply, and the drain terminal of the third P-type switch tube is the output terminal of the power output module;

[0020] The control terminal of the second N-type switch tube is connected to the control terminal of the fourth P-type switch tube, the drain terminal of the second N-type switch tube is connected to the control terminal of the third P-type switch tube, and the source terminal of the second N-type switch tube is connected to the signal ground;

[0021] The control terminal of the third N-type switch tube is connected to the drain terminal of the first P-type switch tube, the drain terminal of the third N-type switch tube is the output terminal of the power output module, and the source terminal of the third N-type switch tube is connected to the signal ground;

[0022] The control terminal of the fourth N-type switch is connected to the drain terminal of the first P-type switch, the drain terminal of the fourth N-type switch is connected to the control terminal of the second N-type switch, and the source terminal of the fourth N-type switch is connected to the signal ground.

[0023] Furthermore, the fuse power supply unit is further configured to output a fuse read operating voltage signal according to a second fuse read control signal and a fuse write operating voltage signal according to a second fuse write control signal when the fuse read / write unit array is in a normal operating state.

[0024] The fuse power supply unit includes: a second power supply stabilization switch module, a second delay module, a read power supply output module and a write power supply output module, the input end of the second power supply stabilization switch module is the input end of the fuse power supply unit, the output end of the second power supply stabilization switch module is connected to the input end of the second delay module, the output end of the second delay module is respectively connected to the input end of the read power supply output module and the input end of the write power supply output module, and the output end of the read power supply output module and the output end of the write power supply output module are both the output end of the fuse power supply unit;

[0025] The second power supply stabilization switch module is used to turn on the second delay module when the voltage of the power supply reaches a preset power supply voltage;

[0026] The second delay module is used to start the delay function when the second power supply stabilization switch module turns on the second delay module, and turn on the reading power output module or the writing power output module when the preset delay time is reached;

[0027] The read power supply output module is configured to generate a fuse read operating voltage signal and output the fuse read operating voltage signal when the second delay module turns on the read power supply output module, the fuse read / write unit array is in a normal working state, and receives a fuse read second control signal;

[0028] The write power supply output module is configured to generate a fuse write operating voltage signal and output the fuse write operating voltage signal when the second delay module turns on the write power supply output module, the fuse read / write unit array is in a normal working state, and receives a fuse write second control signal;

[0029] The output current of the read power supply output module is smaller than the output current of the write power supply output module.

[0030] Furthermore, the second power supply stabilization switch module includes: a second NOT gate and a fifth N-type switch tube, the input end of the second NOT gate is the input end of the second power supply stabilization switch module, the output end of the second NOT gate is connected to the control end of the fifth N-type switch tube, the drain end of the fifth N-type switch tube is the output end of the second power supply stabilization switch module, and the source end of the fifth N-type switch tube is connected to the signal ground.

[0031] Furthermore, the second delay module includes: a fourth resistor and a second capacitor, one end of the fourth resistor is connected to the power supply, the other end of the fourth resistor is connected to one end of the second capacitor, the other end of the second capacitor is connected to the signal ground, and the other end of the fourth resistor is also connected to the output end of the second power supply stabilization switch module.

[0032] Furthermore, the reading power supply output module includes: a fifth resistor, a sixth resistor, a fifth P-type switch tube, a sixth P-type switch tube, a seventh P-type switch tube, an eighth P-type switch tube, a sixth N-type switch tube, a seventh N-type switch tube and an eighth N-type switch tube;

[0033] The control terminal of the fifth P-type switch is connected to the second delay module, the source terminal of the fifth P-type switch is connected to the power supply, the drain terminal of the fifth P-type switch is connected to one end of the sixth resistor, and the other end of the sixth resistor is connected to the signal ground;

[0034] One end of the fifth resistor is the fuse read second control signal input end, the other end of the fifth resistor is connected to the control end of the eighth P-type switch tube, the source end of the eighth P-type switch tube is connected to the power supply, and the drain end of the eighth P-type switch tube is connected to the control end of the seventh P-type switch tube;

[0035] The control terminal of the sixth P-type switch tube is connected to the control terminal of the fifth P-type switch tube, the source terminal of the sixth P-type switch tube is connected to the power supply, and the drain terminal of the sixth P-type switch tube is connected to the control terminal of the seventh P-type switch tube;

[0036] The source terminal of the seventh P-type switch tube is connected to the power supply, and the drain terminal of the seventh P-type switch tube is the output terminal of the reading power supply output module;

[0037] The control terminal of the sixth N-type switch is connected to the control terminal of the eighth P-type switch, the drain terminal of the sixth N-type switch is connected to the control terminal of the seventh P-type switch, and the source terminal of the sixth N-type switch is connected to the signal ground;

[0038] The control terminal of the seventh N-type switch tube is connected to the drain terminal of the fifth P-type switch tube, the drain terminal of the seventh N-type switch tube is the output terminal of the reading power supply output module, and the source terminal of the seventh N-type switch tube is connected to the signal ground;

[0039] The control terminal of the eighth N-type switch tube is connected to the drain terminal of the fifth P-type switch tube, the drain terminal of the eighth N-type switch tube is connected to the control terminal of the sixth N-type switch tube, and the source terminal of the eighth N-type switch tube is connected to the signal ground.

[0040] Furthermore, the write power supply output module includes: a sixth resistor, a seventh resistor, a fifth P-type switch tube, a ninth P-type switch tube, a tenth P-type switch tube, an eleventh P-type switch tube, a seventh N-type switch tube, a ninth N-type switch tube and a tenth N-type switch tube,

[0041] The control terminal of the fifth P-type switch is connected to the second delay module, the source terminal of the fifth P-type switch is connected to the power supply, the drain terminal of the fifth P-type switch is connected to one end of the sixth resistor, and the other end of the sixth resistor is connected to the signal ground;

[0042] One end of the seventh resistor is the fuse write second control signal input end, the other end of the seventh resistor is connected to the control end of the ninth P-type switch tube, the source end of the ninth P-type switch tube is connected to the power supply, and the drain end of the ninth P-type switch tube is connected to the control end of the eleventh P-type switch tube;

[0043] The control terminal of the tenth P-type switch tube is connected to the control terminal of the fifth P-type switch tube, the source terminal of the tenth P-type switch tube is connected to the power supply, and the drain terminal of the tenth P-type switch tube is connected to the control terminal of the eleventh P-type switch tube;

[0044] The source terminal of the eleventh P-type switch tube is connected to the power supply, and the drain terminal of the eleventh P-type switch tube is the output terminal of the write power output module;

[0045] The control terminal of the seventh N-type switch tube is connected to the drain terminal of the fifth P-type switch tube, the drain terminal of the seventh N-type switch tube is the output terminal of the write power output module, and the source terminal of the seventh N-type switch tube is connected to the signal ground;

[0046] The control terminal of the ninth N-type switch is connected to the drain terminal of the fifth P-type switch, the drain terminal of the ninth N-type switch is connected to the control terminal of the ninth P-type switch, and the source terminal of the ninth N-type switch is connected to the signal ground;

[0047] The control end of the tenth N-type switch tube is connected to the control end of the ninth P-type switch tube, the drain end of the tenth N-type switch tube is connected to the control end of the eleventh P-type switch tube, and the source end of the tenth N-type switch tube is connected to the signal ground.

[0048] The present invention provides a trimming circuit with a power-on false burn protection mechanism. The fuse power supply unit provides a fuse read / write operating voltage signal with a preset delay time when the fuse read / write unit array is in the power-on state, so that the time when the power supply end of each fuse read / write unit in the fuse read / write unit array receives the fuse read / write operating voltage signal is later than the start-up time of the logic control unit that can issue the fuse read first control signal and the fuse write first control signal. Therefore, the fuse read / write operating voltage signal can be provided to the fuse read / write unit only after ensuring that each fuse read / write unit in the power-on state can receive the fuse read first control signal and the fuse write first control signal, effectively avoiding the phenomenon that the fuse read / write unit array is shocked by the current at the moment the power supply is powered on, causing the trimming fuse to burn accidentally. Moreover, by delaying the power supply, the power-on overvoltage pulse can be effectively prevented from directly acting on the trimming fuse, thereby protecting the trimming fuse from damage. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] The accompanying drawings are used to provide further understanding of the present invention and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the present invention, but do not constitute a limitation of the present invention.

[0050] Figure 1 This is a structural block diagram of the trimming circuit with a power-on burnout protection mechanism provided by the present invention.

[0051] Figure 2 A circuit schematic diagram of an embodiment of a fuse power supply unit provided by the present invention.

[0052] Figure 3 A circuit schematic diagram of another embodiment of the fuse power supply unit provided by the present invention.

[0053] Figure 4 This is a circuit schematic diagram of the fuse read / write unit provided by the present invention. DETAILED DESCRIPTION

[0054] It should be noted that, in the absence of conflict, the embodiments and features of the embodiments of the present invention may be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0055] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0056] It should be noted that the terms "first," "second," and the like in the specification and claims of the present invention and the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate for the embodiments of the present invention described herein. In addition, the terms "including," "having," and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to these processes, methods, products, or apparatuses.

[0057] In this embodiment, a trimming circuit with a power-on burnout protection mechanism is provided. Figure 1 FIG. 1 is a structural block diagram of a trimming circuit 10 with a power-on burnout protection mechanism according to an embodiment of the present invention. Figure 1 As shown, including:

[0058] The fuse power supply unit 100 is used to output a fuse read / write operating voltage signal after a preset delay time when the power supply is turned on and the fuse read / write unit array is in a power-on state;

[0059] The fuse read / write unit array 200 includes a plurality of fuse read / write units 210. The power supply terminal of each fuse read / write unit 210 is used to receive the fuse read / write operating voltage signal. The control terminal of each fuse read / write unit 210 is used to receive a first fuse read control signal and a first fuse write control signal. Each fuse read / write unit 210 can read data stored in a fuse trim bit according to the first fuse read control signal and can write data stored in the fuse trim bit according to the first fuse write control signal.

[0060] Among them, the preset delay time length can make the time when the power supply end of each fuse read and write unit 210 in the power-on state receives the fuse read and write working voltage signal later than the startup time of the logic control unit that can issue the fuse read first control signal and the fuse write first control signal.

[0061] In an embodiment of the present invention, after the fuse power supply unit 100 is connected to the power supply and the fuse read / write unit array is in the power-on state, a fuse read / write operating voltage signal is output after a preset delay time, and the control end of each fuse read / write unit 210 in the fuse read / write unit array 200 receives the first fuse read control signal and the first fuse write control signal. Due to the preset delay time of the fuse power supply unit 100, the power supply end of each fuse read / write unit 210 will receive the fuse read / write operating voltage signal only after receiving the first fuse read / write control signal, that is, the time when the power supply end of each fuse read / write unit 210 receives the fuse read / write operating voltage signal is later than the startup time of the logic control unit that can issue the first fuse read control signal and the first fuse write control signal. In this way, the fuse reading and writing operating voltage signal will be provided to the fuse reading and writing unit array only after the logic control unit that issues the fuse reading first control signal and the fuse writing first control signal is started and works normally, thereby effectively avoiding the phenomenon that the fuse reading and writing unit array is shocked by the current at the moment when the power supply is powered on, causing the fuse to burn out accidentally. By delaying the power supply, it can also effectively prevent the power-on overvoltage pulse from directly acting on the trimming fuse, thereby protecting the trimming fuse from damage.

[0062] Therefore, the present invention provides a trimming circuit with a power-on false burn protection mechanism. When the fuse read / write unit array is in the power-on state, the fuse power supply unit provides a fuse read / write working voltage signal with a preset delay time, so that the time when the power supply end of each fuse read / write unit in the fuse read / write unit array receives the fuse read / write working voltage signal is later than the start-up time of the logic control unit that can send the fuse read first control signal and the fuse write first control signal. Therefore, the fuse read / write working voltage signal can be provided to the fuse read / write unit only after ensuring that each fuse read / write unit in the power-on state can receive the fuse read first control signal and the fuse write first control signal, effectively avoiding the phenomenon that the fuse read / write unit array is shocked by the current at the moment the power supply is powered on, causing the trimming fuse to burn accidentally. Moreover, by delaying the power supply, it can also effectively prevent the power-on overvoltage pulse from directly acting on the trimming fuse, thereby protecting the trimming fuse from damage.

[0063] As a specific real-time method, such as Figure 2 As shown, the fuse power supply unit 100 includes: a first power supply stabilization switch module 110, a first delay module 120 and a power supply output module 130, the input end of the first power supply stabilization switch module 110 is the input end of the fuse power supply unit 100, the output end of the first power supply stabilization switch module 110 is connected to the input end of the first delay module 120, the output end of the first delay module 120 is connected to the input end of the power supply output module 130, and the output end of the power supply output module 130 is the output end of the fuse power supply unit 100;

[0064] The first power supply stabilization switch module 110 is used to turn on the first delay module when the voltage of the power supply reaches a preset power supply voltage;

[0065] The first delay module 120 is used to start the delay function when the first power supply stabilization switch module turns on the first delay module, and turn on the power output module when the preset delay time is reached;

[0066] The power supply output module 130 is configured to generate a fuse read / write operating voltage signal and output the fuse read / write operating voltage signal when the fuse read / write unit array is in a power-on state and the first delay module turns on the power supply output module.

[0067] It should be understood that in an embodiment of the present invention, the input end of the first power supply stabilization switch module 110 is connected to the power supply, and can turn on the first delay module when the voltage of the power supply reaches a preset power supply voltage. For example, if the preset power supply voltage is 5V, then when the voltage of the power supply is lower than 5V, the first power supply stabilization switch module 110 is in a state of output closure, and when the voltage of the power supply reaches 5V, the first delay module 120 is turned on. The first power supply stabilization switch module 110 can effectively ensure that the output preset power supply voltage is the power supply voltage in the stable state of the power supply, avoid outputting the power supply voltage in the climbing state, and thus effectively avoid fluctuations in the working state caused by unstable power supply voltage.

[0068] Specifically, if Figure 2 As shown, the first power supply stabilization switch module 110 includes: a first NOT gate X201 and a first N-type switch tube MN201, the input end of the first NOT gate X201 is the input end of the first power supply stabilization switch module 110, the output end of the first NOT gate X201 is connected to the control end of the first N-type switch tube MN201, the drain end of the first N-type switch tube MN201 is the output end of the first power supply stabilization switch module 110, and the source end of the first N-type switch tube MN201 is connected to the signal ground GND.

[0069] It should be understood that when the voltage of the power supply received at the input end of the first power supply stabilization switch module 110 is lower than the preset power supply voltage, that is, the input end of the first NOT gate X201 is a low-level signal, then the control end of the first N-type switch tube MN201 is a high-level signal. At this time, the drain-source of the first N-type switch tube MN201 is connected to directly pull down the power supply VDD of the delay module, that is, the first delay module cannot work; and when the voltage of the power supply received at the input end of the first power supply stabilization switch module 110 reaches the preset power supply voltage, the input end of the first NOT gate X201 (that is, the enable control line VDDOK_P of the fuse power supply unit) is a high-level signal, and the control end of the first N-type switch tube MN201 is a low-level signal. At this time, the first delay module 120 can enter the working state.

[0070] In the embodiment of the present invention, the first delay module 120 can adjust the preset delay time according to the parameters of the capacitor and the resistor. Figure 2 As shown, the first delay module 120 includes: a first resistor R201 and a first capacitor C201, one end of the first resistor R201 is connected to the power supply, the other end of the first resistor R201 is connected to one end of the first capacitor C201, the other end of the first capacitor C201 is connected to the signal ground GND, and the other end of the first resistor R201 is also connected to the output end of the first power supply stabilization switch module 110.

[0071] Specifically, the delay time parameter of the first delay module 120 can be set by the parameter values ​​of the first resistor R201 and the first capacitor C201.

[0072] In the embodiment of the present invention, the delay time , where time is in seconds, voltage is in volts, resistance is in ohms, and capacitance is in farads. R represents the resistance of the first resistor R201, C represents the capacitance of the first capacitor C201, and VDD represents the voltage of the power supply, which can be a preset power supply voltage. VDD-Vout equals the turn-on voltage Vt of the first P-type switch MP201. By adjusting the specific value of RC, a suitable delay time can be set.

[0073] In the embodiment of the present invention, Figure 2 As shown, the power output module 130 includes: a first P-type switch tube MP201, a second P-type switch tube MP202, a third P-type switch tube MP203, a fourth P-type switch tube MP204, a second N-type switch tube MN202, a third N-type switch tube MN203, a fourth N-type switch tube MN204, a second resistor R202 and a third resistor R203;

[0074] The control end of the first P-type switch MP201 is connected to the first delay module 120 (specifically, connected to the other end of the first resistor R201 of the first delay module 120), the source end of the first P-type switch MP201 is connected to the power supply VDD, the drain end of the first P-type switch MP201 is connected to one end of the third resistor R203, and the other end of the third resistor R203 is connected to the signal ground GND;

[0075] One end of the second resistor R202 is connected to the power supply VDD, the other end of the second resistor R202 is connected to the control end of the fourth P-type switch transistor MP204, the source end of the fourth P-type switch transistor MP204 is connected to the power supply VDD, and the drain end of the fourth P-type switch transistor MP204 is connected to the control end of the third P-type switch transistor MP203;

[0076] The control terminal of the second P-type switch transistor MP202 is connected to the control terminal of the first P-type switch transistor MP201, the source terminal of the second P-type switch transistor MP202 is connected to the power supply VDD, and the drain terminal of the second P-type switch transistor MP202 is connected to the control terminal of the third P-type switch transistor MP203;

[0077] The source terminal of the third P-type switch MP203 is connected to the power supply VDD, and the drain terminal of the third P-type switch MP203 is the output terminal of the power output module 130;

[0078] The control terminal of the second N-type switch transistor MN202 is connected to the control terminal of the fourth P-type switch transistor MP204, the drain terminal of the second N-type switch transistor MN202 is connected to the control terminal of the third P-type switch transistor MP203, and the source terminal of the second N-type switch transistor MN202 is connected to the signal ground GND;

[0079] The control terminal of the third N-type switch MN203 is connected to the drain terminal of the first P-type switch MP201 . The drain terminal of the third N-type switch MN203 is the output terminal of the power output module 130 . The source terminal of the third N-type switch MN203 is connected to the signal ground GND.

[0080] The control terminal of the fourth N-type switch tube MN204 is connected to the drain terminal of the first P-type switch tube MP201 , the drain terminal of the fourth N-type switch tube MN204 is connected to the control terminal of the second N-type switch tube MN202 , and the source terminal of the fourth N-type switch tube MN204 is connected to the signal ground GND.

[0081] In this embodiment of the present invention, when the power supply VDD is first powered on, because the voltage across the first capacitor C201 cannot change suddenly, the gate voltages of the first and second P-type switching transistors MP201 and MP202 are low, and both the first and second P-type switching transistors MP201 and MP202 are in the on state. The on-state of the first P-type switching transistor MP201 causes the gate voltages of the fourth and third N-type switching transistors MN204 and MN203 to be high, turning both transistors on. The on-state of the fourth N-type switching transistor MN204 causes the gate voltages of the second and fourth P-type switching transistors MN202 and MP204 to be low, turning the second N-type switching transistor MN202 off and the fourth P-type switching transistor MP204 on. Because the second P-type switch MP202 and the fourth P-type switch MP204 are turned on and the second N-type switch MN202 is turned off, the gate voltage of the third P-type switch MP203 is high and turned off. However, the third N-type switch MN203 is turned on again. Therefore, the fuse read / write operating voltage signal VFUSE outputted by the output line is equal to the signal ground GND voltage.

[0082] As the power supply VDD voltage rises to a level sufficient for normal logic operation, the enable control line VDDOK_P of the fuse power supply unit goes high, causing the output of the NOT gate X201 to go low. This means that the control terminal of the first N-type switch MN201 goes low, turning it off. At this point, the power supply VDD begins charging the first capacitor C201 through the first resistor R201. The gate voltages of the first and second P-type switches MP201 and MP202 gradually increase. After a certain period of time, both the first and second P-type switches MP201 and MP202 turn off. The shutdown of the first P-type switch MP201 causes the gate voltages of the fourth and third N-type switches MN204 and MN203 to go low, turning them off. The shutdown of the fourth N-type switch MN204 causes the gate voltages of the second and fourth N-type switches MN202 and MP204 to go high, turning the second N-type switch MN202 on and the fourth P-type switch MP204 off. Since the second P-type switch MP202 and the fourth P-type switch MP204 are both turned off and the second N-type switch MN202 is turned on, the gate voltage of the third P-type switch MP203 is low and turned on. However, the third N-type switch MN203 is turned off. Therefore, the fuse read / write operating voltage signal VFUSE outputted by the output line is equal to the power supply VDD voltage.

[0083] Therefore, in the trimming circuit with a power-on false burning protection mechanism provided by the present invention, at the initial stage of power-on, the fuse power supply unit will not immediately supply power to the fuse read / write unit array. Instead, a preset delay time is used to ensure that a stable power supply is provided to the fuse read / write unit array only after the logic control unit that issues the first fuse read control signal and the first fuse write control signal is started and operates normally. This not only avoids the problem of false burning of the trimming fuse caused by the current impact on the fuse read / write unit array at the moment of power-on, but also effectively prevents the power-on overvoltage pulse from directly acting on the trimming fuse through the delayed power supply, thereby further protecting the trimming fuse from damage.

[0084] As another specific implementation of the fuse power supply unit, in order to further avoid the phenomenon of fuse burning when the fuse read and write unit array is in normal working state, the fuse power supply unit 100 is also used to output a fuse read operating voltage signal according to the fuse read second control signal and output a fuse write operating voltage signal according to the fuse write second control signal when the fuse read and write unit array 200 is in normal working state.

[0085] Specifically, if Figure 3 As shown, the fuse power supply unit 100 includes: a second power supply stabilization switch module 140, a second delay module 150, a read power supply output module 160 and a write power supply output module 170, the input end of the second power supply stabilization switch module 140 is the input end of the fuse power supply unit 100, the output end of the second power supply stabilization switch module 140 is connected to the input end of the second delay module 150, the output end of the second delay module 150 is respectively connected to the input end of the read power supply output module 160 and the input end of the write power supply output module 170, the output end of the read power supply output module 160 and the output end of the write power supply output module 170 are both the output end of the fuse power supply unit 100;

[0086] The second power supply stabilization switch module 140 is used to turn on the second delay module when the voltage of the power supply reaches a preset power supply voltage;

[0087] The second delay module 150 is used to start the delay function when the second power supply stabilization switch module turns on the second delay module, and turn on the reading power output module or the writing power output module when the preset delay time is reached;

[0088] The read power supply output module 160 is configured to generate a fuse read operating voltage signal and output the fuse read operating voltage signal when the second delay module turns on the read power supply output module, the fuse read / write unit array is in a normal working state, and receives a fuse read second control signal;

[0089] The write power supply output module 170 is configured to generate a fuse write operating voltage signal and output the fuse write operating voltage signal when the second delay module turns on the write power supply output module, the fuse read / write unit array is in a normal working state, and receives a fuse write second control signal;

[0090] The output current of the read power output module 160 is smaller than the output current of the write power output module 170 .

[0091] It should be understood that the fuse power supply unit 100 can output a fuse read / write operating voltage signal after a preset delay period during the power-up period of the fuse read / write unit array 200, and generate a fuse read operating voltage signal based on the second fuse read control signal and output a fuse write operating voltage signal based on the second fuse write control signal when the fuse read / write unit array 200 enters the operating state. It should be noted that to prevent erroneous fuse burning during operation, the output current of the read power supply output module is less than the output current of the write power supply output module. This ensures that the fuse read / write unit array 200 can properly complete fuse trimming during the write period (fuse trimming can be completed because the current reaches the fuse trimming current) and prevents erroneous fuse burning during the read period (fuse burning will not occur because the current during the read period is less than the fuse trimming current).

[0092] Specifically, if Figure 3 As shown, the second power supply stabilization switch module 140 includes: a second NOT gate X401 and a fifth N-type switch tube MN401, the input end of the second NOT gate X401 is the input end of the second power supply stabilization switch module 140, the output end of the second NOT gate X401 is connected to the control end of the fifth N-type switch tube MN401, the drain end of the fifth N-type switch tube MN401 is the output end of the second power supply stabilization switch module 140, and the source end of the fifth N-type switch tube MN401 is connected to the signal ground GND.

[0093] It should be understood that when the voltage of the power supply received at the input end of the second power supply stabilization switch module 140 is lower than the preset power supply voltage, that is, the input end of the second NOT gate X401 is a low-level signal, then the control end of the fifth N-type switch tube MN401 is a high-level signal. At this time, the drain-source of the fifth N-type switch tube MN401 is connected to directly pull down the power supply VDD of the delay module, that is, the second delay module cannot work; and when the voltage of the power supply received at the input end of the second power supply stabilization switch module 140 reaches the preset power supply voltage VDDOK_P, the input end of the second NOT gate X401 is a high-level signal, and the control end of the fifth N-type switch tube MN401 is a low-level signal. At this time, the second delay module 150 can enter the working state.

[0094] In the embodiment of the present invention, Figure 3 As shown, the second delay module 150 may specifically include: a fourth resistor R401 and a second capacitor C401, one end of the fourth resistor R401 is connected to the power supply VDD, the other end of the fourth resistor R401 is connected to one end of the second capacitor C401, the other end of the second capacitor C401 is connected to the signal ground GND, and the other end of the fourth resistor R401 is also connected to the output end of the second power supply stabilization switch module 140.

[0095] Specifically, the delay time parameter of the second delay module 150 can be set by the parameter values ​​of the fourth resistor R401 and the second capacitor C401.

[0096] In the embodiment of the present invention, the delay time , where time is in seconds, voltage is in volts, resistance is in ohms, and capacitance is in farads. R represents the resistance of the fourth resistor R401, C represents the capacitance of the second capacitor C401, and VDD represents the voltage of the power supply, which can be a preset power supply voltage. VDD-Vout equals the turn-on voltage Vt of the fifth P-type switch MP401. By adjusting the specific value of RC, a suitable delay time can be set.

[0097] In the embodiment of the present invention, Figure 3 As shown, the reading power supply output module 160 includes: a fifth resistor R402, a sixth resistor R403, a fifth P-type switch transistor MP401, a sixth P-type switch transistor MP402, a seventh P-type switch transistor MP403, an eighth P-type switch transistor MP404, a sixth N-type switch transistor MN402, a seventh N-type switch transistor MN403 and an eighth N-type switch transistor MN404;

[0098] The control terminal of the fifth P-type switch MP401 is connected to the second delay module 150 (specifically, connected to the other end of the fourth resistor R401 of the second delay module 150), the source terminal of the fifth P-type switch MP401 is connected to the power supply VDD, the drain terminal of the fifth P-type switch MP401 is connected to one end of the sixth resistor R403, and the other end of the sixth resistor R403 is connected to the signal ground GND;

[0099] One end of the fifth resistor R402 is the fuse read second control signal input terminal RD2_P, the other end of the fifth resistor R402 is connected to the control terminal of the eighth P-type switch transistor MP404, the source end of the eighth P-type switch transistor MP404 is connected to the power supply VDD, and the drain end of the eighth P-type switch transistor MP404 is connected to the control terminal of the seventh P-type switch transistor MP403;

[0100] The control terminal of the sixth P-type switch transistor MP402 is connected to the control terminal of the fifth P-type switch transistor MP401, the source terminal of the sixth P-type switch transistor MP402 is connected to the power supply VDD, and the drain terminal of the sixth P-type switch transistor MP402 is connected to the control terminal of the seventh P-type switch transistor MP403;

[0101] The source terminal of the seventh P-type switch MP403 is connected to the power supply VDD, and the drain terminal of the seventh P-type switch MP403 is the output terminal VFUSE of the reading power supply output module 160;

[0102] The control terminal of the sixth N-type switch MN402 is connected to the control terminal of the eighth P-type switch MP404, the drain terminal of the sixth N-type switch MN402 is connected to the control terminal of the seventh P-type switch MP403, and the source terminal of the sixth N-type switch MN402 is connected to the signal ground GND;

[0103] The control terminal of the seventh N-type switch MN403 is connected to the drain terminal of the fifth P-type switch MP401 . The drain terminal of the seventh N-type switch MN403 is the output terminal VFUSE of the read power output module 160 . The source terminal of the seventh N-type switch MN403 is connected to the signal ground GND.

[0104] The control terminal of the eighth N-type switch tube MN404 is connected to the drain terminal of the fifth P-type switch tube MP401 , the drain terminal of the eighth N-type switch tube MN404 is connected to the control terminal of the sixth N-type switch tube MN402 , and the source terminal of the eighth N-type switch tube MN404 is connected to the signal ground GND.

[0105] Specifically, if Figure 3 As shown, the write power supply output module 170 includes: a sixth resistor R403, a seventh resistor R404, a fifth P-type switch transistor MP401, a ninth P-type switch transistor MP405, a tenth P-type switch transistor MP406, an eleventh P-type switch transistor MP407, a seventh N-type switch transistor MN403, a ninth N-type switch transistor MN405, and a tenth N-type switch transistor MN406.

[0106] The control terminal of the fifth P-type switch MP401 is connected to the second delay module 150 (specifically, connected to the other end of the fourth resistor R401 of the second delay module 150), the source terminal of the fifth P-type switch MP401 is connected to the power supply VDD, the drain terminal of the fifth P-type switch MP401 is connected to one end of the sixth resistor R403, and the other end of the sixth resistor R403 is connected to the signal ground GND;

[0107] One end of the seventh resistor R404 is the fuse write second control signal input terminal WR2_P, the other end of the seventh resistor R404 is connected to the control terminal of the ninth P-type switch transistor MP405, the source end of the ninth P-type switch transistor MP405 is connected to the power supply, and the drain end of the ninth P-type switch transistor MP405 is connected to the control terminal of the eleventh P-type switch transistor MP407;

[0108] The control terminal of the tenth P-type switch transistor MP406 is connected to the control terminal of the fifth P-type switch transistor MP401, the source terminal of the tenth P-type switch transistor MP406 is connected to the power supply, and the drain terminal of the tenth P-type switch transistor MP406 is connected to the control terminal of the eleventh P-type switch transistor MP407;

[0109] The source terminal of the eleventh P-type switch MP407 is connected to the power supply VDD, and the drain terminal of the eleventh P-type switch MP407 is the output terminal VFUSE of the write power supply output module 170;

[0110] The control terminal of the seventh N-type switch MN403 is connected to the drain terminal of the fifth P-type switch MP401 . The drain terminal of the seventh N-type switch MN403 is the output terminal VFUSE of the write power output module 170 . The source terminal of the seventh N-type switch MN403 is connected to the signal ground GND.

[0111] The control terminal of the ninth N-type switch transistor MN405 is connected to the drain terminal of the fifth P-type switch transistor MP401, the drain terminal of the ninth N-type switch transistor MN405 is connected to the control terminal of the ninth P-type switch transistor MP405, and the source terminal of the ninth N-type switch transistor MN405 is connected to the signal ground;

[0112] The control terminal of the tenth N-type switch tube MN406 is connected to the control terminal of the ninth P-type switch tube MP405 , the drain terminal of the tenth N-type switch tube MN406 is connected to the control terminal of the eleventh P-type switch tube MP407 , and the source terminal of the tenth N-type switch tube MN406 is connected to the signal ground GND.

[0113] The following combination Figure 3 The specific working process of the fuse power supply unit in the embodiment of the present invention during the power-on period and the normal working period of the fuse reading and writing unit is described in detail.

[0114] When VDD is first powered on, because the voltage across the second capacitor C401 cannot change suddenly, the gate voltages of the fifth, sixth, and tenth P-type switching transistors MP401, MP402, and MP406 are low, and all three P-type switching transistors MP401, MP402, and MP406 are in the on state. The conduction of the fifth P-type switching transistor MP401 causes the gate voltages of the eighth, seventh, and ninth N-type switching transistors MN404, MN403, and MN405 to be high, turning all three N-type switching transistors on. The conduction of the eighth N-type switching transistor MN404 causes the gate voltages of both the sixth and eighth P-type switching transistors MN402 and MP404 to be low, turning the sixth N-type switching transistor MN402 off and the eighth P-type switching transistor MP404 on. Because the sixth and eighth P-type switches MP402 and MP404 are both conductive, while the sixth N-type switch MN402 is turned off, the gate voltage of the seventh P-type switch MP403 is high, turning it off. Because the ninth N-type switch MN405 is conductive, the gate voltages of the tenth and ninth N-type switches MN406 and MP405 are both low, turning the tenth N-type switch MN406 off while the ninth P-type switch MP405 is conductive. Because the ninth and tenth P-type switches MP405 and MP406 are both conductive, while the tenth N-type switch MN406 is turned off, the gate voltage of the eleventh P-type switch MP407 is high, turning it off. Because the seventh and eleventh P-type switches MP403 and MP407 are both turned off while the seventh N-type switch MN403 is conductive, the output line VFUSE is equal to the signal ground GND voltage.

[0115] As the power supply VDD voltage rises to a level sufficient for normal logic operation, the control line VDDOK_P goes high, driving the output of the second NOT gate X401 low. This causes the gate of the fifth N-type switch MN401 to go low, turning it off. At this point, the power supply VDD begins charging the second capacitor C401 through the fourth resistor R401. The gate voltages of the fifth, sixth, and tenth P-type switches MP401, MP402, and MP406 gradually increase. After a certain period of time, all three P-type switches MP401, MP402, and MP406 are turned off. The shutdown of the fifth P-type switch MP401 causes the gate voltages of the eighth, seventh, and ninth N-type switches MN404, MN403, and MN405 to go low, turning them off. At this time, the external read control line, or the second fuse read control signal input terminal RD2_P, is low. The gates of the sixth N-type switch MN402 and the eighth P-type switch MP404 are low, turning off the sixth N-type switch MN402 and turning on the eighth P-type switch MP404. Because the eighth P-type switch MP404 is turned on, the sixth N-type switch MN402 and the sixth P-type switch MP402 are turned off, causing the gate voltage of the seventh P-type switch MP403 to be high, turning it off. At this time, the external write control line, or the second fuse write control signal input terminal WR2_P, is low. The gates of the tenth N-type switch MN406 and the ninth P-type switch MP405 are low, turning off the tenth N-type switch MN406 and the ninth P-type switch MP405. Because the ninth P-type switch MP405 is turned on, the tenth N-type switch MN406 and the tenth P-type switch MP406 are turned off, causing the gate voltage of the eleventh P-type switch MP407 to be high, turning it off. Because the seventh P-type switch MP403, the eleventh P-type switch MP407, and the seventh N-type switch MN403 are all off, the output line VFUSE is in a high-impedance state, and power cannot be supplied to the fuse read / write array. Specifically, during the initial power-up phase, before the fuse read / write unit array receives the first fuse read control signal and the first fuse write control signal, the fuse power supply unit does not supply power to the fuse read / write unit array. This prevents the fuse read / write unit array from being subjected to a current surge during power-up, potentially causing the trimming fuse to burn out.

[0116] Therefore, during the entire power-on process, since the seventh P-type switch tube MP403 and the eleventh P-type switch tube MP407 of the fuse power supply tube are always closed, the programming tube MN301 can be opened due to power overvoltage shock or logic interference at the moment of power-on (such as Figure 4 to prevent the fuse from burning accidentally.

[0117] After the power supply is properly powered on, that is, after the fuse read / write unit array enters normal operation, during fuse data programming, the second fuse write control signal input terminal WR2_P in the fuse power supply unit is high, and the ninth N-type switch MN405 is turned off. This causes the gates of the tenth N-type switch MN406 and the ninth P-type switch MP405 to be high, turning the tenth N-type switch MN406 on while the ninth P-type switch MP405 is turned off. Because the tenth N-type switch MN406 is turned on, while the ninth and tenth P-type switches MP405 and MP406 are turned off, the gate of the eleventh P-type switch MP407 is turned low, turning it on. Because the eleventh P-type switch MP407 is turned on while the seventh N-type switch MN403 and MP403 are turned off, the output line VFUSE is equal to the VDD voltage. At the same time, the first write control line WR_P in the fuse read / write unit, i.e., the first fuse write control signal, goes high, turning on MN301 in the fuse read / write unit. Because the eleventh P-type switch MP407 and MN301 in the fuse read / write unit are turned on simultaneously and their current capability is greater than the fuse write current, fuse RF301 is ensured to blow.

[0118] After the power supply is properly powered on, when fuse data is read, the second fuse read control signal input terminal RD2_P in the fuse supply unit is high, and the eighth N-type switch MN404 is turned off. This causes the gates of the sixth N-type switch MN402 and the eighth P-type switch MP404 to be high, turning the sixth N-type switch MN402 on while the eighth P-type switch MP404 is turned off. With the sixth N-type switch MN402 turned on and the eighth P-type switch MP404 and the sixth P-type switch MP402 both turned off, the gate of the seventh P-type switch MP403 is low, turning it on. With the seventh P-type switch MP403 turned on while the seventh N-type switch MN403 and the eleventh P-type switch MP407 are both turned off, the output line VFUSE is equal to the VDD voltage. At the same time, the first read control line RD_P in the fuse read / write unit, i.e., the fuse read first control signal, is high, so that MN302 in the fuse read / write unit is turned on, and VPBIAS provides a bias voltage to MP301 to turn on MP301. At this time, the fuse data is read normally and output through X301.

[0119] In this embodiment of the present invention, the eleventh P-type switch MP407 serves as the power supply for fuse programming. When conducting, its output current capability exceeds the current required to blow the trimmed fuse (100mA to 150mA). The seventh P-type switch MP403 serves as the power supply for fuse reading. When conducting, its output current capability is significantly lower than the current required to blow the trimmed fuse (100mA to 150mA), typically controlled to a few to ten milliamperes. The second fuse reading control signal (i.e., the false trimming control signal) controls the seventh P-type switch MP403 to conduct only during data reading. This significantly reduces the probability of both the eleventh P-type switch MP407 in the fuse power supply unit and the NMOS transistor MN301 in the fuse reading / writing unit being simultaneously disturbed and turned on. Even if the NMOS transistor MN301 in the fuse read / write unit is disturbed and is in the on state, the output current of the seventh P-type switch transistor MP403 is much smaller than the current required to burn out the fuse trimming resistor (100mA to 150mA). Therefore, the trimming fuse RF301 in the fuse read / write unit will not be burned out, thereby greatly protecting the fuse from being accidentally trimmed during the data reading period.

[0120] In the embodiment of the present invention, Figure 4 , which is a circuit schematic diagram of each fuse read / write unit in the fuse read / write unit array 200 .

[0121] Specifically, the fuse read / write unit array 200 includes N fuse read / write units X1, X2, ..., XN. The specific number of fuse read / write units to be used can be determined according to actual circuit requirements.

[0122] like Figure 4 As shown, each fuse read / write unit 210 may specifically include: an N-type switch tube MN301, an N-type switch tube MN302, a P-type switch tube MP301, a resistor R301, a fuse RF301, a current source I301, an inverter X301, a three-state output inverter X302, a power supply line VFUSE, a write control line WR_P, a read control line RD_P, an output line DOUT and a bias voltage control line VPBIAS.

[0123] The source and substrate of the N-type switch MN301 are connected to signal GND. Its drain is connected to the source and substrate of the P-type switch MP301, and to one end of a fuse RF301. The other end of the fuse RF301 is connected to the power supply line VFUSE. The gate of the N-type switch MN301 is connected to one end of a resistor R301 and is controlled by a signal on the write control line WR_P. The other end of the resistor R301 is connected to signal ground GND.

[0124] The source and substrate of the N-type switch MN302 are connected to one terminal of the current source I301, while the other terminal of the current source I301 is connected to the signal ground GND. The drain of the N-type switch MN302 is connected to the drain of the P-type switch MP301, to the input of the inverter X301, and to the output of the three-state output inverter X302. The gate of the N-type switch MN302 is connected to the control terminal of the three-state output inverter X302 and is controlled by the read control line RD_P. The gate of the P-type switch MP301 is controlled by the bias voltage control line VPBIAS. The output of the inverter X301 is connected to the input of the three-state output inverter X302 and to the output line DOUT.

[0125] In summary, the present invention provides a trimming circuit with a power-on false burn protection mechanism. In the initial stage of power-on, the fuse power supply unit will not immediately supply power to the fuse read-write unit array. Instead, a preset delay time is used to ensure that the logic control unit that sends the first fuse read control signal and the first fuse write control signal is started and works normally before it starts to provide a stable power supply to the fuse read-write unit array. This not only avoids the problem of the trimming fuse being accidentally burned by the current impact on the fuse read-write unit array at the moment of power-on, but also effectively prevents the power-on overvoltage pulse from directly acting on the trimming fuse by delaying the power supply, thereby further protecting the circuit. The trimming fuse is protected from damage; during the normal operation of the fuse read / write unit array, a fuse read operating voltage signal can be generated based on the fuse read second control signal, and a fuse write operating voltage signal can be output based on the fuse write second control signal, and the output current of the read power supply output module is less than the output current of the write power supply output module. This can ensure that the fuse read / write unit array completes the fuse trimming normally during the write period (since the current reaches the fuse trimming current, the fuse trimming can be completed), and can also prevent the fuse from being accidentally burned during the read period (since the current during the read period is less than the fuse trimming current, the fuse will not be accidentally burned). In addition, the fuse read / write unit array includes multiple fuse read / write units, and each unit can perform accurate read and write operations through a logic control unit, thereby improving the reliability and safety of the circuit. In summary, the trimming circuit with a power-on mis-burning protection mechanism provided by the present invention can not only effectively prevent power-on mis-burning and mis-burning of trimming, but also has good compatibility and scalability, and is suitable for various electronic devices that require fuse trimming functions, providing a strong guarantee for the safe operation of electronic devices.

[0126] It will be understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present invention, and the present invention is not limited thereto. Those skilled in the art will appreciate that various modifications and improvements can be made without departing from the spirit and substance of the present invention, and such modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A trimming circuit with a power-on burnout protection mechanism, characterized in that: include: The fuse power supply unit is used to output a fuse read / write operating voltage signal after a preset delay time when the power supply is turned on and the fuse read / write unit array is in a power-on state; A fuse read / write unit array, comprising a plurality of fuse read / write units, wherein a power supply terminal of each fuse read / write unit is configured to receive a fuse read / write operating voltage signal, a control terminal of each fuse read / write unit is configured to receive a first fuse read control signal and a first fuse write control signal, and each fuse read / write unit is capable of reading data stored in a fuse trim bit according to the first fuse read control signal and writing data stored in the fuse trim bit according to the first fuse write control signal; The preset delay time length can ensure that the time when the power supply end of each fuse read / write unit in the power-on state receives the fuse read / write operating voltage signal is later than the start-up time of the logic control unit capable of issuing the fuse read first control signal and the fuse write first control signal; Wherein, the fuse power supply unit includes: a first power supply stabilization switch module, a first delay module and a power supply output module, the input end of the first power supply stabilization switch module is the input end of the fuse power supply unit, the output end of the first power supply stabilization switch module is connected to the input end of the first delay module, the output end of the first delay module is connected to the input end of the power supply output module, and the output end of the power supply output module is the output end of the fuse power supply unit; The first power supply stabilization switch module is used to turn on the first delay module when the voltage of the power supply reaches a preset power supply voltage; The first delay module is used to start the delay function when the first power supply stabilization switch module turns on the first delay module, and turn on the power output module when the preset delay time is reached; The power supply output module is used to generate a fuse read / write operating voltage signal and output the fuse read / write operating voltage signal when the fuse read / write unit array is in a power-on state and the first delay module turns on the power supply output module; The first power supply stabilization switch module includes: a first NOT gate and a first N-type switch tube, wherein the input end of the first NOT gate is the input end of the first power supply stabilization switch module, the output end of the first NOT gate is connected to the control end of the first N-type switch tube, the drain end of the first N-type switch tube is the output end of the first power supply stabilization switch module, and the source end of the first N-type switch tube is connected to the signal ground; Among them, the first delay module includes: a first resistor and a first capacitor, one end of the first resistor is connected to the power supply, the other end of the first resistor is connected to one end of the first capacitor, the other end of the first capacitor is connected to the signal ground, and the other end of the first resistor is also connected to the output end of the first power supply stabilization switch module.

2. The trimming circuit with a power-on burnout protection mechanism according to claim 1, wherein: The power supply output module includes: a first P-type switch tube, a second P-type switch tube, a third P-type switch tube, a fourth P-type switch tube, a second N-type switch tube, a third N-type switch tube, a fourth N-type switch tube, a second resistor and a third resistor; The control end of the first P-type switch is connected to the first delay module, the source end of the first P-type switch is connected to the power supply, the drain end of the first P-type switch is connected to one end of the third resistor, and the other end of the third resistor is connected to the signal ground; One end of the second resistor is connected to the power supply, the other end of the second resistor is connected to the control end of the fourth P-type switch tube, the source end of the fourth P-type switch tube is connected to the power supply, and the drain end of the fourth P-type switch tube is connected to the control end of the third P-type switch tube; The control terminal of the second P-type switch tube is connected to the control terminal of the first P-type switch tube, the source terminal of the second P-type switch tube is connected to the power supply, and the drain terminal of the second P-type switch tube is connected to the control terminal of the third P-type switch tube; The source terminal of the third P-type switch tube is connected to the power supply, and the drain terminal of the third P-type switch tube is the output terminal of the power output module; The control terminal of the second N-type switch tube is connected to the control terminal of the fourth P-type switch tube, the drain terminal of the second N-type switch tube is connected to the control terminal of the third P-type switch tube, and the source terminal of the second N-type switch tube is connected to the signal ground; The control terminal of the third N-type switch tube is connected to the drain terminal of the first P-type switch tube, the drain terminal of the third N-type switch tube is the output terminal of the power output module, and the source terminal of the third N-type switch tube is connected to the signal ground; The control terminal of the fourth N-type switch is connected to the drain terminal of the first P-type switch, the drain terminal of the fourth N-type switch is connected to the control terminal of the second N-type switch, and the source terminal of the fourth N-type switch is connected to the signal ground.

3. The trimming circuit with a power-on burnout protection mechanism according to claim 1, wherein: The fuse power supply unit is further configured to output a fuse read operating voltage signal according to a second fuse read control signal and a fuse write operating voltage signal according to a second fuse write control signal when the fuse read / write unit array is in a normal working state. The fuse power supply unit includes: a second power supply stabilization switch module, a second delay module, a read power supply output module and a write power supply output module, the input end of the second power supply stabilization switch module is the input end of the fuse power supply unit, the output end of the second power supply stabilization switch module is connected to the input end of the second delay module, the output end of the second delay module is respectively connected to the input end of the read power supply output module and the input end of the write power supply output module, and the output end of the read power supply output module and the output end of the write power supply output module are both the output end of the fuse power supply unit; The second power supply stabilization switch module is used to turn on the second delay module when the voltage of the power supply reaches a preset power supply voltage; The second delay module is used to start the delay function when the second power supply stabilization switch module turns on the second delay module, and turn on the reading power output module or the writing power output module when the preset delay time is reached; The read power supply output module is configured to generate a fuse read operating voltage signal and output the fuse read operating voltage signal when the second delay module turns on the read power supply output module, the fuse read / write unit array is in a normal working state, and receives a fuse read second control signal; The write power supply output module is configured to generate a fuse write operating voltage signal and output the fuse write operating voltage signal when the second delay module turns on the write power supply output module, the fuse read / write unit array is in a normal working state, and receives a fuse write second control signal; The output current of the read power supply output module is smaller than the output current of the write power supply output module.

4. The trimming circuit with a power-on burnout protection mechanism according to claim 3, wherein: The second power supply stabilization switch module includes: a second NOT gate and a fifth N-type switch tube, the input end of the second NOT gate is the input end of the second power supply stabilization switch module, the output end of the second NOT gate is connected to the control end of the fifth N-type switch tube, the drain end of the fifth N-type switch tube is the output end of the second power supply stabilization switch module, and the source end of the fifth N-type switch tube is connected to the signal ground.

5. The trimming circuit with a power-on burnout protection mechanism according to claim 3, wherein: The second delay module includes: a fourth resistor and a second capacitor, one end of the fourth resistor is connected to the power supply, the other end of the fourth resistor is connected to one end of the second capacitor, the other end of the second capacitor is connected to the signal ground, and the other end of the fourth resistor is also connected to the output end of the second power supply stabilization switch module.

6. The trimming circuit with a power-on burnout protection mechanism according to claim 3, wherein: The reading power supply output module includes: a fifth resistor, a sixth resistor, a fifth P-type switch tube, a sixth P-type switch tube, a seventh P-type switch tube, an eighth P-type switch tube, a sixth N-type switch tube, a seventh N-type switch tube and an eighth N-type switch tube; The control terminal of the fifth P-type switch is connected to the second delay module, the source terminal of the fifth P-type switch is connected to the power supply, the drain terminal of the fifth P-type switch is connected to one end of the sixth resistor, and the other end of the sixth resistor is connected to the signal ground; One end of the fifth resistor is the fuse read second control signal input end, the other end of the fifth resistor is connected to the control end of the eighth P-type switch tube, the source end of the eighth P-type switch tube is connected to the power supply, and the drain end of the eighth P-type switch tube is connected to the control end of the seventh P-type switch tube; The control terminal of the sixth P-type switch tube is connected to the control terminal of the fifth P-type switch tube, the source terminal of the sixth P-type switch tube is connected to the power supply, and the drain terminal of the sixth P-type switch tube is connected to the control terminal of the seventh P-type switch tube; The source terminal of the seventh P-type switch tube is connected to the power supply, and the drain terminal of the seventh P-type switch tube is the output terminal of the reading power supply output module; The control terminal of the sixth N-type switch is connected to the control terminal of the eighth P-type switch, the drain terminal of the sixth N-type switch is connected to the control terminal of the seventh P-type switch, and the source terminal of the sixth N-type switch is connected to the signal ground; The control terminal of the seventh N-type switch tube is connected to the drain terminal of the fifth P-type switch tube, the drain terminal of the seventh N-type switch tube is the output terminal of the reading power output module, and the source terminal of the seventh N-type switch tube is connected to the signal ground; The control terminal of the eighth N-type switch tube is connected to the drain terminal of the fifth P-type switch tube, the drain terminal of the eighth N-type switch tube is connected to the control terminal of the sixth N-type switch tube, and the source terminal of the eighth N-type switch tube is connected to the signal ground.

7. The trimming circuit with a power-on burnout protection mechanism according to claim 3, wherein: The write power supply output module includes: a sixth resistor, a seventh resistor, a fifth P-type switch tube, a ninth P-type switch tube, a tenth P-type switch tube, an eleventh P-type switch tube, a seventh N-type switch tube, a ninth N-type switch tube and a tenth N-type switch tube. The control terminal of the fifth P-type switch is connected to the second delay module, the source terminal of the fifth P-type switch is connected to the power supply, the drain terminal of the fifth P-type switch is connected to one end of the sixth resistor, and the other end of the sixth resistor is connected to the signal ground; One end of the seventh resistor is the fuse write second control signal input end, the other end of the seventh resistor is connected to the control end of the ninth P-type switch tube, the source end of the ninth P-type switch tube is connected to the power supply, and the drain end of the ninth P-type switch tube is connected to the control end of the eleventh P-type switch tube; The control terminal of the tenth P-type switch tube is connected to the control terminal of the fifth P-type switch tube, the source terminal of the tenth P-type switch tube is connected to the power supply, and the drain terminal of the tenth P-type switch tube is connected to the control terminal of the eleventh P-type switch tube; The source terminal of the eleventh P-type switch tube is connected to the power supply, and the drain terminal of the eleventh P-type switch tube is the output terminal of the write power output module; The control terminal of the seventh N-type switch tube is connected to the drain terminal of the fifth P-type switch tube, the drain terminal of the seventh N-type switch tube is the output terminal of the write power output module, and the source terminal of the seventh N-type switch tube is connected to the signal ground; The control terminal of the ninth N-type switch is connected to the drain terminal of the fifth P-type switch, the drain terminal of the ninth N-type switch is connected to the control terminal of the ninth P-type switch, and the source terminal of the ninth N-type switch is connected to the signal ground; The control end of the tenth N-type switch tube is connected to the control end of the ninth P-type switch tube, the drain end of the tenth N-type switch tube is connected to the control end of the eleventh P-type switch tube, and the source end of the tenth N-type switch tube is connected to the signal ground.

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