Semiconductor device and preparation method thereof
By using the LPCVD process to form a dense gate oxide layer in semiconductor chip manufacturing, the problems of channel surface state changes and threshold voltage fluctuations caused by wet etching are solved, and the electrical performance of the device is improved.
Patent Information
- Application Number
- CN202510656649.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-20
- Publication Date
- 2025-09-02
AI Technical Summary
In semiconductor chip manufacturing, unstable amount of wet etching liquid leads to changes in the channel surface state of the low-voltage device region and abnormal fluctuations in the threshold voltage of the low-voltage MOS device, affecting the electrical performance of the device.
The LPCVD process is used to form a dense second gate oxide layer in the high-voltage and low-voltage device regions, and then the second gate oxide layer and the first gate oxide layer in the low-voltage device region are removed by wet etching, and then a third gate oxide layer is formed to avoid damage to the substrate by wet etching and doped ions precipitation.
Effectively prevents the damage of wet etching to the substrate in the low-voltage device area, suppresses the precipitation of doped ions, prevents threshold voltage fluctuations, and improves the electrical performance of the device.
Smart Images
Figure CN120583709A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor device and a method for preparing the same. Background Art
[0002] Semiconductor chips are developing towards higher component density, faster computing speeds, and greater data storage capacity. However, in semiconductor chip manufacturing, different electrical requirements necessitate different gate oxide thickness requirements for different devices.
[0003] Currently, a common well is commonly used to fabricate different devices (device structures with different gate oxide thicknesses). This common well fabrication method can save some masks (reticles), significantly reducing costs. However, in the conventional fabrication process of semiconductor structures with two different gate oxide thicknesses, after forming the first gate oxide layer, a wet etching process is typically required to remove the first gate oxide layer in the low-voltage device region. This process, due to the unstable amount of wet etching solution, can cause a certain amount of silicon substrate loss in the low-voltage device region, altering the channel surface state. Furthermore, N-type ions (such as phosphorus ions) precipitate from the substrate (well region) in the low-voltage device region. These precipitated N-type ions react with the wet etching solution, causing changes in the charge in the depletion layer. This ultimately affects the threshold voltage of the MOS device in the low-voltage device region, leading to abnormal threshold voltage fluctuations in the MOS device. Summary of the Invention
[0004] The present application provides a semiconductor device and a method for preparing the same, which can solve at least one of the following problems: changes in the channel surface state of the low-voltage device area caused by unstable wet etching solution volume, abnormal fluctuations in the threshold voltage of the low-voltage MOS device, and the like.
[0005] In one aspect, an embodiment of the present application provides a method for manufacturing a semiconductor device, comprising:
[0006] Providing a substrate, wherein the substrate comprises a high-voltage device region and a low-voltage device region;
[0007] Simultaneously forming a first well region in the substrate of the high-voltage device region and a second well region in the substrate of the low-voltage device region by ion implantation;
[0008] forming a first gate oxide layer by a thermal oxidation process, wherein the first gate oxide layer covers the substrate of the high-voltage device area and the substrate of the low-voltage device area;
[0009] forming a second gate oxide layer by using an LPCVD process, wherein the second gate oxide layer covers the first gate oxide layer in the high-voltage device region and the low-voltage device region;
[0010] Removing the second gate oxide layer and the first gate oxide layer in the low-voltage device area through a wet etching process;
[0011] forming a third gate oxide layer by a thermal oxidation process, wherein the third gate oxide layer covers the second gate oxide layer in the high-voltage device area and the substrate in the low-voltage device area;
[0012] A polysilicon material layer is formed, where the polysilicon material layer covers the third gate oxide layer in the high-voltage device region and the third gate oxide layer in the low-voltage device region.
[0013] Optionally, in the preparation method of the semiconductor device, in the process of forming the second gate oxide layer using the LPCVD process, the reaction gas includes at least: silicon source gas and oxygen source gas; the process temperature is 700°C to 900°C; and the process time is 30min to 120min.
[0014] Optionally, in the method for preparing the semiconductor device, the thickness of the second gate oxide layer is 60 angstroms to 65 angstroms.
[0015] Optionally, in the method for preparing the semiconductor device, the chemical solution used in the wet etching process includes at least ammonia water and hydrofluoric acid.
[0016] Optionally, in the method for preparing the semiconductor device, during the process of forming the first gate oxide layer by a thermal oxidation process, the process temperature is 800° C. to 900° C., and the flow rate of the introduced oxygen is 1 slm to 20 slm.
[0017] Optionally, in the method for preparing the semiconductor device, during the process of forming the third gate oxide layer by a thermal oxidation process, the process temperature is 800° C. to 900° C., and the flow rate of the introduced oxygen is 1 slm to 20 slm.
[0018] Optionally, in the method for preparing the semiconductor device, the thickness of the first gate oxide layer is 40 angstroms to 50 angstroms; the thickness of the third gate oxide layer is 80 angstroms to 90 angstroms.
[0019] Optionally, in the method for preparing the semiconductor device, after forming the polysilicon material layer, the method for preparing the semiconductor device further comprises:
[0020] Part of the polysilicon material layer, part of the third gate oxide layer, part of the second gate oxide layer, and part of the first gate oxide layer in the high-voltage device area are etched to the substrate surface to form a high-voltage gate structure, and part of the polysilicon material layer and part of the third gate oxide layer in the low-voltage device area are etched to the substrate surface to form a low-voltage gate structure.
[0021] Optionally, in the method for preparing the semiconductor device, an N-type doped first well region is formed in the substrate of the high-voltage device region and an N-type doped second well region is formed in the substrate of the low-voltage device region by N-type ion implantation.
[0022] On the other hand, an embodiment of the present application further provides a semiconductor device, including:
[0023] A substrate comprising a high-voltage device region and a low-voltage device region;
[0024] a first well region and a second well region, wherein the first well region is located in the substrate of the high-voltage device region, and the second well region is located in the substrate of the low-voltage device region;
[0025] a first gate oxide layer, the first gate oxide layer covering the substrate of the high-voltage device region, the first gate oxide layer being prepared by a thermal oxidation process;
[0026] a second gate oxide layer, the second gate oxide layer covering the first gate oxide layer of the high-voltage device region, the second gate oxide layer being prepared by an LPCVD process;
[0027] a third gate oxide layer, the third gate oxide layer covering the second gate oxide layer in the high-voltage device area and the substrate covering the low-voltage device area, the third gate oxide layer being prepared by a thermal oxidation process;
[0028] A polysilicon material layer covers the third gate oxide layer of the high-voltage device region and the third gate oxide layer of the low-voltage device region.
[0029] The technical solution of this application has at least the following advantages:
[0030] The present application provides a semiconductor device and a preparation method thereof, wherein in the preparation method, a first gate oxide layer is first formed on a substrate in a high-voltage device region and a low-voltage device region, and then a second gate oxide layer is formed by an LPCVD process, and then the second gate oxide layer and the first gate oxide layer in the low-voltage device region are removed by wet etching, and then a third gate oxide layer is formed on the high-voltage device region and the low-voltage device region. At this time, the first to third gate oxide layers constitute the gate oxide structure of the high-voltage device region, and the third gate oxide layer serves as the gate oxide structure of the low-voltage device region. The present application forms a dense second gate oxide layer by an LPCVD process before removing the second gate oxide layer and the first gate oxide layer in the low-voltage device region by wet etching. The gate oxide layer, the dense second gate oxide layer and the first gate oxide layer can prevent the wet solution from mistakenly etching the substrate during wet over-etching, thereby causing a change in the channel surface state. It can also prevent the dopant ions in the substrate from being precipitated and reacting with the wet solution, resulting in a change in the charge of the depletion layer, and ultimately affecting the threshold voltage of the MOS device in the low-voltage device area. In other words, the combination of the dense second gate oxide layer and the first gate oxide layer can not only effectively prevent the damage to the substrate in the low-voltage device area caused by wet etching, but also inhibit the precipitation of dopant ions in the substrate, so that the threshold voltage of the MOS device in the low-voltage device area will not fluctuate abnormally, thereby improving the electrical performance of the device. BRIEF DESCRIPTION OF THE DRAWINGS
[0031] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the specific implementation methods or the description of the prior art. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.
[0032] Figure 1 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;
[0033] Figure 2-Figure 8 Schematic diagram of a semiconductor structure in each process step of manufacturing a semiconductor device according to an embodiment of the present invention;
[0034] The description of the accompanying drawings is as follows:
[0035] 10 - substrate, 11 - shallow trench isolation structure, 21 - first well region, 22 - second well region, 30 - first gate oxide layer, 40 - second gate oxide layer, 50 - third gate oxide layer, 60 - polysilicon material layer. DETAILED DESCRIPTION
[0036] The following is a clear and complete description of the technical solutions in this application in conjunction with the accompanying drawings. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of this application.
[0037] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate the description of this application and simplify the description. They do not indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0038] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to internal connections between two components; they can refer to wireless connections or wired connections. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.
[0039] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.
[0040] The present invention provides a method for preparing a semiconductor device. Figure 1 , Figure 1 1 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention, wherein the method for manufacturing a semiconductor device comprises:
[0041] First, perform step S1: refer to Figure 2 , Figure 2 This is a schematic diagram of a semiconductor structure after forming a first well region and a second well region according to an embodiment of the present application. A substrate 10 is provided, comprising a high-voltage device region and a low-voltage device region. A shallow trench isolation structure 11 is formed in the substrate 10 to isolate the high-voltage device region from the low-voltage device region.
[0042] Then, step S2 is performed: a first well region 21 is formed in the substrate 10 of the high voltage device region and a second well region 22 is formed in the substrate 10 of the low voltage device region simultaneously by ion implantation of a common well.
[0043] In this embodiment, the high-voltage device region and the low-voltage device region are both PMOS devices. Preferably, an N-type doped first well region 21 is formed in the substrate 10 of the high-voltage device region, and an N-type doped second well region 22 is formed in the substrate 10 of the low-voltage device region by N-type ion implantation.
[0044] In this embodiment, phosphorus (P) ion implantation is performed to simultaneously form an N-type doped first well region 21 in the substrate 10 of the high voltage device region and an N-type doped second well region 22 in the substrate 10 of the low voltage device region.
[0045] Next, execute step S3: refer to Figure 3 , Figure 3 This is a schematic diagram of the semiconductor structure after the first gate oxide layer is formed in an embodiment of the present application. The first gate oxide layer 30 is formed by a thermal oxidation process. The first gate oxide layer 30 covers the substrate 10 of the high-voltage device area and the substrate 10 of the low-voltage device area.
[0046] Preferably, in the process of forming the first gate oxide layer 30 by adopting the thermal oxidation process, the process temperature is 800° C. to 900° C., and the flow rate of the introduced oxygen is 1 slm to 20 slm.
[0047] Preferably, the thickness of the first gate oxide layer 30 is 40 angstroms to 50 angstroms.
[0048] Further, step S4 is performed: refer to Figure 4 , Figure 4 This is a schematic diagram of the semiconductor structure after the second gate oxide layer is formed in an embodiment of the present application. The second gate oxide layer 40 is formed by the LPCVD process, and the second gate oxide layer 40 covers the first gate oxide layer 30 of the high-voltage device area and the low-voltage device area.
[0049] Specifically, in the process of forming the second gate oxide layer by using the LPCVD process, the reaction gas includes at least: silicon source gas and oxygen source gas; the process temperature is 700° C. to 900° C.; and the process time is 30 min to 120 min.
[0050] Preferably, the thickness of the second gate oxide layer is 60 angstroms to 65 angstroms.
[0051] Next, execute step S5: refer to Figure 5 , Figure 5This is a schematic diagram of the semiconductor structure after the second gate oxide layer and the first gate oxide layer of the low-voltage device area are removed according to an embodiment of the present application. The second gate oxide layer 40 and the first gate oxide layer 30 of the low-voltage device area are removed by a wet etching process.
[0052] Wherein, the chemical solution used in the wet etching process includes at least ammonia water and hydrofluoric acid.
[0053] In this embodiment, the liquid used in the wet etching process is hydrofluoric acid and sacrificial ammonium ions (NH4 + ) mixed solution, the subsequent main need is to prevent the doping ions (phosphorus ions) in the substrate of the low-voltage device area from precipitating and reacting with the hydrofluoric acid in the wet process solution.
[0054] Further, step S6 is performed: refer to Figure 6 , Figure 6 This is a schematic diagram of the semiconductor structure after the third gate oxide layer is formed in an embodiment of the present application. The third gate oxide layer 50 is formed by a thermal oxidation process. The third gate oxide layer 50 covers the second gate oxide layer 40 of the high-voltage device area and the substrate 10 covering the low-voltage device area.
[0055] Preferably, in the process of forming the third gate oxide layer 50 by the thermal oxidation process, the process temperature is 800° C. to 900° C., and the flow rate of the introduced oxygen is 1 slm to 20 slm.
[0056] Finally, execute step S7: Figure 7 , Figure 7 This is a schematic diagram of the semiconductor structure after forming a polysilicon material layer in an embodiment of the present application, forming a polysilicon material layer 60, which covers the third gate oxide layer 50 of the high-voltage device area and the third gate oxide layer 50 of the low-voltage device area.
[0057] Preferably, the thickness of the third gate oxide layer 50 is 80 angstroms to 90 angstroms.
[0058] Further, after forming the polysilicon material layer, referring to Figure 8 , Figure 8 It is a schematic diagram of the semiconductor structure after the high-voltage gate structure and the low-voltage gate structure are formed in an embodiment of the present application. The method for preparing the semiconductor device also includes: etching part of the polysilicon material layer 60, part of the third gate oxide layer 50, part of the second gate oxide layer 40, and part of the first gate oxide layer 30 in the high-voltage device area to the surface of the substrate 10 to form a high-voltage gate structure, and etching part of the polysilicon material layer 60 and part of the third gate oxide layer 50 in the low-voltage device area to the surface of the substrate 10 to form a low-voltage gate structure.
[0059] In the present application, a dense second gate oxide layer is formed by using an LPCVD process before wet etching to remove the second gate oxide layer and the first gate oxide layer in the low-voltage device area. The combination of the dense second gate oxide layer and the first gate oxide layer can avoid the wet solution from mistakenly etching the substrate of the low-voltage device area during wet over-etching, thereby causing the channel surface state to change. It can also avoid the doped ions (phosphorus ions) in the substrate of the low-voltage device area from precipitating and reacting with the wet solution, causing the depletion layer charge to change, and ultimately affecting the threshold voltage of the MOS device in the low-voltage device area. In other words, the combination of the dense second gate oxide layer and the first gate oxide layer can effectively prevent the damage to the substrate of the low-voltage device area caused by wet etching, and can also inhibit the precipitation of doped ions (phosphorus ions) in the substrate, so that the threshold voltage of the MOS device in the low-voltage device area will not fluctuate abnormally, thereby improving the electrical performance of the device.
[0060] Based on the same inventive concept, the present application also provides a semiconductor device, referring to Figure 8 , the semiconductor device comprises:
[0061] A substrate 10, wherein the substrate 10 includes a high-voltage device region and a low-voltage device region;
[0062] a first well region 21 and a second well region 22 , wherein the first well region 21 is located in the substrate 10 of the high-voltage device region, and the second well region 22 is located in the substrate 10 of the low-voltage device region;
[0063] A first gate oxide layer 30, the first gate oxide layer 30 covers the substrate 10 of the high-voltage device region, and the first gate oxide layer 30 is prepared by a thermal oxidation process;
[0064] a second gate oxide layer 40, the second gate oxide layer 40 covering the first gate oxide layer 30 of the high-voltage device region, the second gate oxide layer 40 being prepared by an LPCVD process;
[0065] a third gate oxide layer 50, the third gate oxide layer 50 covering the second gate oxide layer 40 of the high-voltage device region and the substrate 10 of the low-voltage device region, the third gate oxide layer 50 being prepared by a thermal oxidation process;
[0066] A polysilicon material layer 60 covers the third gate oxide layer 50 in the high-voltage device region and the third gate oxide layer 50 in the low-voltage device region.
[0067] Obviously, the above embodiments are merely examples for clarity of explanation and are not intended to limit the implementation methods. Those skilled in the art will appreciate that other variations or modifications can be made based on the above description. It is not necessary and impossible to enumerate all implementation methods here. Obvious variations or modifications arising therefrom remain within the scope of protection of this application.
Claims
1. A method for preparing a semiconductor device, characterized in that: include: Providing a substrate, wherein the substrate comprises a high-voltage device region and a low-voltage device region; Simultaneously forming a first well region in the substrate of the high-voltage device region and a second well region in the substrate of the low-voltage device region by ion implantation; forming a first gate oxide layer by a thermal oxidation process, wherein the first gate oxide layer covers the substrate of the high-voltage device area and the substrate of the low-voltage device area; forming a second gate oxide layer by using an LPCVD process, wherein the second gate oxide layer covers the first gate oxide layer in the high-voltage device region and the low-voltage device region; Removing the second gate oxide layer and the first gate oxide layer in the low-voltage device area through a wet etching process; forming a third gate oxide layer by a thermal oxidation process, wherein the third gate oxide layer covers the second gate oxide layer in the high-voltage device area and the substrate in the low-voltage device area; A polysilicon material layer is formed, where the polysilicon material layer covers the third gate oxide layer in the high-voltage device region and the third gate oxide layer in the low-voltage device region.
2. The method for preparing a semiconductor device according to claim 1, wherein: In the process of forming the second gate oxide layer using the LPCVD process, the reaction gas includes at least: silicon source gas and oxygen source gas; the process temperature is 700° C. to 900° C.; and the process time is 30 minutes to 120 minutes.
3. The method for preparing a semiconductor device according to claim 1, wherein: The thickness of the second gate oxide layer is 60 angstroms to 65 angstroms.
4. The method for preparing a semiconductor device according to claim 1, wherein: The chemical solution used in the wet etching process includes at least ammonia water and hydrofluoric acid.
5. The method for preparing a semiconductor device according to claim 1, wherein: In the process of forming the first gate oxide layer by adopting the thermal oxidation process, the process temperature is 800° C. to 900° C., and the flow rate of the introduced oxygen is 1 slm to 20 slm.
6. The method for preparing a semiconductor device according to claim 1, wherein: In the process of forming the third gate oxide layer by adopting the thermal oxidation process, the process temperature is 800° C. to 900° C., and the flow rate of the introduced oxygen is 1 slm to 20 slm.
7. The method for preparing a semiconductor device according to claim 1, wherein: The thickness of the first gate oxide layer is 40 angstroms to 50 angstroms; the thickness of the third gate oxide layer is 80 angstroms to 90 angstroms.
8. The method for preparing a semiconductor device according to claim 1, wherein: After forming the polysilicon material layer, the method for preparing the semiconductor device further includes: Part of the polysilicon material layer, part of the third gate oxide layer, part of the second gate oxide layer, and part of the first gate oxide layer in the high-voltage device area are etched to the substrate surface to form a high-voltage gate structure, and part of the polysilicon material layer and part of the third gate oxide layer in the low-voltage device area are etched to the substrate surface to form a low-voltage gate structure.
9. The method for manufacturing a semiconductor device according to claim 1, wherein: By N-type ion implantation, an N-type doped first well region is formed in the substrate of the high-voltage device region, and an N-type doped second well region is formed in the substrate of the low-voltage device region.
10. A semiconductor device, characterized in that: include: A substrate comprising a high-voltage device region and a low-voltage device region; a first well region and a second well region, wherein the first well region is located in the substrate of the high-voltage device region, and the second well region is located in the substrate of the low-voltage device region; a first gate oxide layer, the first gate oxide layer covering the substrate of the high-voltage device region, the first gate oxide layer being prepared by a thermal oxidation process; a second gate oxide layer, the second gate oxide layer covering the first gate oxide layer of the high-voltage device region, the second gate oxide layer being prepared by an LPCVD process; a third gate oxide layer, the third gate oxide layer covering the second gate oxide layer in the high-voltage device area and the substrate covering the low-voltage device area, the third gate oxide layer being prepared by a thermal oxidation process; A polysilicon material layer covers the third gate oxide layer of the high-voltage device region and the third gate oxide layer of the low-voltage device region.