Gate structure and preparation method thereof

Abstract

The invention provides a gate structure and a preparation method thereof, and belongs to the field of semiconductors. The preparation method of the gate structure comprises the steps that a substrate is provided, STI is formed on the substrate, a gate oxide layer, a polycrystalline silicon layer and a first hard mask layer are sequentially deposited on an active region from the substrate to the upper portion, and the first hard mask layer is made of silicon oxide; depositing a second hard mask layer on the surface of the first hard mask layer, wherein the second hard mask layer is made of an SICN material; sequentially patterning the second hard mask layer, the first hard mask layer and the polycrystalline silicon layer to form a laminated structure; forming side walls on the two sides of the laminated structure; and sequentially removing the second hard mask layer and the first hard mask layer to form a gate structure. According to the invention, the SICN material layer is deposited on the surface of the silicon oxide, and the hard mask formed by the silicon oxide and the SICN material can block the influence of subsequent ion implantation on the polycrystalline silicon gate, so that the threshold voltage drift of the polycrystalline silicon gate is avoided.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a gate structure and a preparation method thereof. Background Art

[0002] In semiconductor manufacturing, the polysilicon gate structure has the function of controlling whether the device is turned off or on. Therefore, making the gate structure is one of the important steps in the semiconductor process. In the process of making the gate structure, there is only silicon dioxide as a hard mask layer on the surface of the polysilicon layer. After patterning to form the gate structure, it is necessary to perform a lightly doped drain (LDD) ion implantation process in the active area, and a heavily doped ion implantation process at the source and drain. During ion implantation, the ions will penetrate the silicon dioxide hard mask layer and enter the polysilicon gate structure in the logic area, thereby affecting the threshold voltage of the polysilicon gate structure and further affecting the logic device.

[0003] To address the aforementioned technical issues, the threshold voltage of the polysilicon gate structure can be maintained within a certain range by integrating the ion implantation process. However, since each step may introduce errors, the probability of errors in the threshold voltage of the gate structure increases.

[0004] It should be noted that the information disclosed in the background technology section of the invention is only intended to deepen the understanding of the general background technology of the invention, and should not be regarded as an admission or any form of implication that the information constitutes prior art already known to those skilled in the art. Summary of the Invention

[0005] The purpose of the present invention is to provide a gate structure and a preparation method thereof to solve the problem that during ion implantation, ions penetrate the silicon dioxide hard mask and enter the polysilicon gate structure, thereby affecting the threshold voltage of the polysilicon gate structure and further affecting the semiconductor device.

[0006] To solve the above technical problems, the present invention provides a method for preparing a gate structure, comprising:

[0007] Providing a substrate, on which an STI is formed to define active regions of NMOS and PMOS, wherein a gate oxide layer, a polysilicon layer, and a first hard mask layer are deposited in sequence from the substrate upwards in the active regions, wherein the material of the first hard mask layer is silicon oxide;

[0008] depositing a second hard mask layer on a surface of the first hard mask layer, wherein the material of the second hard mask layer is a SICN material;

[0009] patterning the second hard mask layer, the first hard mask layer, and the polysilicon layer in sequence to form a stacked structure;

[0010] forming side walls on both sides of the stacked structure;

[0011] The second hard mask layer and the first hard mask layer are removed in sequence to form a gate structure.

[0012] Preferably, the thickness of the second hard mask layer is in the range of

[0013] Preferably, the second hard mask layer is formed by chemical vapor deposition.

[0014] Preferably, dry etching is used to remove the second hard mask layer, and the dry etching gas includes NF3 and Ar.

[0015] Preferably, the flow rate of NF3 is 10-150 ml / min, and the flow rate of Ar is 10-300 ml / min.

[0016] Preferably, before depositing the first hard mask, the method further comprises performing n-type pre-doping on the polysilicon layer of the NMOS;

[0017] After forming the stacked structure, the method further includes lightly doping the active regions of the NMOS and PMOS to form LDD structures in the active regions.

[0018] Preferably, the method also includes forming a side wall structure on both sides of the stacked structure, the side wall structure including a first side wall and a second side wall, and before forming the LDD structure, the first side wall is formed on both sides of the stacked structure, and after forming the LDD structure, the second side wall is formed on both sides of the stacked structure, and the second side wall covers one side of the first side wall, and the first side wall and the second side wall both include a silicide material layer and a nitride material layer.

[0019] Preferably, in the step of forming the spacer structure, the height of the spacer structure is lower than the height of the second hard mask layer.

[0020] Preferably, the thickness of the first hard mask layer is

[0021] Based on the same inventive concept, the present invention further provides a gate structure, comprising:

[0022] Prepared by the preparation method described above.

[0023] Compared with the prior art, the gate structure preparation method of the present invention has the following advantages:

[0024] The present invention deposits a layer of SICN material on the surface of silicon oxide. Because SICN has shorter silicon-carbon (Si-C) bonds and longer silicon-nitrogen (Si-N) bonds, the combination of these bonds gives the SICN structure excellent compactness and stability. Furthermore, SICN exhibits excellent adhesion to silicon oxide. The hard mask formed by the silicon oxide and SICN materials can block the effects of subsequent ion implantation on the polysilicon gate, thereby preventing threshold voltage drift of the polysilicon gate. The silicon oxide material layer protects the polysilicon layer, preventing damage to the polysilicon layer during etching of the SICN material layer.

[0025] The gate structure provided by the present invention and the gate structure preparation method provided by the present invention belong to the same inventive concept. Therefore, the gate structure provided by the present invention has at least all the advantages of the gate structure preparation method provided by the present invention and can avoid the threshold voltage drift of the gate structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 is a flow chart of a method for preparing a gate structure in one embodiment of the present invention;

[0027] Figure 2 is a schematic diagram of forming a second hard mask layer on the surface of the first hard mask layer in one embodiment of the present invention;

[0028] Figure 3 is a schematic diagram of a patterned photoresist layer in one embodiment of the present invention;

[0029] Figure 4 is a schematic diagram of an embodiment of the present invention after etching the SHB layer;

[0030] Figure 5 is a schematic diagram of an embodiment of the present invention after etching the ODL layer;

[0031] Figure 6 is a schematic diagram of forming a stacked structure in one embodiment of the present invention;

[0032] Figure 7 is a schematic diagram of forming a sidewall structure on the sidewall of a stacked structure in one embodiment of the present invention;

[0033] Figure 8 is a schematic diagram after the second hard mask layer is removed according to one embodiment of the present invention;

[0034] Figure 9 is a schematic diagram after the first hard mask layer is removed according to one embodiment of the present invention;

[0035] In the figure,

[0036] 100-substrate; 200-silicon oxide layer;

[0037] 300-polysilicon layer; 310-stacked structure;

[0038] 320-side wall structure; 330-LDD structure;

[0039] 340-gate structure; 400-first hard mask layer;

[0040] 500-second hard mask layer; 600-ODL layer;

[0041] 700-SHB layer; 800-photoresist layer. DETAILED DESCRIPTION

[0042] In order to make the objects, advantages and features of the present invention clearer, the gate structure and its preparation method proposed in the present invention are further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. It should be understood that the drawings in the specification do not necessarily show the specific structure of the present invention in proportion, and the illustrative features used to illustrate certain principles of the present invention in the drawings in the specification will also be slightly simplified. The specific design features of the present invention disclosed herein, including, for example, specific dimensions, directions, positions and shapes, will be determined in part by the specific application and use environment. In addition, in the embodiments described below, the same figure mark is sometimes used in common between different drawings to represent the same part or a part with the same function, and its repeated description is omitted. In this specification, similar numbers and letters are used to represent similar items. Therefore, once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.

[0043] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "plurality" means at least two, such as two, three, etc., unless otherwise specifically defined.

[0044] In the description of this specification, the reference terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and features of different embodiments or examples without contradiction.

[0045] The core idea of ​​the present invention is to provide a gate structure preparation method that can prevent ions from penetrating the silicon dioxide hard mask into the polysilicon gate structure, avoid the threshold voltage shift of the polysilicon gate structure, and ensure the reliability of the logic device performance.

[0046] In order to realize the above idea, the present invention provides a method for preparing a gate structure. Figures 1 to 9 A specific embodiment of a gate structure manufacturing method disclosed herein includes the following steps S1 to S5.

[0047] Step S1: Provide a substrate 100, on which STI is formed to define active areas of NMOS and PMOS. The active areas are sequentially deposited with a gate oxide layer 200, a polysilicon layer 300 and a first hard mask layer 400 from the substrate upwards, and the material of the first hard mask layer 400 is silicon oxide.

[0048] Specifically, refer to Figure 1 and Figure 2 As shown, the material of the substrate 100 can be silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium, or it can be silicon on insulator or germanium on insulator; or it can be other materials, such as III-V compounds such as gallium arsenide. In this embodiment, the material of the substrate 100 is silicon. STI isolation is formed on the substrate 100 to define the active regions of NMOS and PMOS, so that gate structures can be fabricated in the active regions. The area where NMOS is located is defined as the NMOS area. The area where PMOS is located is defined as the PMOS area. A P well is formed on the substrate 100 in the NMOS area. An N well is formed on the substrate 100 in the PMOS area.

[0049] In the active areas of the NMOS region and the PMOS region, a gate oxide layer 200, a polysilicon layer 300 and a first hard mask layer 400 are sequentially deposited from the substrate 100 upwards. The material of the gate oxide layer 200 includes silicon dioxide, silicon oxynitride, high-K material, etc. In this embodiment, the material of the gate oxide layer 200 is silicon dioxide. For the polysilicon layer 300 in the NMOS region, since the polysilicon is doped with phosphorus (P) or arsenic (AS) in the subsequent process. Since the particles of P or AS are large, it is not easy to diffuse evenly, especially when the N+ doping depth does not match the thickness of the polysilicon layer 300, the doping will be too shallow, so that the doping concentration of the NMOS near the junction of the polysilicon layer 300 and the gate oxide layer 200 is not large enough, and polysilicon loss occurs, which affects the performance of the device. Therefore, the polysilicon layer 300 in the NMOS region is pre-doped using the NPO process. The pre-doped impurity is preferably P. In Figure 2 In the embodiment, the polysilicon layer 300 in the NMOS region has been pre-doped, while the polysilicon layer 300 in the PMOS region has not been pre-doped. The first hard mask layer 400 is made of silicon oxide, such as silicon dioxide or silicon oxynitride. In this embodiment, silicon dioxide is still selected as the material for the first hard mask layer. The first hard mask layer is used to relieve stress on the second hard mask layer and serves as an etch stop layer for subsequent etching of the second hard mask layer.

[0050] Step S2: depositing a second hard mask layer 500 on the surface of the first hard mask layer 400 , wherein the material of the second hard mask layer 500 is a SICN material.

[0051] Specifically, refer to Figure 1 and Figure 2 As shown, a second hard mask layer 500 is formed on the surface of the first hard mask layer 400, and the material of the second hard mask layer 500 is SICN material, that is, SICN material layer. The thickness range of the second hard mask layer 500 is That is, the thickness of the SICN material layer can be or The thickness of the first hard mask layer 400 is That is, the thickness of the silicon dioxide material layer can be or The SICN material layer can block ions from entering the polysilicon layer 300. A thicker SICN material layer can improve the ability to block ions from entering the polysilicon layer 300. However, an excessively thick SICN material layer can increase stress and make subsequent etching of the SICN material layer more difficult.

[0052] In this embodiment, a SICN material layer is formed by chemical vapor deposition. SICN is chosen as the hard mask because it has short silicon-carbon (Si-C) bonds and long silicon-nitrogen (Si-N) bonds. The combination of these bonds gives SICN excellent structural compactness and stability. Furthermore, SICN has excellent adhesion to silicon dioxide. The hard mask composed of silicon oxide and SICN can block the effects of subsequent ion implantation on the polysilicon gate, thereby preventing threshold voltage drift of the polysilicon gate.

[0053] Step S3 : patterning the second hard mask layer 500 , the first hard mask layer 400 and the polysilicon layer 300 to form a stacked structure 310 .

[0054] Specifically, refer to Figures 1 to 6 As shown, to improve the accuracy of pattern transfer during gate structure patterning, an anti-reflective coating is deposited on the second hard mask layer 500. For example, an ODL layer 600, an SHB layer 700, and a photoresist layer 800 are deposited sequentially on the surface of the second hard mask layer 500 from the substrate 100 upwards. The ODL layer 600 is made of an organic dielectric layer (Oxide Deposition Layer, ODL). The SHB layer 700 is a silicon-O-based hard mask intermediate layer (Si-O-Based Hard Mask, SHB).

[0055] Patterning the second hard mask layer 500 , the first hard mask layer 400 , and the polysilicon layer 300 to form a stacked structure 310 includes:

[0056] First, the pattern of the gate structure is transferred to the photoresist layer 800 by exposure and development, and the photoresist layer 800 is patterned to form a Figure 3 The photoresist pattern shown in FIG. The SHB layer 700 is dry-etched with the patterned photoresist layer 800 as a mask to form a Figure 4 The structure shown in FIG. Next, the ODL layer 600 is dry-etched using the etched SHB layer 700 as a mask. Then, etching is continued to pattern the ODL layer 600. Finally, the SHB layer 700 and the photoresist layer 800 on the surface of the ODL layer 600 are removed by dry etching to form the structure shown in FIG. Figure 5 The structure shown.

[0057] Finally, the second hard mask layer 500, the first hard mask layer 400, and the polysilicon layer 300 are sequentially etched using the patterned ODL layer 600 as a mask to form a stacked structure 310. The SICN material layer is etched using a dry etching method using the patterned ODL layer 600 as a mask. The dry etching gases include NF3 and Ar. The flow rate of NF3 is 10 to 150 ml / min, and the flow rate of Ar is 10 to 300 ml / min. Since the first hard mask layer only serves to relieve the stress of the SICN and serve as an etch stop layer for the SICN, it does not need to be too thick. Preferably, the thickness of the first hard mask layer is less than the thickness of the second hard mask layer. That is, the thickness of the silicon dioxide material layer is less than the thickness of the SICN material layer. After the etching of the SICN material layer is completed, the first hard mask layer 400 is dry-etched using the SICN material layer as a hard mask. Then, the polysilicon layer 300 is etched using the first hard mask layer 400 as a hard mask to form a stacked structure 310. Figure 6 The structure shown.

[0058] Step S4 : forming sidewall structures 320 on both sides of the stacked structure 310 .

[0059] Specifically, refer to Figure 1 and Figure 7 As shown, the method also includes forming sidewall structures 320 on both sides of the stacked structure 310. The sidewall structure 320 is a double-layer structure, including a first sidewall and a second sidewall. First, the first sidewall is formed on both sides of the stacked structure 310. Then, the active regions of NMOS and PMOS are lightly doped to form an LDD structure in the active regions. The impurity doped in NMOS is preferably P. The impurity doped in PMOS is preferably B. By forming a very thin lightly doped region in the active regions of NMOS and PMOS, the peak electric field strength near the active region is reduced, thereby weakening the hot carrier effect. Finally, a second sidewall is formed. The second sidewall covers one side of the first sidewall. The first sidewall and the second sidewall both include a silicide material layer and a nitride material layer. The silicide material layer is preferably a silicon dioxide material layer. The nitride material layer is preferably a silicon nitride material layer. The silicon dioxide material layer is arranged close to the stacked structure 310.

[0060] Furthermore, during the etching step for forming the sidewall spacer 320, the height of the sidewall spacer 320 is kept lower than the height of the SICN material layer. When the SICN material layer is subsequently removed, the high etching selectivity of the SICN material layer relative to the silicon dioxide and silicon nitride layers prevents the sidewall spacer 320 from being higher than the polysilicon layer 300 after the SICN material layer is etched. Ideally, the height of the sidewall spacer 320 should be equal to the height of the polysilicon layer.

[0061] Finally, after forming the spacer structure 320, the source and drain are formed on both sides of the stacked structure 310. Ion implantation is performed by performing N+ ion implantation in the NMOS region to form the source and drain of the NMOS. Ion implantation is performed by performing P+ ion implantation in the PMOS region to form the source and drain of the PMOS.

[0062] Step S5 : removing the second hard mask layer 500 and the first hard mask layer 400 in sequence to form a gate structure 340 .

[0063] Specifically, refer to Figure 1 、 Figures 7 to 9 As shown, dry etching is still used to remove the second hard mask layer. That is, NF3 and Ar mixed gas is used for etching to remove the SICN material layer on the top of the stacked structure 310 to form Figure 8 The structure shown. It should be noted that in the preceding process, the loss of silicon oxide on the substrate 100 should be minimized to avoid the silicon oxide on the substrate 100 being etched before the SICN material layer is etched, thereby causing damage to the substrate. When NF3 and Ar are used for etching, the etching selectivity of the etching gas to the SICN material layer is greater than that to the silicon dioxide material layer. After the SICN material layer is completely etched, only a portion of the silicon dioxide material layer is etched. Next, wet etching is used to remove the remaining silicon oxide on the polysilicon and the silicon oxide on the substrate 100, and the following is obtained: Figure 9 The gate structure 340 is shown. It should be noted that when removing the second hard mask layer, the second hard mask layer 500 can be removed simultaneously with the step of thinning the silicon nitride (SIN) sidewall in the stress memory technology (SMT) process to increase the process window, and then the first hard mask layer 400 can be removed.

[0064] In this embodiment, a layer of SICN material layer is deposited on the surface of the SiO2 material layer. Since SICN has a shorter silicon-carbon bond (Si-C) and a longer silicon-nitrogen bond (Si-N), the combination of the silicon-carbon bond (Si-C) and the silicon-nitrogen bond (Si-N) makes the SICN structure have good density and stability. In addition, SICN has good adhesion to silicon dioxide, avoiding the formation of a gap between the SICN material layer and the SiO2 material layer during the etching process. In the subsequent steps of forming the LDD structure 330 by the light doping process and forming the source and drain by the ion implantation process, ions can be prevented from penetrating the SiO2 material layer into the polysilicon layer 300, thereby avoiding the threshold voltage drift of the gate structure 340. By providing the SiO2 material layer, the SiO2 material layer can protect the polysilicon layer 300 and avoid damage to the polysilicon layer 300 when etching the SICN material layer.

[0065] To realize the above idea, this embodiment further discloses a gate structure, which is prepared using the above-mentioned preparation method.

[0066] The gate structure 340 provided in this embodiment and the gate structure preparation method provided in this embodiment belong to the same inventive concept. Therefore, the gate structure 340 provided in this embodiment has at least all the advantages of the gate structure preparation method provided in this embodiment and can avoid threshold voltage drift of the gate structure 340.

[0067] In summary, the above embodiments provide detailed descriptions of different configurations of gate structures and preparation methods thereof. Of course, the above description is only a description of preferred embodiments of the present invention, and is not any limitation to the scope of the present invention. The present invention includes but is not limited to the configurations listed in the above embodiments. Those skilled in the art can draw inferences based on the contents of the above embodiments. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosures shall fall within the scope of protection of the claims.

Claims

1. A method for preparing a gate structure, characterized in that: include: Providing a substrate, on which an STI is formed to define active regions of NMOS and PMOS, wherein a gate oxide layer, a polysilicon layer, and a first hard mask layer are deposited in sequence from the substrate upwards in the active regions, wherein the material of the first hard mask layer is silicon oxide; depositing a second hard mask layer on a surface of the first hard mask layer, wherein the material of the second hard mask layer is a SICN material; patterning the second hard mask layer, the first hard mask layer, and the polysilicon layer in sequence to form a stacked structure; forming sidewall structures on both sides of the stacked structure; The second hard mask layer and the first hard mask layer are removed in sequence to form a gate structure.

2. The method for preparing a gate structure according to claim 1, wherein: The thickness of the second hard mask layer is in the range of 3. The method for preparing a gate structure according to claim 1, wherein: A second hard mask layer is formed by chemical vapor deposition.

4. The method for preparing a gate structure according to claim 1, wherein: The second hard mask layer is removed by dry etching, and the dry etching gas includes NF3 and Ar.

5. The method for preparing a gate structure according to claim 4, wherein: The flow rate of NF3 is 10-150 ml / min, and the flow rate of Ar is 10-300 ml / min.

6. The method for preparing a gate structure according to claim 1, wherein: Before depositing the first hard mask, the method further includes performing n-type pre-doping on the polysilicon layer of the NMOS; After forming the stacked structure, the method further includes lightly doping the active regions of the NMOS and PMOS to form LDD structures in the active regions.

7. The method for preparing a gate structure according to claim 6, wherein: The method also includes forming a sidewall structure on both sides of the stacked structure, the sidewall structure including a first sidewall and a second sidewall. Before forming the LDD structure, the first sidewall is formed on both sides of the stacked structure. After forming the LDD structure, the second sidewall is formed on both sides of the stacked structure. The second sidewall covers one side of the first sidewall. Both the first sidewall and the second sidewall include a silicide material layer and a nitride material layer.

8. The method for preparing a gate structure according to claim 7, wherein: In the step of forming the spacer structure, the height of the spacer structure is lower than the height of the second hard mask layer.

9. The method for preparing a gate structure according to claim 1, wherein: The thickness of the first hard mask layer is 10. A gate structure, characterized in that: include: The method is described in any one of claims 1 to 9.

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