A method of manufacturing an integrated circuit

Abstract

A single integrated circuit including a memory region and a non-memory region is provided. The memory region includes a first conductive structure, a memory element disposed on the first conductive structure, and a first via disposed on the memory element. The non-memory region includes a second conductive structure and a second via disposed on the second conductive structure. The first conductive structure and the second conductive structure are formed by a first photolithography process including a first photomask, the first conductive structure serving as a first bottom electrode within the memory region. The first via and the second via are formed by a third photolithography process including a third photomask. The first photomask and the third photomask include the same pattern.

Description

Technical Field

[0001] This invention relates generally to a new process technology for embedded memory, and more particularly to an embedded memory integration technology that reduces photomask costs. Background Technology

[0002] Resistive random access memory (RRAM) is a type of non-volatile memory whose resistance can be switched to a low-resistance state (LRS) or a high-resistance state (HRS) by applying an appropriate voltage. This difference in resistance (the difference between LRS and HRS) allows for the storage of digital data "0" and "1".

[0003] RRAM is a general-purpose memory technology that can be used as both standalone and embedded memory. When used as embedded memory, additional photomasks are required to successfully integrate RRAM into an integrated circuit (IC). Current RRAM processes require 2-3 additional photomasks to achieve integration into the IC chip.

[0004] In semiconductor manufacturing, photomask costs account for a significant proportion of the total process cost, and this proportion increases with the advancement of the process node. Therefore, processes that can reduce the number of photomasks are particularly attractive. For non-volatile memories, this type of memory technology requires far fewer photomasks than existing embedded non-volatile memories (which are often based on embedded flash memory technology and require more than 10 additional photomasks), thus offering a significant advantage. Existing embedded RRAM process flows require two or more additional photomasks, where the first mask defines the RRAM bottom electrode (BE), and the second mask defines the formation location of the RRAM cells. Summary of the Invention

[0005] According to a first aspect of the present invention, a single integrated circuit is provided comprising a memory region and a non-memory region. The memory region includes a first conductive structure, a memory element disposed on the first conductive structure, and a first via disposed on the memory element. The non-memory region includes a second conductive structure and a second via disposed on the second conductive structure. The first conductive structure and the second conductive structure are formed by a first photolithography process including a first photomask, wherein the first conductive structure serves as a first bottom electrode within the memory region.

[0006] In some embodiments, the storage element includes: a dielectric layer disposed on the first bottom electrode; a capping layer disposed on the dielectric layer; and a top electrode disposed on the capping layer.

[0007] In some embodiments, the storage area further includes a stacked bottom electrode disposed on the first bottom electrode.

[0008] In some embodiments, the storage area further includes a first top metal layer disposed on the first through hole.

[0009] In some embodiments, the storage region further includes a first bottom metal layer. The first bottom electrode is disposed on the first bottom metal layer.

[0010] In some embodiments, the non-storage area further includes a second top metal layer disposed on the second via.

[0011] In some embodiments, the non-storage area further includes a second bottom metal layer. The second conductive structure is disposed on the second bottom metal layer.

[0012] In some embodiments, the first bottom metal layer and the second bottom metal layer are formed by a first metallization process.

[0013] In some embodiments, the first top metal layer and the second top metal layer are formed by a second metallization process.

[0014] In some embodiments, the second via does not surround the side surface of the second conductive structure.

[0015] In some embodiments, the second through-hole portion surrounds the side surface of the second conductive structure.

[0016] In some embodiments, the second through-hole completely surrounds the side surface of the second conductive structure.

[0017] In some embodiments, within the non-storage area, a plurality of the second conductive structures are disposed on a single second bottom metal layer.

[0018] In some implementations, within the storage area, only a single first bottom electrode is disposed on a single first bottom metal layer.

[0019] In some embodiments, the storage element is one of the following: resistive random access memory (RRAM); conductive bridged random access memory (CBRAM); magnetoresistive random access memory (MRAM); ferroelectric random access memory (FeRAM); and phase change random access memory (PCRAM).

[0020] In some embodiments, the first via and the second via are formed by a third photolithography process including a third photomask.

[0021] In some embodiments, the first photomask and the third photomask include the same pattern.

[0022] According to a second aspect of the present invention, a method for manufacturing an integrated circuit is provided, comprising: defining a memory region and a non-memory region on a semiconductor wafer; depositing a first interlayer dielectric layer on a first bottom metal layer in the memory region and a second bottom metal layer in the non-memory region; etching the first interlayer dielectric layer by means of a first photolithography process including a first photomask to form a first conductive structure in the memory region and a second conductive structure in the non-memory region, wherein the first conductive structure serves as a first bottom electrode in the memory region; depositing a memory layer stack in the memory region and the non-memory region; etching the memory layer stack by means of a second photolithography process including a second photomask to form a memory element in the memory region; depositing a second interlayer dielectric layer in the memory region and the non-memory region; and etching the second interlayer dielectric layer by means of a third photolithography process including a third photomask to form a first via in the memory region and a second via in the non-memory region. The first photomask and the third photomask include the same pattern.

[0023] In some embodiments, the storage stack includes: a dielectric layer; a capping layer; and a top electrode layer.

[0024] In some embodiments, the storage stack layer further includes a bottom electrode layer.

[0025] In some embodiments, the method further includes: forming a first bottom metal layer in the storage area and forming a second bottom metal layer in the non-storage area by a first metallization process.

[0026] In some embodiments, the method further includes forming a first top metal layer in the storage area and a second top metal layer in the non-storage area by a second metallization process. Attached Figure Description

[0027] The non-limiting embodiments of the present invention will be more readily understood by referring to the following figures.

[0028] Figure 1 A schematic diagram of an embedded RRAM manufactured using existing technology.

[0029] Figure 2 This is a schematic diagram of an embedded RRAM manufactured using a novel process according to an embodiment of the present invention.

[0030] Figures 3A to 3C This is a schematic diagram of the improved via and BE connection structure in the non-RRAM area of ​​the new embedded RRAM process according to an embodiment of the present invention.

[0031] Figure 4This is a top view schematic diagram of the BE in the non-RRAM area and the RRAMBE in the RRAM area in the new embedded RRAM process of the present invention.

[0032] Figures 5A to 5B This is a schematic diagram showing the thickness and material of each layer of the RRAM stack in the new embedded RRAM process of this invention.

[0033] Figures 6A to 6I This is a schematic diagram of a new process flow for embedded RRAM according to an embodiment of the present invention. Detailed Implementation

[0034] Figure 1 This example describes an embedded RRAM fabricated using an existing process that requires two or more additional photomasks. The wafer is divided into a non-RRAM region 110 and an RRAM region 120. In this case, the RRAM process begins at metal layer M. x+1 111 and 121. Subsequently, an interlayer dielectric (ILD) is deposited, followed by a first photolithography patterning process. In this first photolithography process, the RRAM bottom electrode (BE) 122 is patterned in the RRAM region 120 using a first photomask. After this, RRAM BE material is deposited on the wafer, followed by chemical mechanical polishing (CMP) and RRAM stack deposition. The RRAM stack includes a dielectric layer 123, a capping layer 124, and a top electrode 125. Furthermore, a hard mask layer 126 is further deposited on the RRAM stack. Subsequently, a second photolithography process is performed on the wafer to define the RRAM cells. The RRAM stack portions outside the RRAM region are subsequently removed. Note that the second photolithography process is performed using an RRAM photomask, which is the second photomask used in this process flow. Afterward, ILD layer deposition and CMP are performed again, and the top electrode 125 of the RRAM cell is connected to other circuitry via a standard CMOS back-to-line (BEOL) process flow. In this example, a through-hole V is used. x+1 127 and metal layer M x+2 128, wherein the through-hole V in RRAM region 120 x+1 Etching 127 penetrates the hard mask 126 and connects to the RRAM top electrode 125. Via V in the non-RRAM region 110. x+1 117 directly with metal layer M x+1 111 Connections. In summary, this existing RRAM process requires at least two different photomasks, one for RRAM bottom electrode patterning and one for RRAM cell patterning.

[0035] like Figure 1As shown, existing processes for embedded memory typically require two or more different photomasks, significantly increasing the implementation cost of embedded memory. Therefore, for embedded memory, there is an urgent need to reduce the number of different photomasks, thereby lowering photomask design costs.

[0036] Figure 2 This is a schematic diagram of an embedded RRAM manufactured using a novel process according to an embodiment of the present invention. According to an embodiment of the present invention, this novel process requires only the design of one additional photomask (“single-mask process”), thereby significantly reducing the design cost of the additional photomask and making the RRAM more competitive.

[0037] and Figure 1 Compared to embedded RRAM manufactured using existing processes, Figure 2 The embedded RRAM manufactured using the single-mask process shown differs in the connection method between the vias and the metal layer in the non-RRAM region 210. Specifically, the via V... x+1 217 is stacked with metal layer M x+1 211 is connected to the conductive structure 212 on top. Such conductive structures in non-RRAM areas have essentially the same structure as BE in RRAM areas, so although they do not function as bottom electrodes in non-memory areas, they are also referred to as BE in this specification for convenience. Figures 3A to 3C An improved via V in the non-RRAM region of a new embedded RRAM process according to an embodiment of the present invention. x+1 A schematic diagram of the connection structure with BE.

[0038] like Figure 3A As shown, in the non-RRAM region 310a, the via V x+1 317a is stacked on top of BE 312a. (As shown) Figure 3B As shown, in the non-RRAM region 310b, via V x+1 317b completely surrounds BE 312b. (For example...) Figure 3C As shown, in the non-RRAM region 310c, the via V x+1 317c partially surrounds BE 312c.

[0039] Figure 4 This is a top view schematic diagram of the BE in the non-RRAM area and the RRAMBE in the RRAM area in the new embedded RRAM process of the present invention.

[0040] like Figure 4 As shown, within the non-RRAM region 410, the isolation metal layer M x+1 Zero, one, or multiple BEs can be set on the top layer. For example, metal layer M x+1 Set 0 BEs on 411d, and set the metal layer M. x+1One BE is set on 411c, and 412c is set on metal layer M. x+1 Two BEs are set on 411b, and 412b is set on the metal layer M. x+1 Four BEs 412a are provided on 411a. Conversely, in the RRAM region 420, the isolation metal layer M... x+1 Only one RRAM BE is set on 421a. 422a.

[0041] Figures 5A to 5B This is a schematic diagram showing the thickness and material of each layer of the RRAM stack in the new embedded RRAM process of this invention.

[0042] Two types of RRAM stacks can be configured within RRAM area 520: (a) such as Figure 5A The RRAMs shown all have a BE material; and (b) Figure 5B The RRAM shown has two bottom electrodes. See also... Figure 5A The thickness of RRAM BE 522 can range from 5 nm to 500 nm, and the material of RRAM BE 522 can be a metal (Ti, Hf, Ta, Ru, Ir, Pt, etc.), a metal oxide (TiOx, TaOx, HfOx, etc.), a metal nitride (TiN, TaN, AlN, etc.), a metal nitride (TiON, TaON, AlON, etc.), or other suitable conductive materials. The thickness of the dielectric layer 523 can range from 0.1 nm to 50 nm, and the material of the dielectric layer 523 can be a dielectric (SiO2, Ta2O5, TiO2, ZrO2, HfO2, Al2O3, etc.) (including mixtures and / or combinations of such materials). The thickness of the capping layer 524 can range from 1 nm to 500 nm, and the material of the capping layer 524 can be a metal (Ti, Hf, Ta, Ru, Ir, Pt, etc.), a metal oxide (TiOx, TaOx, HfOx, etc.), a metal nitride (TiN, TaN, AlN, etc.), a metal oxynitride (TiON, TaON, AlON, etc.), or other suitable conductive materials. The thickness of the top electrode 525 can also range from 1 nm to 500 nm, and the material of the top electrode 525 can be a metal (Ti, Hf, Ta, Ru, Ir, Pt, etc.), a metal oxide (TiOx, TaOx, HfOx, etc.), a metal nitride (TiN, TaN, AlN, etc.), a metal oxynitride (TiON, TaON, AlON, etc.), or other suitable conductive materials. The material of the hard mask layer 526 can be SiN.

[0043] See Figure 5BA second RRAM BE 522a is deposited between the dielectric layer 523 and the first RRAM BE 522. The thickness of the second RRAM BE 522a can be 1 nm to 500 nm, and the material of the second RRAM BE 522a can be a metal (Ti, Hf, Ta, Ru, Ir, Pt, etc.), a metal oxide (TiOx, TaOx, HfOx, etc.), a metal nitride (TiN, TaN, AlN, etc.), a metal oxynitride (TiON, TaON, AlON, etc.), or other suitable conductive materials.

[0044] Figures 6A to 6I This is a schematic diagram of a new process flow for embedded RRAM according to an embodiment of the present invention. This new process flow may include the following steps.

[0045] like Figure 6A As shown, the wafer can be divided into a non-RRAM region 610 and an RRAM region 620. In this example, the RRAM process begins at metal layer M. x+1 .

[0046] Subsequently, in the non-RRAM region 610 and RRAM region 620, the interlayer medium (ILD) is deposited. Figure 6B ), and perform the first photolithography patterning process on BE ( Figure 6C It should be noted that in this first photolithographic patterning process, the same method as using through-hole V is employed. x+1 The same photomask is used to pattern the BEs in non-RRAM region 610 and RRAM region 620. In other words, the photolithographic patterning of BEs in non-RRAM region 610 and RRAM region 620 does not require the use of an additional photomask.

[0047] Following this, BE material is first deposited on the wafer. Figure 6D Then, chemical mechanical polishing (CMP) is performed. Figure 6E ), with metal layer M in non-RRAM region 610 and RRAM region 620 x+1 BE 622 was deposited at the top.

[0048] like Figure 6F As shown, an RRAM stack is subsequently deposited on the wafer. The RRAM stack includes a dielectric layer 623, a capping layer 624, and a top electrode 625. Furthermore, a hard mask layer 626 is further deposited on the RRAM stack.

[0049] like Figure 6G As shown, the wafer then undergoes a second photolithography process to define the RRAM cells. The RRAM stack within the non-RRAM region 610 will subsequently be removed. It should be noted that this second photolithography process is performed using an RRAM photomask, which is the only additional photomask used in this process flow.

[0050] like Figure 6H As shown, ILD layer deposition and CMP are performed again.

[0051] like Figure 6I As shown, the connection between the RRAM cell top electrode 625 and other circuits is completed using a standard CMOS BEOL process. In this example, a through-hole V is used. x+1 627 and metal layer M x+2 628, of which, through hole V x+1 Etching 627 penetrates the hard mask 626 and connects to the RRAM top electrode 625. In the non-RRAM region 610, via V... x+1 617 is directly connected to BE 612, and BE 612 is further connected to the metal layer M. x+1 611 connection.

[0052] According to an embodiment of the present invention, the metal layer M in the storage area x+1 Metal layer M in non-storage area x+1 (like Figure 2 M in x+1 221 and M x+1 211) can be formed simultaneously by the same metallization process, and the metal layer M in the storage area x+1 It can be used with the metal layer M in the non-storage area x+1 Connected.

[0053] According to an embodiment of the present invention, the metal layer M in the storage area x+2 Metal layer M in non-storage area x+2 (like Figure 2 M in x+2 228 and M x+2 218) can be formed simultaneously by the same metallization process, and the metal layer M in the storage area x+2 It can be used with the metal layer M in the non-storage area x+2 Connected.

[0054] In the process flow of the present invention described above, the metal layer M is used as a reference. x+1 and metal layer M x+2 Taking the setting of an RRAM storage array as an example, this embedded RRAM single-mask process uses a defined through-hole V... x+1 The same photomask defines the BE (BE) within the non-RRAM region 610 and the RRAM region 620. Figure 6C This makes the photomask defining the RRAM cell the only additional photomask required. Figure 6G After completing the RRAM cycle, the defined via V is used again. x+1 The photomask is formed in the non-RRAM region 610 with the metal layer M x+1Connected to metal layer M via BE x+2 And within RRAM region 620, the metal layer M x+2 Through-hole V connected to the top electrode of the RRAM x+1 ( Figure 6I ).

[0055] The process flow of the present invention can also be used in other back-end process (BEOL) memories, including but not limited to conductive bridged random access memory (CBRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FeRAM), and phase change random access memory (PCRAM).

[0056] The novel process technology of this invention has the following advantages: it reduces the number of additional photomasks required for embedded memory to just one, thereby significantly reducing mask costs. Compared with existing embedded memory integration methods, this technology can reduce photomask costs by more than 50%.

[0057] The above description of the illustrated embodiments of the present invention (including the description in the abstract) is not intended to be exhaustive or to precisely limit the invention to the various forms disclosed. While specific embodiments and examples of the invention have been described herein for illustrative purposes, as those skilled in the art should understand, various equivalent modifications can be made within the scope of this disclosure. Other embodiments may have layers arranged in a different order than those illustrated in the embodiments, or may increase or decrease the number of layers based on the illustrated embodiments.

[0058] Although the operations have been described above as multiple independent operations in order to best facilitate understanding of the invention, this order of description should not be construed as implying that the operations necessarily depend on a specific order. In particular, the operations need not necessarily be performed in the order described.

[0059] In this specification, the terms "above," "over," "below," "between," and "upper" are used to indicate the relative position of a material layer or component to other layers or components. For example, when a layer is described as being deposited "above," "over," or "below" another layer, it means that the layer may be in direct contact with the other layer or separated from it by one or more intermediate layers. Similarly, when a layer is described as being deposited "between" two layers, it means that the layer may be in direct contact with both layers or separated by one or more intermediate layers. Conversely, when a first layer is described as being "above" a second layer, it means that it is in direct contact with the second layer. Likewise, unless otherwise explicitly stated, when a component is described as being deposited "between" two layers, it means that the component may be in direct contact with each of the adjacent components or separated by one or more intermediate layers.

[0060] In this specification, the terms “example” and “illustration” are used to indicate that something is an example, instance, or illustration. Any aspect or design described herein as an “example” or “illustration” should not necessarily be construed as preferred or superior to other aspects or designs. Rather, the purpose of using the terms “example” or “illustration” is to state concepts in a specific manner. In this specification, the word “or” is intended to mean “or” in an inclusive sense, not in an exclusionary sense. That is, unless otherwise stated or clearly apparent from the context, “X includes A or B” is intended to mean any of the naturally inclusive permutations and combinations. In other words, “X includes A or B” is satisfied if: “X includes A”; “X includes B”; or X includes both A and B. Furthermore, any number of objects not specified in this specification and the appended claims may be generally understood to be “one or more” unless otherwise explicitly stated or clearly apparent from the context as a single item. Additionally, the terms “implementation” or “an embodiment” used herein are not intended to refer to the same embodiment unless described embodied therein. In this specification, the terms "first," "second," "third," "fourth," etc., are intended to be used as markers to distinguish different components and do not necessarily have the ordinal meaning represented by their numerical parts.

Claims

1. A method of fabricating an integrated circuit, characterized by, Comprising: defining a memory region and a non-memory region on a semiconductor wafer; depositing a first interlayer dielectric layer on a first bottom metal layer within the memory region and a second bottom metal layer within the non-memory region; forming a first conductive structure within the memory region and a second conductive structure within the non-memory region by etching the first interlayer dielectric layer with a first photolithography process including a first photomask, wherein the first conductive structure serves as a first bottom electrode within the memory region; depositing a memory stack layer within the memory region and the non-memory region; forming a memory element within the memory region by etching the memory stack layer with a second photolithography process including a second photomask; depositing a second interlayer dielectric layer within the memory region and the non-memory region; and forming a first via within the memory region and a second via within the non-memory region by etching the second interlayer dielectric layer with a third photolithography process including a third photomask, wherein the first photomask and the third photomask include the same pattern.

2. The method of claim 1, wherein, The memory stack layer comprises: a dielectric layer; a capping layer; and a top electrode layer.

3. The method of claim 2, wherein, The memory stack layer further comprises: a bottom electrode layer.

4. The method of claim 1, wherein, Further comprising: forming the first bottom metal layer within the memory region and the second bottom metal layer within the non-memory region by a first metallization process.

5. The method of claim 4, wherein, Further comprising: forming a first top metal layer within the memory region and a second top metal layer within the non-memory region by a second metallization process.

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