A tag chip and a method for configuring a digital baseband clock thereof

Abstract

The application provides a tag chip and a digital baseband clock configuration method thereof. When an uplink data transmission rate is obtained for the first time, a clock division coefficient corresponding to the uplink data transmission rate is calculated, and the clock division coefficient is stored in a non-volatile storage module. When an instruction signal corresponding to the uplink data transmission rate is received again, the clock division coefficient can be directly taken out from the non-volatile storage module for division, so that the process of recalculating the division coefficient each time is avoided, and the power consumption of the tag chip is reduced. The method can support the demand of multiple uplink data transmission rates, and the division coefficients corresponding to different uplink data transmission rates can be stored in the non-volatile storage module, so that the tag chip can be flexibly adapted to different communication environments and requirements.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of tag communication, in particular to a tag chip and a digital baseband clock configuration method thereof. BACKGROUND

[0002] In the traditional design of a tag chip, the strategy of dynamically selecting a suitable clock according to an instruction requirement or a preamble length is adopted for the configuration of a digital baseband clock. Since the digital baseband clock is not fixed but needs to be recalculated according to different instructions, this process brings an unignorable power consumption problem for a passive tag chip. The passive tag chip itself does not have an independent power supply, and its energy is completely dependent on the coupling of an external radio frequency field. Under the condition of limited energy, the recalculation of the clock division ratio needs to consume the limited energy resources of the chip each time. These calculation processes involve complex logical operations and register operations, which not only increase the instantaneous power consumption peak of the chip, but also may cause a significant increase in the overall energy consumption of the chip. In the application scenario of the passive tag, where the energy acquisition is unstable and limited, this additional power consumption overhead will directly shorten the effective working distance of the tag chip and reduce the reliability and stability of its communication. SUMMARY

[0003] The present application aims to provide a tag chip and a digital baseband clock configuration method thereof to at least partially overcome the defects of the prior art.

[0004] SUMMARY To achieve the above-mentioned purpose, the present application provides the following technical solutions:

[0005] In a first aspect, a digital baseband clock configuration method of a tag chip is provided, the tag chip comprising an analog front end, a digital baseband module and a non-volatile storage module; the method comprising the steps of:

[0006] In response to obtaining an instruction signal of a reader, the digital baseband module determines a current uplink data transmission rate according to the instruction signal, and queries whether there is a suitable clock division coefficient in the non-volatile storage module;

[0007] If there is a suitable clock division coefficient in the non-volatile storage module, the digital baseband module divides the main clock provided by the analog front end according to the clock division coefficient to obtain a division clock of the digital baseband module;

[0008] If the non-volatile storage module does not have a matching clock division factor, the digital baseband module calculates a clock division factor according to the frequency of the main clock provided by the analog front end and the uplink data transmission rate, and divides the main clock according to the clock division factor to obtain a divided clock of the digital baseband module; meanwhile, the clock division factor is written into the non-volatile storage module.

[0009] As an optional implementation of the method of the first aspect, the digital baseband module determines the current uplink data transmission rate according to the instruction signal, specifically including:

[0010] The digital baseband module parses the instruction signal to obtain the uplink data transmission rate carried by the instruction signal.

[0011] Specifically, the non-volatile storage module has clock division factors and corresponding uplink data transmission rates associatedly stored therein; the digital baseband module queries whether there is a matching clock division factor in the non-volatile storage module, specifically including:

[0012] The digital baseband module queries the non-volatile storage module according to the uplink data transmission rate, and if the query hits, determines a clock division factor matching the uplink data transmission rate.

[0013] As an optional implementation of the method of the first aspect, the digital baseband module determines the current uplink data transmission rate according to the instruction signal, specifically including:

[0014] The digital baseband module determines the uplink data transmission rate according to the length of the preamble in the data frame of the instruction signal.

[0015] Specifically, the non-volatile storage module has clock division factors and corresponding preamble lengths associatedly stored therein; the digital baseband module queries whether there is a matching clock division factor in the non-volatile storage module, specifically including:

[0016] The digital baseband module queries the non-volatile storage module according to the length of the preamble in the data frame of the instruction signal, and if the query hits, determines a clock division factor matching the uplink data transmission rate.

[0017] Secondly, a tag chip is provided, including: an analog front end, a digital baseband module and a non-volatile storage module.

[0018] The analog front end is configured to generate a main clock of the system.

[0019] The non-volatile storage module is configured to store clock division factors.

[0020] The digital baseband module is configured to, in response to an instruction signal of a reader, determine a current uplink data transmission rate according to the instruction signal, and query whether there is a clock division coefficient adapted to the uplink data transmission rate in the nonvolatile storage module; if there is a clock division coefficient adapted to the uplink data transmission rate in the nonvolatile storage module, the main clock provided by the analog front end is divided according to the clock division coefficient to obtain a divided clock of the digital baseband module; if there is no clock division coefficient adapted to the uplink data transmission rate in the nonvolatile storage module, a clock division coefficient is calculated according to the frequency of the main clock and the uplink data transmission rate, the main clock is divided according to the clock division coefficient to obtain a divided clock; and the clock division coefficient is written into the nonvolatile storage module.

[0021] As an optional implementation of the tag chip of the second aspect, the digital baseband module is specifically used for:

[0022] The instruction signal is parsed to obtain the uplink data transmission rate carried by the instruction signal.

[0023] Specifically, the nonvolatile storage module has clock division coefficients and corresponding uplink data transmission rates associated and stored therein; the digital baseband module is specifically used for:

[0024] The nonvolatile storage module is queried according to the uplink data transmission rate, and if the query hits, a clock division coefficient adapted to the uplink data transmission rate is determined.

[0025] As an optional implementation of the tag chip of the second aspect, the digital baseband module is specifically used for:

[0026] The uplink data transmission rate is determined according to the length of a preamble in a data frame of the instruction signal.

[0027] Specifically, the nonvolatile storage module has clock division coefficients and corresponding preamble lengths associated and stored therein; the digital baseband module is specifically used for:

[0028] The nonvolatile storage module is queried according to the length of a preamble in a data frame of the instruction signal, and if the query hits, a clock division coefficient adapted to the uplink data transmission rate is determined.

[0029] Advantages: Compared with the prior art, the digital baseband clock configuration method of the tag chip has the following advantages:

[0030] The method calculates the clock division coefficient corresponding to the uplink data transmission rate when the uplink data transmission rate is obtained for the first time, and stores the clock division coefficient in the non-volatile storage module. When the instruction signal corresponding to the uplink data transmission rate is received again, the clock division coefficient can be directly taken out from the non-volatile storage module for frequency division, avoiding the process of recalculating the frequency division coefficient each time, thereby reducing the power consumption of the tag chip.

[0031] Since the frequency division coefficient has been stored in the non-volatile storage module, the digital baseband module can be quickly taken out and applied, improving the response speed of the tag chip to the reader instruction.

[0032] The method can support the demand for multiple uplink data transmission rates, and can store the frequency division coefficients corresponding to different uplink data transmission rates in the non-volatile storage module, so that the tag chip can flexibly adapt to different communication environments and requirements.

[0033] The tag chip proposed by the application also has the above beneficial effects. BRIEF DESCRIPTION OF DRAWINGS

[0034] Figure 1 A flowchart of a digital baseband clock configuration method of a tag chip related to the embodiment.

[0035] Figure 2 A structural diagram of a tag chip related to the embodiment. DETAILED DESCRIPTION

[0036] The application will be further described below in conjunction with the drawings and specific embodiments. It should be understood that the application can be implemented in various forms, and some exemplary and non-limiting embodiments shown in the drawings and described below are not intended to limit the application to the specific embodiments described.

[0037] It should be understood that the technical features listed above for different embodiments can be combined with each other to form additional embodiments within the scope of the application, if technically feasible. In addition, the specific examples and embodiments described in the application are non-limiting, and corresponding modifications can be made to the structures, steps and sequences described above without departing from the scope of the application.

[0038] Reference should be made to Figure 1 , Figure 1 An exemplary flowchart of a digital baseband clock configuration method of a tag chip is given, and the tag chip as described above, as shown in Figure 2 , includes an analog front end, a digital baseband module and a non-volatile storage module. As shown in Figure 1 , the method includes steps S100 to S104.

[0039] S100: In response to the instruction signal of the reader, the digital baseband module determines the current uplink data transmission rate according to the instruction signal, and queries whether there is a matching clock division coefficient in the non-volatile storage module.

[0040] S102: If there is a matching clock division coefficient in the non-volatile storage module, the digital baseband module divides the main clock provided by the analog front end according to the clock division coefficient to obtain the division clock of the digital baseband module.

[0041] S104: If there is no matching clock division coefficient in the non-volatile storage module, the digital baseband module calculates the clock division coefficient according to the frequency of the main clock provided by the analog front end and the uplink data transmission rate, and divides the main clock according to the clock division coefficient to obtain the division clock of the digital baseband module; at the same time, the clock division coefficient is written into the non-volatile storage module.

[0042] In some embodiments, the uplink data transmission rate is directly specified by the instruction signal of the reader. After the digital baseband module acquires the instruction signal of the reader, the instruction signal is parsed to obtain the uplink data transmission rate carried by the instruction signal.

[0043] Correspondingly, the non-volatile storage module stores the clock division coefficient and the corresponding uplink data transmission rate in association. Taking an RFID tag chip as an example, if the main clock frequency of the RFID tag chip is 1280 kHz and the uplink data transmission rate requirement of the RFID tag chip is 640 kHz, then the clock division coefficient is 1 / 2, and the uplink data transmission rate 640 kHz is stored in association with the clock division coefficient 1 / 2 in the non-volatile storage module.

[0044] After the digital baseband module determines the current uplink data transmission rate according to the instruction signal, it can query in the non-volatile storage module according to the uplink data transmission rate. Still taking the uplink data transmission rate 640 kHz as an example, after the digital baseband module determines the current uplink data transmission rate to be 640 kHz according to the instruction signal, it queries all the stored data containing 640 kHz in the non-volatile storage module. If the query hits, the digital baseband module can directly take the clock division coefficient in the hit query result as the current applicable clock division coefficient of the digital baseband module, and then calculate the division clock of the digital baseband module according to the clock division coefficient and the main clock provided by the analog front end. If the query does not hit, the digital baseband module calculates the clock division coefficient according to the frequency of the main clock provided by the analog front end and the uplink data transmission rate, and divides the main clock according to the clock division coefficient to obtain the division clock of the digital baseband module; at the same time, the clock division coefficient is written into the non-volatile storage module.

[0045] In some embodiments, the uplink data transmission rate is determined according to the preamble length in the data frame of the instruction signal of the reader. The digital baseband module determines the uplink data transmission rate according to the length of the preamble in the data frame of the instruction signal after obtaining the instruction signal.

[0046] It should be noted that the correspondence between the preamble length and the uplink data transmission rate is usually pre-set. For example, the system can pre-define that a data length corresponds to how many system clock cycles, and the tag chip can know the preamble length by counting how many system clock cycles are used by the preamble of the data frame received from the reader, and then determine the uplink data transmission rate according to the pre-set relationship between the uplink data transmission rate and the preamble length.

[0047] Correspondingly, the non-volatile storage module described above stores the clock division coefficient and the corresponding preamble length in association. When the digital baseband module queries whether there is a suitable clock division coefficient in the non-volatile storage module, it can first determine the length of the preamble in the data frame of the instruction signal, and then query the non-volatile storage module according to the length of the preamble. If the query hits, the clock division coefficient in the hit query result can be directly taken as the currently applicable digital baseband module clock division coefficient. If the query does not hit, the digital baseband module calculates the clock division coefficient according to the frequency of the master clock provided by the analog front end and the uplink data transmission rate, and divides the master clock according to the clock division coefficient to obtain the frequency-division clock of the digital baseband module; at the same time, the clock division coefficient is written into the non-volatile storage module.

[0048] It should be noted that the tag chip described above can be an active chip or a passive chip, i.e., the method can be applied to the digital baseband clock configuration of an active chip, and also can be applied to the digital baseband clock configuration of a passive chip.

[0049] It should be noted that for two data frames with the same uplink data transmission rate, there can be a certain error when the digital baseband module calculates the lengths of the preambles of the two data frames, but the error will not be very large. Therefore, when querying the clock division coefficient according to the length of the preamble of the data frame, the difference between the length of the preamble of the current data frame and the length of the preamble stored in the non-volatile storage module can be calculated. If the difference value does not exceed the pre-set threshold, it can be determined that the uplink data transmission rates of the two data frames are consistent, at which time it is determined that the query hits, and the clock division coefficient in the hit query result is taken as the currently applicable digital baseband module clock division coefficient.

[0050] The method provided in the embodiment is a digital baseband clock configuration method of a tag chip. When an uplink data transmission rate is obtained for the first time, the method calculates a clock division coefficient corresponding to the uplink data transmission rate, and stores the clock division coefficient in a non-volatile storage module. When an instruction signal corresponding to the uplink data transmission rate is received again, the clock division coefficient can be directly obtained from the non-volatile storage module for division, avoiding the process of recalculating the division coefficient each time, thereby reducing the power consumption of the tag chip. Since the division coefficient has been stored in the non-volatile storage module, the digital baseband module can be quickly obtained and applied, improving the response speed of the tag chip to the reader instruction. The method can support the demand for multiple uplink data transmission rates, and can store the division coefficients corresponding to different uplink data transmission rates in the non-volatile storage module, so that the tag chip can flexibly adapt to different communication environments and requirements.

[0051] Corresponding to the above method, the embodiment also provides a tag chip which adopts the above method for digital baseband clock configuration. Please continue to refer to Figure 2 The tag chip comprises an analog front end, a digital baseband module, and a non-volatile storage module.

[0052] The analog front end is configured to generate a system master clock.

[0053] The non-volatile storage module is configured to store a clock division coefficient.

[0054] The digital baseband module is configured to, in response to obtaining an instruction signal of a reader, determine a current uplink data transmission rate according to the instruction signal, and query whether there is a matching clock division coefficient in the non-volatile storage module; if there is a matching clock division coefficient in the non-volatile storage module, divide the master clock provided by the analog front end according to the clock division coefficient to obtain a division clock of the digital baseband module; if there is no matching clock division coefficient in the non-volatile storage module, calculate a clock division coefficient according to the frequency of the master clock and the uplink data transmission rate, divide the master clock according to the clock division coefficient to obtain a division clock; and write the clock division coefficient into the non-volatile storage module.

[0055] In some embodiments, the uplink data transmission rate is directly specified by the instruction signal of the reader. After the digital baseband module obtains the instruction signal of the reader, the uplink data transmission rate carried by the instruction signal can be obtained by analyzing the instruction signal.

[0056] Correspondingly, the non-volatile storage module stores the clock division factor and the corresponding uplink data transmission rate in association. After the digital baseband module determines the current uplink data transmission rate according to the instruction signal, the digital baseband module can query the non-volatile storage module according to the uplink data transmission rate. If the query hits, the digital baseband module can directly take out the clock division factor in the query result of the hit as the currently applicable clock division factor of the digital baseband module, and then calculate the division clock of the digital baseband module according to the clock division factor and the master clock provided by the analog front end. If the query does not hit, the digital baseband module calculates the clock division factor according to the frequency of the master clock provided by the analog front end and the uplink data transmission rate, and divides the master clock according to the clock division factor to obtain the division clock of the digital baseband module; at the same time, the clock division factor is written into the non-volatile storage module.

[0057] In some embodiments, the uplink data transmission rate is determined according to the preamble length in the data frame of the instruction signal of the reader. The digital baseband module determines the uplink data transmission rate according to the length of the preamble in the data frame of the instruction signal after obtaining the instruction signal.

[0058] Correspondingly, the non-volatile storage module stores the clock division factor and the corresponding uplink data transmission rate in association. After the digital baseband module determines the current uplink data transmission rate according to the instruction signal, the digital baseband module can query the non-volatile storage module according to the uplink data transmission rate. If the query hits, the digital baseband module can directly take out the clock division factor in the query result of the hit as the currently applicable clock division factor of the digital baseband module, and then calculate the division clock of the digital baseband module according to the clock division factor and the master clock provided by the analog front end. If the query does not hit, the digital baseband module calculates the clock division factor according to the frequency of the master clock provided by the analog front end and the uplink data transmission rate, and divides the master clock according to the clock division factor to obtain the division clock of the digital baseband module; at the same time, the clock division factor is written into the non-volatile storage module.

[0059] It should be noted that for two data frames with the same uplink data transmission rate, there may be a certain error when the digital baseband module calculates the length of the preambles of the two data frames, but the error will not be large. Therefore, when querying the clock division factor according to the length of the preamble of the data frame, the difference between the length of the preamble of the current data frame and the length of the preamble stored in the non-volatile storage module can be calculated. If the difference value does not exceed the preset threshold, it can be determined that the uplink data transmission rates of the two data frames are consistent, at which time it is determined that the query hits, and the clock division factor in the query result of the hit is taken as the currently applicable clock division factor of the digital baseband module.

[0060] Any combination of the technical features in the above-described embodiments can be made, and for the sake of brevity, not all possible combinations are described, however, as long as the combination of the technical features does not exist in contradiction, it shall be considered within the scope of the present disclosure.

[0061] The above-described embodiments only express several implementation manners of the present application, and the description is relatively specific and detailed, but it shall not be understood as a limitation on the patent scope of the present application. It shall be pointed out that, for ordinary skilled persons in the art, several modifications and improvements can be made without departing from the concept of the present application, and these shall be within the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the appended claims.

Claims

1. A method for configuring a digital baseband clock for a tag chip, characterized in that, The tag chip comprises an analog front end, a digital baseband module and a non-volatile storage module; the method comprises the steps of: In response to obtaining an instruction signal of a reader, the digital baseband module determines a current uplink data transmission rate according to the instruction signal and queries the non-volatile storage module to determine whether there is a clock division coefficient adapted to the uplink data transmission rate, specifically comprising: If the uplink data transmission rate is directly specified by the instruction signal of the reader, the digital baseband module analyzes the instruction signal to obtain the uplink data transmission rate carried by the instruction signal; the non-volatile storage module has clock division coefficients and corresponding uplink data transmission rates stored in association; the digital baseband module queries the non-volatile storage module according to the uplink data transmission rate, and if the query hits, determines the clock division coefficient adapted to the uplink data transmission rate; If the uplink data transmission rate is determined according to the preamble length in the data frame of the instruction signal of the reader, the digital baseband module determines the uplink data transmission rate according to the preamble length in the data frame of the instruction signal; the non-volatile storage module has clock division coefficients and corresponding preamble lengths stored in association; the digital baseband module queries the non-volatile storage module according to the preamble length in the data frame of the instruction signal, and if the query hits, determines the clock division coefficient adapted to the uplink data transmission rate; If the non-volatile storage module has the clock division coefficient adapted thereto, the digital baseband module divides the main clock provided by the analog front end according to the clock division coefficient to obtain the division clock of the digital baseband module; If the non-volatile storage module does not have the clock division coefficient adapted thereto, the digital baseband module calculates the clock division coefficient according to the frequency of the main clock provided by the analog front end and the uplink data transmission rate, divides the main clock according to the clock division coefficient to obtain the division clock of the digital baseband module, and writes the clock division coefficient into the non-volatile storage module.

2. A label chip, characterized by Comprise: an analog front end, a digital baseband module and a non-volatile storage module; The analog front end is configured to generate the main clock of the system; The non-volatile storage module is configured to store clock division coefficients; The digital baseband module is configured to, in response to obtaining an instruction signal of a reader, determine a current uplink data transmission rate according to the instruction signal and query the non-volatile storage module to determine whether there is a clock division coefficient adapted to the uplink data transmission rate, specifically comprising: If the uplink data transmission rate is directly specified by the instruction signal of the reader, the digital baseband module analyzes the instruction signal to obtain the uplink data transmission rate carried by the instruction signal; the non-volatile storage module has clock division coefficients and corresponding uplink data transmission rates stored in association; the digital baseband module queries the non-volatile storage module according to the uplink data transmission rate, and if the query hits, determines the clock division coefficient adapted to the uplink data transmission rate; If the uplink data transmission rate is determined according to the preamble length in the data frame of the instruction signal of the reader, the digital baseband module determines the uplink data transmission rate according to the preamble length in the data frame of the instruction signal; the non-volatile storage module has associatedly stored clock division coefficients and corresponding preamble lengths; the digital baseband module queries the non-volatile storage module according to the preamble length in the data frame of the instruction signal, and if the query hits, determines the clock division coefficient adapted to the uplink data transmission rate; The digital baseband module is further configured to: if there is an adapted clock division coefficient in the non-volatile storage module, divide the master clock provided by the analog front end according to the clock division coefficient to obtain a divided clock of the digital baseband module; if there is no adapted clock division coefficient in the non-volatile storage module, calculate a clock division coefficient according to the frequency of the master clock and the uplink data transmission rate, divide the master clock according to the clock division coefficient to obtain a divided clock; and write the clock division coefficient into the non-volatile storage module.

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