Low voltage multiplier circuit and electronic device
By designing a low-voltage multiplier circuit composed of transistors and MOS tubes, and utilizing the logarithmic relationship of the transistors and the current mirror to eliminate the Early effect, the problems of small linear input range, large nonlinear error and high distortion of the low-voltage multiplier are solved, and a circuit structure with high linearity, low error and low distortion is achieved.
Patent Information
- Application Number
- CN202510979019.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-16
- Publication Date
- 2025-09-05
AI Technical Summary
Existing low-voltage multipliers have problems such as small linear input range, large nonlinear error and high distortion, and the circuit complexity is high.
A low-voltage multiplier circuit consisting of a first triode, a second triode, a third triode, a fourth triode and a first MOS transistor is adopted. The logarithmic relationship of the triodes is used to realize the multiplication and division operations of currents. The Early effect is eliminated by matching the current mirror and the MOS transistors, thereby simplifying the circuit structure.
A multiplier circuit with high linearity, low error and low distortion at low voltage is realized. The circuit structure is simple and the operating voltage only requires Vthn+VBE+Vos, which meets the low voltage application of 1.8V.
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Figure CN120597901A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of multipliers, and in particular to a low-voltage multiplier circuit and electronic equipment. Background Art
[0002] Multipliers, as fundamental building blocks in integrated circuits, are widely used in many signal processing fields, including artificial neural networks, adaptive filtering, modulation and demodulation, and frequency conversion. Currently, many design techniques and circuit structures are centered around optimizing various multiplier performance characteristics, such as high speed, low power consumption, low supply voltage, and high bandwidth. For example, in power factor correction (PFC) applications, most PFC control chips require a multiplier to implement their functionality.
[0003] There are many approaches to multiplier design: some exploit the square-law relationship between voltage and current in MOS transistors, some exploit the volt-ampere characteristics of MOS transistors in their linear region, and some utilize Gilbert cells. However, these approaches, in low-voltage multipliers, suffer from limited linear input range, large nonlinear errors, and high distortion, as well as high circuit complexity. Summary of the Invention
[0004] In view of the above-mentioned deficiencies in the prior art, an object of the present invention is to provide a low-voltage multiplier circuit and electronic equipment to solve the problems of small linear input range, large nonlinear error and high distortion of low-voltage multipliers.
[0005] The technical solutions of the present invention are as follows:
[0006] A low-voltage multiplier circuit comprises a first triode, a second triode, a third triode, a fourth triode and a first MOS transistor;
[0007] The base of the first transistor, the collector of the first transistor, the base of the second transistor, and the collector of the second transistor are used to receive a first current, the emitter of the first transistor and the emitter of the fourth transistor are used to receive a second current, the emitter of the second transistor, the emitter of the third transistor, the gate of the first MOS transistor, and the drain of the first MOS transistor are interconnected, the source of the first MOS transistor is grounded, the collector of the third transistor is used to output a third current, and the base of the third transistor, the base of the fourth transistor, and the collector of the fourth transistor are used to receive a fourth current.
[0008] Optionally, the low-voltage multiplier circuit further includes a second MOS transistor and a third MOS transistor;
[0009] The gate of the second MOS transistor, the drain of the second MOS transistor, and the gate of the third MOS transistor are used to access the first current, the source of the second MOS transistor is connected to the collector of the first triode, the drain of the third MOS transistor is used to access the second current, and the source of the third MOS transistor is connected to the collector of the third triode.
[0010] Optionally, the first triode, the second triode, the third triode and the fourth triode have the same size.
[0011] Optionally, the low-voltage multiplier circuit further includes:
[0012] An input circuit, wherein the power supply end of the input circuit is used to connect to a power supply, the first output end of the input circuit is used to output a first current, the second output end of the input circuit is used to output a second current, and the third output end of the input circuit is used to output a fourth current. The first input end of the input circuit is used to receive the first input current, the second input end of the input circuit is used to receive the second input current, and the third input end of the input circuit is used to receive the third input current. The input circuit is used to output the first current after adding the first input current and the second input current. The input circuit is also used to output the second current after adding the first input current and the fourth current. The input circuit is also used to output the fourth current after converting the third input current.
[0013] Optionally, the input circuit includes a first current mirror, a second current mirror, a third current mirror, a fourth current mirror and a fifth current mirror, the input end of the first current mirror is used to connect to the first input current, the output end of the second current mirror is used to output the second current, the input end of the third current mirror is connected to the output end of the first current mirror, the output end of the third current mirror is used to output the first current, the fourth current mirror is connected to the third current mirror, the input end of the fourth current mirror is used to connect to the second input current, the fifth current mirror is connected to the second current mirror, and the output end of the fifth current mirror is used to output the fourth current.
[0014] Optionally, the first current mirror includes a fourth MOS transistor, a fifth MOS transistor, and a sixth MOS transistor, the second current mirror includes a seventh MOS transistor and an eighth MOS transistor, the third current mirror includes a ninth MOS transistor and a tenth MOS transistor, the fourth current mirror includes an eleventh MOS transistor and a twelfth MOS transistor, and the fifth current mirror includes a thirteenth MOS transistor, a fourteenth MOS transistor, and a fifteenth MOS transistor;
[0015] The gate of the fourth MOS transistor, the drain of the fourth MOS transistor, the gate of the fifth MOS transistor, and the gate of the sixth MOS transistor are used to receive a first input current; the source of the fourth MOS transistor, the source of the fifth MOS transistor, the source of the sixth MOS transistor, the source of the seventh MOS transistor, and the source of the eighth MOS transistor are grounded; the drain of the sixth MOS transistor and the drain of the seventh MOS transistor are used to output a second current; the gate of the seventh MOS transistor, the gate of the eighth MOS transistor, the drain of the eighth MOS transistor, and the drain of the thirteenth MOS transistor are interconnected; the drain of the fifth MOS transistor, the gate of the ninth MOS transistor, the drain of the ninth MOS transistor, and the gate of the tenth MOS transistor are interconnected. The drain of the tenth MOS transistor and the drain of the eleventh MOS transistor are used to output a first current; the gate of the eleventh MOS transistor, the gate of the twelfth MOS transistor, and the drain of the twelfth MOS transistor are used to receive a second input current; the gate of the thirteenth MOS transistor, the gate of the fourteenth MOS transistor, the gate of the fifteenth MOS transistor, and the drain of the fifteenth MOS transistor are interconnected; the drain of the fourteenth MOS transistor is used to output a fourth current; and the source of the ninth MOS transistor, the source of the tenth MOS transistor, the source of the eleventh MOS transistor, the source of the twelfth MOS transistor, the source of the thirteenth MOS transistor, the source of the fourteenth MOS transistor, and the source of the fifteenth MOS transistor are used to connect to a power supply.
[0016] Optionally, the fourth MOS transistor, the fifth MOS transistor, and the sixth MOS transistor have the same size, the seventh MOS transistor and the eighth MOS transistor have the same size, the ninth MOS transistor and the tenth MOS transistor have the same size, the eleventh MOS transistor and the twelfth MOS transistor have the same size, and the thirteenth MOS transistor, the fourteenth MOS transistor, and the fifteenth MOS transistor have the same size.
[0017] The present invention further provides an electronic device comprising a plurality of the low-voltage multiplier circuits described above, wherein the plurality of the low-voltage multiplier circuits are cascaded.
[0018] Optionally, the electronic device further includes:
[0019] Multiple current mirrors, the input ends of the multiple current mirrors are connected one-to-one with the output ends of the multiple low-voltage multiplier circuits, and the current mirrors are used to convert the current signal output by the low-voltage multiplier circuit into a current source and then output it.
[0020] Optionally, the electronic device further includes:
[0021] A processor, wherein an input end of the processor is connected to the output ends of the multiple current mirrors, and the processor is used to receive the current sources output by the multiple current mirrors and perform conversion processing on the current sources.
[0022] Through the connection relationship of the above structure, the present invention makes it possible to eliminate the need for an additional operational amplifier in the low-voltage multiplier circuit, simplify the circuit structure, and only require an operating voltage of Vthn+VBE+Vos, where Vthn is the threshold value of the NMOS transistor, typically 0.4V, VBE is the voltage drop between the base and emitter of the transistor, typically about 0.6V, and Vos is the saturation voltage drop of the MOS transistor, typically 0.2V, meeting the requirements of a low-voltage application of 1.8V. In addition, the matching between the transistors makes the present structure have the advantages of high linearity, small error, and low distortion. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary personnel in this field, other drawings can be obtained based on the structures shown in these drawings without paying any creative work.
[0024] Figure 1 1 is a circuit structure diagram of an embodiment of a low-voltage multiplier circuit of the present invention.
[0025] Figure 2 2 is a circuit structure diagram of another embodiment of the low-voltage multiplier circuit of the present invention.
[0026] Figure 3 It is a circuit structure diagram of an embodiment of an input circuit in a low-voltage multiplier circuit of the present invention.
[0027] Explanation of the accompanying symbols: Q1, first triode; Q2, second triode; Q3, third triode; Q4, fourth triode; MN1, first MOS transistor; MN2, second MOS transistor; MN3, third MOS transistor; N1, fourth MOS transistor; N2, fifth MOS transistor; N3, sixth MOS transistor; N4, seventh MOS transistor; N5, eighth MOS transistor; P1, ninth MOS transistor; P2, tenth MOS transistor; P3, eleventh MOS transistor; P4, twelfth MOS transistor; P5, thirteenth MOS transistor; P6, fourteenth MOS transistor; P7, fifteenth MOS transistor; I12, first current; I14, second current; I1, first input current; I2, second input current; I3, third current; I4, fourth current; I7, third input current; VCC, power supply. DETAILED DESCRIPTION
[0028] In order to make the purpose, technical solution and effect of the present invention clearer and more specific, the present invention is further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.
[0029] In the embodiments and patent claims, unless otherwise specified herein, the words "a," "an," "the," and "the" may include plural forms. If the embodiments of the present invention include descriptions of "first," "second," etc., such descriptions are for descriptive purposes only and should not be understood as indicating or implying their relative importance or implicitly specifying the number of the technical features indicated. Therefore, a feature specified as "first" or "second" may explicitly or implicitly include at least one of such features.
[0030] It should be further understood that the term "comprising" as used in the description of the present invention refers to the presence of the features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof. It should be understood that when an element is said to be "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there can be intermediate elements. In addition, "connected" or "coupled" as used herein can include wireless connections or wireless couplings. The term "and / or" as used herein includes all or any units and all combinations of one or more associated listed items.
[0031] It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art in the art to which the present invention belongs. It should also be understood that terms such as those defined in common dictionaries should be understood to have meanings consistent with their meanings in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless specifically defined as herein.
[0032] In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the fact that ordinary technicians in this field can implement them. When the combination of technical solutions is mutually contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.
[0033] Multipliers, as fundamental building blocks in integrated circuits, are widely used in many signal processing fields, including artificial neural networks, adaptive filtering, modulation and demodulation, and frequency conversion. Currently, many design techniques and circuit structures are centered around optimizing various multiplier performance characteristics, such as high speed, low power consumption, low supply voltage, and high bandwidth. For example, in power factor correction (PFC) applications, most PFC control chips require a multiplier to implement their functionality.
[0034] There are many approaches to multiplier design: some exploit the square-law relationship between voltage and current in MOS transistors, some exploit the volt-ampere characteristics of MOS transistors in their linear region, and some utilize Gilbert cells. However, these approaches, in low-voltage multipliers, suffer from limited linear input range, large nonlinear errors, and high distortion, as well as high circuit complexity.
[0035] To solve the above problems, the present invention provides a low-voltage multiplier circuit.
[0036] Reference Figure 1 In one embodiment, the low voltage multiplier circuit includes a first transistor Q1, a second transistor Q2, a third transistor Q3, a fourth transistor Q4 and a first MOS transistor MN1;
[0037] The base of the first transistor Q1, the collector of the first transistor Q1, the base of the second transistor Q2, and the collector of the second transistor Q2 are used to receive the first current I12; the emitter of the first transistor Q1 and the emitter of the fourth transistor Q4 are used to receive the second current I14; the emitter of the second transistor Q2, the emitter of the third transistor Q3, the gate of the first MOS transistor MN1, and the drain of the first MOS transistor MN1 are interconnected; the source of the first MOS transistor MN1 is grounded; the collector of the third transistor Q3 is used to output the third current I3; the base of the third transistor Q3, the base of the fourth transistor Q4, and the collector of the fourth transistor Q4 are used to receive the fourth current I4.
[0038] Furthermore, the first transistor Q1 , the second transistor Q2 , the third transistor Q3 and the fourth transistor Q4 have the same size.
[0039] In this embodiment, the first transistor Q1, the second transistor Q2, the third transistor Q3, and the fourth transistor Q4 can be NPN transistors, and the first MOS transistor MN1 can be an NMOS transistor. The low-voltage multiplier circuit utilizes the logarithmic relationship between the voltage and current of the transistors, and can realize current multiplication and division operations by adding and subtracting the transistor voltages.
[0040] right Figure 1The circuit structure is analyzed as follows:
[0041] Because the transistor works in the amplification region, its collector current I c and the base-emitter voltage drop V BE The relationship is:
[0042]
[0043] Among them I S is a constant used to describe the transfer characteristics of the transistor in the forward amplification region, V T is the thermal voltage, which is about 26mV at room temperature. When the amplification factor of the transistor is sufficient, the base current can be ignored relative to the collector current. For the fourth transistor Q4, its collector current is I4, which is the same as the fourth current I4. The collector current of the third transistor Q3 is I3, which is the same as the third current I3. The collector current of the first transistor Q1 is set to I1, and the collector current of the second transistor Q2 is set to I2. According to Figure 1 The circuit connections are:
[0044]
[0045] I 12 =I1+I2;
[0046] I 14 =I1+I4;
[0047] Among them, I 12 The magnitude of the first current I12 is the same as that of the first current I12. 14 The magnitude of the second current I14 is the same as that of the second current I14, V BE1 is the base-emitter voltage drop V of the first transistor Q1 BE2 is the base-emitter voltage drop V of the second transistor Q2 BE3 is the base-emitter voltage drop V of the third transistor Q3 BE4 is the base-emitter voltage drop of the fourth transistor Q4; because the first transistor Q1, the second transistor Q2, the third transistor Q3 and the fourth transistor Q4 use transistors of the same size and fully matched, their I S Similarly, we can divide I1 / I2 and I4 / I3 respectively to obtain:
[0048]
[0049] Depend on Figure 1 The connection relationship of the first transistor Q1 is BE1 Subtract the V of the second transistor Q2 BE2 Equal to the V of the fourth transistor Q4 BE4 Subtract the V of the third transistor Q3 BE3 ,Right now:
[0050] V BE1 -V BE2 =V BE4 -V BE3 ;
[0051] so:
[0052]
[0053] We can further obtain:
[0054]
[0055] From the above analysis, we can see that the current I 12 is the sum of currents I1 and I2, current I 14 The present invention makes the output current I3 have a fixed multiplication and division relationship with I1, I2 and I4. If the current I1 is set as a fixed current, the output current I3 is the product of I2 and I4 in a set ratio; if the current I2 (or I4) is set as a fixed current, the output current I3 and the value of I4 (or I2) divided by I1 are the set ratio, and the linear error is extremely small. In addition, the above multiplication and division relationships are not affected by the transistor V BE 、V T 、V A and I S The influence of other parameters is reduced, and the dependence on process and temperature is reduced. In summary, the circuit structure of the present invention does not require an additional op amp and has a simple circuit structure. The operating voltage only requires Vthn+VBE+Vos, where Vthn is the NMOS transistor threshold, typically about 0.4V, VBE is the transistor base-emitter voltage drop, typically about 0.6V, and Vos is the MOS transistor saturation voltage drop, typically about 0.2V, which meets the low voltage application of 1.8V. In addition, the matching between the transistors makes this structure have the advantages of high linearity, small error and low distortion.
[0056] In addition, the multiplier can also use the voltage and current of the transistor with a logarithmic relationship to achieve multiplication, but it does not take into account the Early effect of the transistor. The collector-emitter voltage drops of the transistor that achieves the logarithmic relationship are different, which will cause linear errors.
[0057] Therefore, refer to Figure 3 In one embodiment, the low-voltage multiplier circuit further includes a second MOS transistor MN2 and a third MOS transistor MN3;
[0058] The gate of the second MOS transistor MN2, the drain of the second MOS transistor MN2, and the gate of the third MOS transistor MN3 are used to receive the first current I12. The source of the second MOS transistor MN2 is connected to the collector of the first transistor Q1. The drain of the third MOS transistor MN3 is used to receive the second current I14. The source of the third MOS transistor MN3 is connected to the collector of the third transistor Q3.
[0059] In this embodiment, in order to further improve the linearity of the low voltage multiplier, the Early effect of the transistor is considered and the corrected transistor collector current I is obtained. C as follows:
[0060]
[0061] Among them I S A constant used to describe the transfer characteristics of the transistor in the forward amplification region, with a typical value of about 10exp(-14)A to 10exp(-16)A; V CE is the transistor collector-emitter voltage drop; V A is the Early voltage, with a typical value of about 10V to 100V; V T is the thermal voltage, which is about 26mV at room temperature. It can be seen that if the V CE If the voltages are the same, the influence of the Early voltage can be eliminated and the calculation is performed according to the above formula. The V CE The difference between the Early voltage V A Compared with two orders of magnitude smaller, V A The influence of V between different transistors can be ignored. CE The difference is within hundreds of mV, and the Early voltage V A The influence is small, so a reasonable approximation is made. The first transistor Q1, the second transistor Q2, the third transistor Q3 and the fourth transistor Q4 are the same transistors, and their V BE The second MOS transistor MN2 and the third MOS transistor MN3 are matched, and their gate-source voltages are approximately equal, V GS2 -V GS3 , V GS2 is the gate-source voltage of the second MOS transistor MN2, V GS3 is the gate-source voltage of the third MOS tube MN3, according to Figure 3 The circuit connection relationship is:
[0062] V CE1 =V BE1 =V BE ;
[0063] V CE2 =V BE2 =V BE ;
[0064] V CE3 =V BE1 +V GS2 -V GS3 =V BE ;
[0065] V CE4 =V BE4 =V BE ;
[0066] From this we can see that:
[0067] V CE1 =V CE2 =V CE3 =V CE4 =V BE ;
[0068] So refer to Figure 3 The low-voltage multiplier circuit of the present invention can eliminate the influence of the Early effect and has high linearity.
[0069] In one embodiment, the low voltage multiplier circuit further includes:
[0070] An input circuit, wherein the power supply end of the input circuit is used to connect to a power supply, the first output end of the input circuit is used to output a first current I12, the second output end of the input circuit is used to output a second current I14, and the third output end of the input circuit is used to output a fourth current I4. The first input end of the input circuit is used to connect to the first input current I1, the second input end of the input circuit is used to connect to the second input current I2, and the third input end of the input circuit is used to connect to the third input current I7. The input circuit is used to add the first input current I1 and the second input current I2 and then output the first current I12. The input circuit is also used to add the first input current I1 and the fourth current I4 and then output the second current I14. The input circuit is also used to convert the third input current I7 and then output the fourth current I4.
[0071] In addition, the input circuit includes a first current mirror, a second current mirror, a third current mirror, a fourth current mirror and a fifth current mirror, wherein the input end of the first current mirror is used to connect to the first input current I1, the output end of the second current mirror is used to output the second current I14, the input end of the third current mirror is connected to the output end of the first current mirror, the output end of the third current mirror is used to output the first current I12, the fourth current mirror is connected to the third current mirror, the input end of the fourth current mirror is used to connect to the second input current I2, the fifth current mirror is connected to the second current mirror, and the output end of the fifth current mirror is used to output the fourth current I4.
[0072] Further, refer to Figure 3 In one embodiment, the first current mirror includes a fourth MOS transistor N1, a fifth MOS transistor N2, and a sixth MOS transistor N3; the second current mirror includes a seventh MOS transistor N4 and an eighth MOS transistor N5; the third current mirror includes a ninth MOS transistor P1 and a tenth MOS transistor P2; the fourth current mirror includes an eleventh MOS transistor P3 and a twelfth MOS transistor P4; and the fifth current mirror includes a thirteenth MOS transistor P5, a fourteenth MOS transistor P6, and a fifteenth MOS transistor P7.
[0073] The gate of the fourth MOS transistor N1, the drain of the fourth MOS transistor N1, the gate of the fifth MOS transistor N2, and the gate of the sixth MOS transistor N3 are used to receive the first input current I1. The source of the fourth MOS transistor N1, the source of the fifth MOS transistor N2, the source of the sixth MOS transistor N3, the source of the seventh MOS transistor N4, and the source of the eighth MOS transistor N5 are grounded. The drain of the sixth MOS transistor N3 and the drain of the seventh MOS transistor N4 are used to output the second current I14. The gate of the seventh MOS transistor N4, the gate of the eighth MOS transistor N5, the drain of the eighth MOS transistor N5, and the drain of the thirteenth MOS transistor P5 are interconnected. The drain of the fifth MOS transistor N2, the gate of the ninth MOS transistor P1, the drain of the ninth MOS transistor P1, and the gate of the tenth MOS transistor P2 are interconnected. The drain of the tenth MOS transistor P2 and the drain of the eleventh MOS transistor P3 are connected, the drain of the tenth MOS transistor P2 and the drain of the eleventh MOS transistor P3 are used to output the first current I12, the gate of the eleventh MOS transistor P3, the gate of the twelfth MOS transistor P4, and the drain of the twelfth MOS transistor P4 are used to receive the second input current I2, the gate of the thirteenth MOS transistor P5, the gate of the fourteenth MOS transistor P6, the gate of the fifteenth MOS transistor P7, and the drain of the fifteenth MOS transistor P7 are interconnected, the drain of the fourteenth MOS transistor P6 is used to output the fourth current, and the source of the ninth MOS transistor P1, the source of the tenth MOS transistor P2, the source of the eleventh MOS transistor P3, the source of the twelfth MOS transistor P4, the source of the thirteenth MOS transistor P5, the source of the fourteenth MOS transistor P6, and the source of the fifteenth MOS transistor P7 are connected to the power supply VCC.
[0074] Furthermore, the fourth MOS transistor N1, the fifth MOS transistor N2, and the sixth MOS transistor N3 have the same size, the seventh MOS transistor N4 and the eighth MOS transistor N5 have the same size, the ninth MOS transistor P1 and the tenth MOS transistor P2 have the same size, the eleventh MOS transistor P3 and the twelfth MOS transistor P4 have the same size, and the thirteenth MOS transistor P5, the fourteenth MOS transistor P6, and the fifteenth MOS transistor P7 have the same size.
[0075] In this embodiment, the fourth MOS transistor N1, the fifth MOS transistor N2, the sixth MOS transistor N3, the seventh MOS transistor N4 and the eighth MOS transistor N5 are NMOS transistors, the ninth MOS transistor P1, the tenth MOS transistor P2, the eleventh MOS transistor P3, the twelfth MOS transistor P4, the thirteenth MOS transistor P5, the fourteenth MOS transistor P6 and the fifteenth MOS transistor P7 are PMOS transistors, and the current adding circuit of the multiplier circuit of the present invention is Figure 1 and Figure 2 According to the circuit analysis, the current I 12is the sum of currents I1 and I2, current I 14 is the sum of currents I1 and I4. Current addition is simple to implement, such as Figure 2 As shown, a current adding circuit is provided for inputting current. It should be noted that the magnitude of the first current I12 is related to the current I 12 The first current I12 is also the sum of the currents of the first transistor Q1 and the second transistor Q2; the magnitude of the second current I14 is the same as the current I 14 The third current I3 is the same as the current I3, and the fourth current I4 is the same as the current I4. Figure 2 The third input current I7 is copied and converted by the fifth current mirror to output a fourth current I4, which has the same magnitude as the current I7. The fourth current I4 has the same magnitude as the third input current I7.
[0076] from Figure 2 It can be seen from the connection relationship that the fourth MOS transistor N1, the fifth MOS transistor N2 and the sixth MOS transistor N3 form a first current mirror. When the same size is set, their currents are equal, that is:
[0077] I1=I N1 =I N2 =I N3 ;
[0078] The seventh MOS transistor N4 and the eighth MOS transistor N5 form a second current mirror. When the same size is set, their currents are equal, that is:
[0079] I P4 =I N5 =I N4 ;
[0080] The ninth MOS transistor P1 and the tenth MOS transistor P2 form a third current mirror. When the same size is set, their currents are equal, that is:
[0081] I N2 =I P1 =I P2 ;
[0082] The eleventh MOS transistor P3 and the twelfth MOS transistor P4 form a fourth current mirror. When the same size is set, their currents are equal, that is:
[0083] I2=I P4 =I P3 ;
[0084] The thirteenth MOS transistor P5, the fourteenth MOS transistor P6 and the fifteenth MOS transistor P7 form a fifth current mirror. When the same size is set, their currents are equal, that is:
[0085] I7=I4=I P5 ;
[0086] in,
[0087] I 12 =I P2 +I P3 =I1+I2;
[0088] I 14 =I N3 +I N4 =I1+I4;
[0089] In this way, current addition is achieved. In addition, the ratio of the current mirror can be adjusted to achieve current addition of different ratios. It should be noted that by inputting the current addition signal, i.e., the first current I12 and the second current I14, to the transistor in the low-voltage multiplier circuit through the input circuit, the linear combination of the input signals can be ensured, thereby enabling the low-voltage multiplier to maintain linear characteristics within a certain range; and in a low-voltage environment, the signal strength is often weak and easily affected by interference such as noise. By adding multiple input current signals, the overall amplitude of the signal can be increased, thereby enhancing the circuit's signal processing capability.
[0090] The present invention also provides an electronic device.
[0091] In one embodiment, the electronic device includes a plurality of the low-voltage multiplier circuits described above, and the plurality of the low-voltage multiplier circuits are cascaded.
[0092] In this embodiment, it is understood that since the above-described low-voltage multiplier circuit is used in the electronic device of the present invention, the embodiments of the electronic device of the present invention include all technical solutions of all embodiments of the above-described low-voltage multiplier circuit, and the technical effects achieved are also identical, which will not be repeated here. To achieve more current multiplication and division, multiple low-voltage multiplier circuits can be cascaded. For example, two low-voltage multiplier circuits can be connected, and the third current output by one low-voltage multiplier circuit can be used as the input current of the other low-voltage multiplier circuit.
[0093] In one embodiment, the electronic device further includes:
[0094] Multiple current mirrors, the input ends of the multiple current mirrors are connected one-to-one with the output ends of the multiple low-voltage multiplier circuits, and the current mirrors are used to convert the current signal output by the low-voltage multiplier circuit into a current source and then output it.
[0095] In this embodiment, the current signal output by the low-voltage multiplier circuit refers to the current magnitude of I3. I3 is a current sink and can be converted into a current source through a current mirror and output to a subsequent circuit for processing.
[0096] In one embodiment, the electronic device further includes:
[0097] A processor, wherein an input end of the processor is connected to the output ends of the multiple current mirrors, and the processor is used to receive the current sources output by the multiple current mirrors and perform conversion processing on the current sources.
[0098] In this embodiment, the processor can be a digital signal processor (DSP), a programmable logic device (PLD), a microprocessor, an MCU, or other electronic components. The processor can convert the current sources output by the multiple current mirrors, i.e., analog signals, into digital signals to facilitate subsequent data processing.
[0099] It should be understood that the application of the present invention is not limited to the above examples. For those skilled in the art, improvements or changes can be made based on the above description. All these improvements and changes should fall within the scope of protection of the claims attached to the present invention.
Claims
1. A low voltage multiplier circuit, characterized in that: It includes a first triode, a second triode, a third triode, a fourth triode and a first MOS tube; The base of the first transistor, the collector of the first transistor, the base of the second transistor, and the collector of the second transistor are used to receive a first current, the emitter of the first transistor and the emitter of the fourth transistor are used to receive a second current, the emitter of the second transistor, the emitter of the third transistor, the gate of the first MOS transistor, and the drain of the first MOS transistor are interconnected, the source of the first MOS transistor is grounded, the collector of the third transistor is used to output a third current, and the base of the third transistor, the base of the fourth transistor, and the collector of the fourth transistor are used to receive a fourth current.
2. The low voltage multiplier circuit according to claim 1, wherein: The low voltage multiplier circuit further includes a second MOS tube and a third MOS tube; The gate of the second MOS transistor, the drain of the second MOS transistor, and the gate of the third MOS transistor are used to access the first current, the source of the second MOS transistor is connected to the collector of the first triode, the drain of the third MOS transistor is used to access the second current, and the source of the third MOS transistor is connected to the collector of the third triode.
3. The low voltage multiplier circuit according to claim 1, wherein: The first transistor, the second transistor, the third transistor and the fourth transistor have the same size.
4. The low voltage multiplier circuit according to claim 1, wherein: The low voltage multiplier circuit further includes: An input circuit, wherein the power supply end of the input circuit is used to connect to a power supply, the first output end of the input circuit is used to output a first current, the second output end of the input circuit is used to output a second current, and the third output end of the input circuit is used to output a fourth current. The first input end of the input circuit is used to receive the first input current, the second input end of the input circuit is used to receive the second input current, and the third input end of the input circuit is used to receive the third input current. The input circuit is used to output the first current after adding the first input current and the second input current. The input circuit is also used to output the second current after adding the first input current and the fourth current. The input circuit is also used to output the fourth current after converting the third input current.
5. The low voltage multiplier circuit according to claim 4, wherein: The input circuit includes a first current mirror, a second current mirror, a third current mirror, a fourth current mirror and a fifth current mirror, wherein the input end of the first current mirror is used to receive the first input current, the output end of the second current mirror is used to output the second current, the input end of the third current mirror is connected to the output end of the first current mirror, the output end of the third current mirror is used to output the first current, the fourth current mirror is connected to the third current mirror, the input end of the fourth current mirror is used to receive the second input current, the fifth current mirror is connected to the second current mirror, and the output end of the fifth current mirror is used to output the fourth current.
6. The low voltage multiplier circuit according to claim 5, wherein: The first current mirror includes a fourth MOS transistor, a fifth MOS transistor, and a sixth MOS transistor, the second current mirror includes a seventh MOS transistor and an eighth MOS transistor, the third current mirror includes a ninth MOS transistor and a tenth MOS transistor, the fourth current mirror includes an eleventh MOS transistor and a twelfth MOS transistor, and the fifth current mirror includes a thirteenth MOS transistor, a fourteenth MOS transistor, and a fifteenth MOS transistor; The gate of the fourth MOS transistor, the drain of the fourth MOS transistor, the gate of the fifth MOS transistor, and the gate of the sixth MOS transistor are used to receive a first input current; the source of the fourth MOS transistor, the source of the fifth MOS transistor, the source of the sixth MOS transistor, the source of the seventh MOS transistor, and the source of the eighth MOS transistor are grounded; the drain of the sixth MOS transistor and the drain of the seventh MOS transistor are used to output a second current; the gate of the seventh MOS transistor, the gate of the eighth MOS transistor, the drain of the eighth MOS transistor, and the drain of the thirteenth MOS transistor are interconnected; the drain of the fifth MOS transistor, the gate of the ninth MOS transistor, the drain of the ninth MOS transistor, and the gate of the tenth MOS transistor are interconnected. The drain of the tenth MOS transistor and the drain of the eleventh MOS transistor are used to output a first current; the gate of the eleventh MOS transistor, the gate of the twelfth MOS transistor, and the drain of the twelfth MOS transistor are used to receive a second input current; the gate of the thirteenth MOS transistor, the gate of the fourteenth MOS transistor, the gate of the fifteenth MOS transistor, and the drain of the fifteenth MOS transistor are interconnected; the drain of the fourteenth MOS transistor is used to output a fourth current; and the source of the ninth MOS transistor, the source of the tenth MOS transistor, the source of the eleventh MOS transistor, the source of the twelfth MOS transistor, the source of the thirteenth MOS transistor, the source of the fourteenth MOS transistor, and the source of the fifteenth MOS transistor are used to connect to a power supply.
7. The low voltage multiplier circuit according to claim 6, wherein: The fourth MOS transistor, the fifth MOS transistor, and the sixth MOS transistor have the same size, the seventh MOS transistor and the eighth MOS transistor have the same size, the ninth MOS transistor and the tenth MOS transistor have the same size, the eleventh MOS transistor and the twelfth MOS transistor have the same size, and the thirteenth MOS transistor, the fourteenth MOS transistor, and the fifteenth MOS transistor have the same size.
8. An electronic device, characterized in that: The invention comprises a plurality of low-voltage multiplier circuits according to any one of claims 1 to 7, wherein the plurality of low-voltage multiplier circuits are cascaded.
9. The electronic device according to claim 8, wherein The electronic device further comprises: Multiple current mirrors, the input ends of the multiple current mirrors are connected one-to-one with the output ends of the multiple low-voltage multiplier circuits, and the current mirrors are used to convert the current signal output by the low-voltage multiplier circuit into a current source and then output it.
10. The electronic device according to claim 9, wherein The electronic device further comprises: A processor, wherein an input end of the processor is connected to the output ends of the multiple current mirrors, and the processor is used to receive the current sources output by the multiple current mirrors and perform conversion processing on the current sources.