Internal test method of chip, chip and related equipment

Abstract

The invention provides an internal test method of a chip, the chip and related equipment, and relates to the technical field of chips. The chip comprises a read-only memory (ROM) and an internal test circuit, and the method comprises the following steps: reading a to-be-tested storage unit in the ROM through the internal test circuit to obtain a read value corresponding to the to-be-tested storage unit. And the internal test circuit is used for performing logical operation on data stored in the to-be-tested storage unit. And according to the read value and the characteristic value corresponding to the to-be-tested storage unit, determining a failure bit of the actual storage data of the to-be-tested storage unit. Wherein the characteristic value is a value obtained by calculating the inherent value corresponding to the storage unit to be tested according to the operation logic corresponding to the internal test circuit. And according to the invalid bit information, the position information of the to-be-tested storage unit in the ROM and the position information of the ROM in the chip, determining and outputting coordinates of the invalid bit in the chip.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of chip technology, and in particular to a chip internal testing method, chip, and related equipment. Background Art

[0002] Current system-on-chips (SoCs) contain a large amount of embedded memory, primarily static random access memory (SRAM) and read-only memory (ROM). ROM operates in a non-destructive read mode, allowing only reading but not writing data. Because data stored in ROM cannot be overwritten, ROM in chips often stores various fixed programs and data.

[0003] Typically, the data stored in ROM is written before the chip is packaged. Understandably, if a ROM storage failure occurs during chip operation, meaning that some of the data stored in the ROM becomes invalid, it will seriously affect the chip's functionality. Therefore, testing and diagnosing the ROM storage status is a prerequisite for preventing the spread of ROM storage failures. Because the on-chip ROM cannot be directly accessed through the chip pins, automated test equipment (ATE) cannot be used to analyze and diagnose the on-chip ROM storage status. Testing and diagnosing the on-chip ROM using the chip's embedded CPU not only results in complex algorithms and low diagnostic efficiency, but also fails to guarantee that the CPU can access all ROMs. Therefore, how to efficiently and accurately diagnose the storage status of the on-chip ROM has become an urgent problem that needs to be solved. Summary of the Invention

[0004] The present invention provides a chip internal test method, chip, and related equipment. By integrating an internal test circuit for ROM within the chip, the chip automatically diagnoses the storage status of the on-chip ROM. The integrated internal test circuit ensures that all ROMs within the chip are fully accessed and tested. Furthermore, the internal test process based on the internal test circuit is concise and can efficiently and accurately determine the storage status of the ROM.

[0005] In a first aspect, embodiments of the present application provide an internal test method for a chip. During the chip development phase, an internal test circuit for a read-only memory (ROM) is integrated into the chip. When the chip internal test process is initiated, a memory cell to be tested in the ROM is first determined, and then the memory cell to be tested is read through the internal test circuit to obtain a read value. The internal test circuit is used to perform logical operations on the data stored in the memory cell to be tested. That is, when the memory cell to be tested is read through the internal test circuit, the actual stored data of the memory cell to be tested is input into the internal test circuit, and then the internal test circuit calculates the actual stored data and outputs a calculated value (i.e., the read value). Then, a characteristic value corresponding to the memory cell to be tested is obtained. It can be understood that the characteristic value is the value corresponding to the inherent value that the memory cell to be tested should store after calculation. The calculation logic for the inherent value is consistent with the calculation logic of the internal test circuit. The read value and characteristic value corresponding to the memory cell to be tested are then compared. It can be understood that if the read value and the characteristic value are consistent, then it means that the actual stored data of the memory cell to be tested is the inherent value that it should store, and the memory cell to be tested has no storage fault. If the read value and the characteristic value are inconsistent, it indicates that the memory cell under test has a storage fault and some of its data is invalid. By comparing the read value and the characteristic value, the failed bit in the actual data stored in the memory cell under test can be diagnosed. Finally, based on the failed bit information, the location of the memory cell under test in the ROM, and the location of the ROM on the chip, the coordinates of the failed bit on the chip are located.

[0006] In an embodiment of the present application, the internal test circuit can calculate the storage data in the ROM before outputting it, thus ensuring the security and confidentiality of the stored data. When testing the ROM, the memory cell to be tested is first determined based on the memory cell address, and then the memory cell to be tested is read by the internal test circuit to obtain the read value corresponding to the memory cell to be tested. By comparing the read value with the characteristic value of the memory cell to be tested, the failure bit of the actual storage data of the memory cell to be tested can be diagnosed. In this way, the storage fault in the ROM can be quickly and accurately located. In addition, the internal test circuit can access each ROM memory cell in sequence according to the memory cell address, which can achieve a comprehensive test of the ROM. At the same time, the chip fault diagnosis steps are simple, thereby further improving the test diagnosis efficiency of the chip.

[0007] In an optional embodiment, the inherent value that the memory cell to be tested should originally store is written into the internal test program of the chip and is not disclosed to the outside. During the test process, the actual storage data of the memory cell to be tested can be inferred based on the read value of the memory cell to be tested output by the internal test circuit, the characteristic value of the memory cell to be tested, and the operation logic corresponding to the internal test circuit. Then, the internal test program outputs the failure bit of the actual storage data of the memory cell to be tested by comparing the actual storage data of the memory cell to be tested with the inherent value corresponding to the memory cell to be tested. In the embodiment of the present application, the inherent value of the ROM is not disclosed to the outside, but is written into the internal test program corresponding to the internal test circuit, so that the security and confidentiality of the ROM storage data can be guaranteed. The internal test program can quickly and accurately locate ROM storage faults by comparing the actual storage data of the memory cell to be tested with the inherent value of the memory cell to be tested.

[0008] In an optional embodiment, after determining the failed bit of the actual stored data of the memory cell under test, the internal test program also needs to compare the failed bit with the inherent value corresponding to the memory cell under test and output the failed bit information corresponding to the failed bit, such as the transition of a logic "0" on a certain bit to "1".

[0009] In an optional embodiment, the internal test circuit's operating logic may perform a bitwise AND operation with a preset data. That is, the read value corresponding to the memory cell under test obtained by the internal test circuit is the data obtained by performing a bitwise AND operation on the actual storage data of the memory cell under test and the preset data.

[0010] In one optional embodiment, the internal test circuit's corresponding arithmetic logic compresses the values ​​corresponding to all memory cells between the starting memory cell and the memory cell to be tested in the ROM. This means the internal test circuit is a compression circuit. For example, if the address of the memory cell to be tested is 9, the read value corresponding to the memory cell to be tested obtained by the internal test circuit is the compressed value of the 10 stored data stored in all memory cells at addresses 0 to 9.

[0011] In a second aspect, an embodiment of the present application provides a chip, which includes a read-only memory (ROM), an internal test circuit, and an analysis module. The internal test circuit includes a control module and an operation module.

[0012] The control module is used to read the read value corresponding to the storage unit to be tested in the ROM output by the operation module, and the operation module is used to perform logical operations on the actual storage data of the storage unit to be tested.

[0013] The analysis module is configured to determine the failed bit of the actual stored data of the memory cell under test based on the read value and the characteristic value corresponding to the memory cell under test. The characteristic value is the value obtained by calculating the inherent value corresponding to the memory cell under test according to the operation logic corresponding to the operation module.

[0014] The analysis module is further configured to determine and output the coordinates of the failed bit in the chip based on the failed bit information, the position information of the storage unit to be tested in the ROM, and the position information of the ROM in the chip.

[0015] In an optional embodiment, the analysis module is specifically configured to determine actual stored data of the memory cell under test based on the read value, the characteristic value, and the operation logic corresponding to the calculation module, and to compare the actual stored data with the inherent value corresponding to the memory cell under test to determine the failed bit of the actual stored data.

[0016] In an optional implementation, the analysis module is further configured to determine and output the fail bit information corresponding to the memory cell to be tested based on the fail bit information and the inherent value corresponding to the memory cell to be tested.

[0017] In an optional implementation, the operation logic corresponding to the operation module is: performing a bitwise AND operation with preset data.

[0018] In an optional implementation, the operation logic corresponding to the operation module is: compressing the values ​​corresponding to all storage cells between the starting storage cell and the storage cell to be tested of the ROM.

[0019] In a third aspect, an embodiment of the present application provides a self-test device for a chip, wherein the self-test device is located in the chip, and the chip includes a read-only memory (ROM) and an internal test circuit. The self-test device of the chip includes:

[0020] The reading module is used to read the reading value corresponding to the storage unit to be tested in the ROM output by the self-test circuit. The self-test circuit is used to perform logical operations on the data stored in the storage unit to be tested.

[0021] The determination module is configured to determine the failed bit of the actual stored data of the memory cell under test based on the read value and the characteristic value corresponding to the memory cell under test. The characteristic value is the value obtained by calculating the inherent value corresponding to the memory cell under test according to the operation logic corresponding to the operation module.

[0022] The determination module is further configured to determine and output the coordinates of the failed bit in the chip based on the failed bit information, the position information of the storage unit to be tested in the ROM, and the position information of the ROM in the chip.

[0023] In an optional embodiment, the determination module is specifically configured to determine actual stored data of the memory cell under test based on the read value, the characteristic value, and the operation logic corresponding to the calculation module, and to compare the actual stored data with the inherent value corresponding to the memory cell under test to determine the failed bit of the actual stored data.

[0024] In an optional implementation, the determination module is further configured to determine and output the fail bit information corresponding to the memory cell to be tested based on the fail bit information and the inherent value corresponding to the memory cell to be tested.

[0025] In an optional implementation, the operation logic corresponding to the self-test circuit is: performing a bitwise AND operation with preset data.

[0026] In an optional embodiment, the operation logic corresponding to the self-test circuit is: compressing the values ​​corresponding to all storage cells between the starting storage cell and the storage cell to be tested of the ROM.

[0027] In a fourth aspect, embodiments of the present application provide a chip testing device comprising a processor and a memory. The processor is coupled to the memory, and the memory is configured to store computer instructions, which are loaded and executed by the processor to enable the chip testing device to implement any of the methods provided in the first aspect.

[0028] In a fifth aspect, an embodiment of the present application provides a chip comprising: a processor and an interface circuit; the interface circuit is used to receive code instructions and transmit them to the processor; and the processor is used to run the code instructions to execute any one of the methods provided in the first aspect.

[0029] In a sixth aspect, an embodiment of the present application provides a computer-readable storage medium, which stores at least one computer program instruction, and the computer program instruction is loaded and executed by a processor to implement any one of the methods provided in the first aspect above.

[0030] In a seventh aspect, an embodiment of the present application provides a computer program product, comprising computer execution instructions, which, when the computer execution instructions are run on a computer, enable the computer to execute any one of the methods provided in the first aspect.

[0031] The technical effects brought about by any implementation method in the second to seventh aspects can refer to the technical effects brought about by the corresponding implementation method in the first aspect, and will not be repeated here.

[0032] In an embodiment of the present application, an internal test circuit for ROM is integrated into the chip, wherein the internal test circuit is used to read the ROM and can calculate the stored data in the ROM before outputting it. When performing fault analysis on the ROM, the internal test program first determines the memory cell to be tested based on the memory cell address, then reads the memory cell to be tested through the internal test circuit to obtain the read value corresponding to the memory cell to be tested. By comparing the read value with the characteristic value of the memory cell to be tested, the failure bit of the actual stored data of the memory cell to be tested can be determined. Among them, reading the ROM through the internal test circuit can ensure the security and confidentiality of the stored data in the ROM. The internal test program can quickly and accurately locate storage faults in the ROM by comparing the read value and characteristic value of the memory cell to be tested. In addition, the internal test circuit can access each ROM memory cell in sequence according to the memory cell address, thus achieving comprehensive access detection of the ROM. At the same time, the internal test process steps are simple, thereby further improving the efficiency of ROM fault diagnosis. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 A schematic diagram of the structure of a BIST circuit provided in an embodiment of the present application;

[0034] Figure 2 A schematic flow chart of a chip internal testing method provided in an embodiment of the present application;

[0035] Figure 3 A schematic structural diagram of a compression circuit provided in an embodiment of the present application;

[0036] Figure 4 A schematic diagram of the structure of a chip provided in an embodiment of the present application;

[0037] Figure 5 A schematic structural diagram of a chip self-test device provided in an embodiment of the present application;

[0038] Figure 6 A schematic structural diagram of a chip testing device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0039] The present invention provides a chip internal test method, chip, and related equipment. By integrating an internal test circuit for ROM within the chip, the chip automatically diagnoses the storage status of the on-chip ROM. The integrated internal test circuit ensures that all ROMs within the chip are fully accessed and tested. Furthermore, the internal test process based on the internal test circuit is concise and can efficiently and accurately determine the storage status of the ROM.

[0040] In the description of this application, unless otherwise specified, " / " indicates that the objects associated before and after are in an "or" relationship, for example, A / B can represent A or B; "and / or" in this application is merely a description of the association relationship of associated objects, indicating that three relationships may exist, for example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural.

[0041] In the description of this application, unless otherwise specified, "plurality" means two or more than two. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can mean: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or plural.

[0042] In addition, to facilitate the clear description of the technical solutions of the embodiments of the present application, in the embodiments of the present application, the words "first" and "second" are used to distinguish between identical or similar items with substantially the same functions and effects. Those skilled in the art will understand that the words "first" and "second" do not limit the quantity or execution order, and the words "first" and "second" do not necessarily mean different.

[0043] In the embodiments of this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of this application should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner to facilitate understanding.

[0044] It will be understood that the “embodiment” mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, the various embodiments throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It will be understood that in the various embodiments of the present application, the size of the sequence number of each process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiment of the present application.

[0045] It is understood that some optional features in the embodiments of the present application may, in certain scenarios, be implemented independently of other features, such as the solution on which they are currently based, to solve corresponding technical problems and achieve corresponding effects. They may also be combined with other features in certain scenarios as needed. Accordingly, the devices provided in the embodiments of the present application may also implement these features or functions accordingly, which will not be described in detail here.

[0046] In this application, unless otherwise specified, the same or similar parts between the various embodiments can be referenced to each other. In this application, unless otherwise specified and there is no logical conflict between the various embodiments, the terms and / or descriptions between different embodiments are consistent and can be referenced to each other. Different embodiments can be combined to form new embodiments based on their inherent logical relationships. The following implementation methods of this application do not constitute a limitation on the scope of protection of this application.

[0047] To facilitate understanding of the technical solutions of the embodiments of the present application, a brief introduction to the relevant technologies of the embodiments of the present application is given below:

[0048] Current SoC chips contain a large amount of embedded memory, primarily static random access memory (SRAM) and read-only memory (ROM). However, since embedded memory cannot be directly accessed through chip pins, it cannot be tested using third-party automated test equipment (ATE). Testing embedded memory using the chip's embedded CPU not only complicates programming the test algorithm and reduces test efficiency, but also fails to ensure that the embedded CPU can access every embedded memory, making comprehensive testing of the chip's embedded memory difficult. Therefore, a self-test solution is needed to enable comprehensive, efficient, and accurate testing of embedded memory within a chip.

[0049] ROM operates in a non-destructive read mode. Data stored in ROM is typically written before the ROM is packaged on the chip. Once written, data is fixed and can only be read out and cannot be modified. Therefore, ROM is also called fixed memory, and the data it stores is very stable. Furthermore, ROM has a relatively simple structure and is easy to use. Therefore, ROM in chips is usually used to store various fixed chip programs and chip data. Therefore, the data stored in ROM is generally subject to security and confidentiality requirements.

[0050] Existing chips have testing and diagnostic solutions for SRAM, but for ROM, testing methods generally only confirm whether a memory fault has occurred, without a diagnostic solution for a faulty ROM. Diagnosing specific ROM memory faults is crucial for preventing them from spreading and for timely repair. Therefore, establishing a ROM-specific testing and diagnostic process is essential. This process can pinpoint ROM design or process issues, which is crucial for improving chip yield.

[0051] Based on this, the embodiments of the present application provide a chip internal test method, chip, and related equipment. The embodiments of the present application integrate an internal test circuit for ROM within the chip and provide an internal test process based on the internal test circuit. The on-chip ROM can be automatically tested based on the internal test process, and ROM storage faults can be quickly and accurately located. At the same time, it can also ensure that all ROMs within the chip are fully tested. The solution provided by the embodiments of the present application is described in detail below:

[0052] Before introducing the internal test method of the chip provided in the embodiment of the present application, the internal test circuit for ROM provided in the embodiment of the present application is first introduced. In the embodiment of the present application, the internal test circuit for ROM is designed during the chip development phase and integrated into the chip. Among them, the internal test circuit is a memory built-in self-test (BIST) circuit. The BIST circuit can be composed of two parts, including a controller and a memory access interface (collar interface). Figure 1 A schematic diagram of the structure of a BIST circuit provided in an embodiment of the present application is shown in FIG. Figure 1 As shown in the figure, the function of the controller is to generate test stimuli and detect corresponding results. Exemplarily, the controller consists of a state machine, a data reading module, an address generation module and other parts. Among them, the state machine is used to control the reading of the memory and needs to output the corresponding address and read operation and other stimulus signals according to the state. The data reading module is used to read the memory, and the address generation module is used to generate the address of the storage unit to be read. The collar interface is used to adapt the memory and can realize functions such as data comparison and fault analysis. Among them, the controller of the MBIST circuit is a synchronous circuit, and the clock during the memory test needs to be the same as the clock of the controller.

[0053] As you can understand, by adding a BIST circuit to the chip, all ROM-specific test algorithms can be implemented. Furthermore, to reduce test time and improve ROM test efficiency, the BIST circuit can utilize the chip's internal at-speed clock. Furthermore, the BIST circuit can perform comprehensive ROM testing and accurately diagnose the location of ROM memory faults. Compared to using external test equipment to test on-chip ROM, it also eliminates the need for numerous signal paths, significantly improving ROM test efficiency.

[0054] Based on the newly integrated internal test circuit for ROM in the chip, the embodiment of the present application provides a set of self-test processes for the ROM in the chip. Figure 2 A schematic diagram of a chip internal testing method provided in an embodiment of the present application is shown in FIG. Figure 2 As shown, the method includes the following steps:

[0055] 201. Read the memory cell to be tested in the ROM through the internal test circuit to obtain a read value corresponding to the memory cell to be tested.

[0056] The internal test circuit is used to perform logical operations on the data stored in the memory cell under test. Specifically, the data stored in the memory cell under test is input into the internal test circuit, and the internal test circuit outputs the calculated value obtained by performing logical operations on the actual stored data in the memory cell under test. This is the read value corresponding to the memory cell under test. The following briefly explains the internal test circuit's operational logic:

[0057] (1) The operation logic of the internal test circuit can be: performing a bitwise AND operation with the preset data.

[0058] The internal test circuit includes multiple AND gate devices. For example, assuming the data stored in the memory cell to be tested has 8 bits, the output result of the internal test circuit is the bitwise AND result of the 8-bit data and a preset 8-bit number. For example, if the actual stored data of the memory cell to be tested is "01011011" and the preset data is "11110000", then the read value after reading through the internal test circuit is "01010000". For another example, if the preset data is "10101100", then the read value after reading through the internal test circuit is "00001000".

[0059] (2) The operation logic of the internal test circuit may be: compressing the values ​​corresponding to all the memory cells between the starting memory cell of the ROM and the memory cell to be tested.

[0060] The internal test circuit can be a compression circuit that can compress the values ​​corresponding to all storage cells between the starting storage cell of the ROM and the storage cell to be tested. For example, Figure 2FIG. 1 is a schematic diagram showing the structure of a compression circuit. Figure 2 As shown, the Q terminal is used to sequentially input the stored data of the ROM memory cells, while the X terminal can output the compressed values ​​of each level of compression. Finally, the device corresponding to the memory cell under test outputs the compressed values ​​of the values ​​corresponding to all memory cells between the starting memory cell and the memory cell under test. For example, assuming the address of the memory cell under test is 5, the compression circuit outputs the compressed values ​​of the six stored data of the six memory cells between addresses 0 and 5.

[0061] As will be appreciated, the internal test circuit's operational logic may also include XOR operations, XNOR operations, and the like, which will not be detailed here. The internal test circuit outputs the calculated value of the actual stored data in the memory cell under test, ensuring that the actual stored data in the ROM is not disclosed externally, thereby ensuring the security and confidentiality of the ROM data storage.

[0062] For example, during the test process, the internal test circuit generates only one test stimulus at a time. After executing a self-test process, the address of the ROM corresponding to the read operation is automatically incremented, and then the internal test circuit tests the next memory cell in turn. In this way, a comprehensive test of the ROM can be achieved.

[0063] 202. Determine a failed bit of actual storage data of the memory cell to be tested according to the read value and a characteristic value corresponding to the memory cell to be tested.

[0064] The characteristic value is the value obtained by calculating the inherent value corresponding to the memory cell to be tested based on the operation logic corresponding to the internal test circuit. It can be understood that the internal test circuit is designed for the ROM during the chip design phase, and the inherent value of the ROM is also written in advance before the chip is packaged. Therefore, during the chip development phase, a characteristic value can be determined for each memory cell of the ROM. In this way, the internal test circuit does not need to know the inherent value; it only needs to compare the read value and the characteristic value to locate the failed bit of the actual storage data of the memory cell to be tested. In this way, the inherent value of the memory cell in the ROM can be prevented from being leaked, thereby protecting the data security of the ROM.

[0065] That is, the characteristic value corresponding to the memory cell under test is a calculated value obtained by performing a logical calculation on the inherent value corresponding to the memory cell under test, and the calculation logic thereof is consistent with the calculation logic corresponding to the internal test circuit. Under the consistent calculation logic, if the calculated value of the actual stored data of the memory cell under test (i.e., the read value) is consistent with the calculated value of the inherent value of the memory cell under test (i.e., the characteristic value), then the actual stored data of the memory cell under test is the inherent value, and the memory cell under test has no storage fault. If they are inconsistent, then it indicates that the memory cell under test has a storage fault.

[0066] For example, in an internal test program, the internal test program can infer the actual storage data of the memory cell to be tested based on the read value, characteristic value, and operation logic corresponding to the internal test circuit of the memory cell to be tested, and then compare the actual storage data with the inherent value corresponding to the memory cell to be tested included in the internal test program to determine the failure bit of the actual storage data. In an embodiment of the present application, the inherent value of the ROM is not disclosed to the outside world, but is written into the internal test program corresponding to the internal test circuit, so as to ensure the security and confidentiality of the ROM storage data. The internal test program can quickly and accurately locate ROM storage faults by comparing the actual storage data of the memory cell to be tested with the inherent value of the memory cell to be tested.

[0067] For example, after determining the failed bit of the actual stored data of the memory cell under test, the internal test program also needs to compare the failed bit with the inherent value corresponding to the memory cell under test and output the failed bit information corresponding to the failed bit, such as the transition of a logic "0" on a certain bit to "1".

[0068] 203. Determine and output the coordinates of the failed bit in the chip based on the failed bit information, the location information of the memory cell to be tested in the ROM, and the location information of the ROM in the chip.

[0069] Finally, the coordinates of the failed bit in the chip are determined based on the failed bit information, the location information of the memory cell to be tested in the ROM, and the location information of the ROM in the chip, and the coordinates of the fault are output.

[0070] In an embodiment of the present application, an internal test circuit for ROM is integrated into the chip, wherein the internal test circuit is used to read the ROM and can calculate the storage data in the ROM before outputting it. When testing the ROM, the internal test program first determines the storage cell to be tested based on the storage cell address, and then reads the storage cell to be tested through the internal test circuit to obtain the read value corresponding to the storage cell to be tested. By comparing the read value with the characteristic value of the storage cell to be tested, the failure bit of the actual storage data of the storage cell to be tested can be determined. Among them, reading the ROM through the internal test circuit can ensure the security and confidentiality of the storage data in the ROM. By comparing the read value and the characteristic value of the storage cell to be tested, storage faults in the ROM can be quickly and accurately located. In addition, the internal test circuit can access each ROM storage cell in sequence according to the storage cell address, which can achieve a comprehensive test of the ROM. At the same time, the internal test process steps are simple, so that storage faults in the ROM can be diagnosed more efficiently.

[0071] Based on the above description, Figure 4 This is a schematic diagram of the structure of a chip provided in an embodiment of the present application. Figure 4As shown, the chip includes a read-only memory ROM 401, an internal test circuit 402 and an analysis module 403. The internal test circuit 402 includes a control module 4021 and an operation module 4022.

[0072] The control module 4021 is used to read the read value corresponding to the memory cell to be tested in the ROM output by the operation module 4022. The operation module 4022 is used to perform logical operations on the real storage data of the memory cell to be tested.

[0073] The analysis module 403 is configured to determine the failed bit of the actual stored data of the memory cell under test based on the read value and the characteristic value corresponding to the memory cell under test. The characteristic value is a value obtained by calculating the inherent value corresponding to the memory cell under test according to the operation logic corresponding to the operation module.

[0074] The analysis module 403 is further configured to determine and output the coordinates of the failed bit in the chip based on the failed bit information, the location information of the memory cell to be tested in the ROM, and the location information of the ROM in the chip.

[0075] In an optional embodiment, the analysis module 403 is configured to determine the actual stored data of the memory cell under test based on the read value, the characteristic value, and the operation logic corresponding to the calculation module. The analysis module 403 compares the actual stored data with the inherent value corresponding to the memory cell under test to determine the failed bit of the actual stored data.

[0076] In an optional implementation, the analysis module 403 is further configured to determine and output the fail bit information corresponding to the memory cell to be tested according to the fail bit information and the inherent value corresponding to the memory cell to be tested.

[0077] In an optional implementation, the operation logic corresponding to the operation module is: performing a bitwise AND operation with preset data.

[0078] In an optional implementation, the operation logic corresponding to the operation module is: compressing the values ​​corresponding to all storage cells between the starting storage cell and the storage cell to be tested of the ROM.

[0079] The chip provided in the embodiments of the present application integrates an internal test circuit for ROM, wherein the internal test circuit is used to read the ROM and can calculate the stored data in the ROM before outputting it. When testing the ROM, the control module of the internal test circuit first determines the memory cell to be tested based on the memory cell address. Then, the calculation module of the internal test circuit reads the memory cell to be tested and obtains the read value corresponding to the memory cell to be tested. The analysis module then compares the read value with the characteristic value of the memory cell to be tested to determine the failed bit of the actual stored data in the memory cell to be tested. Reading the ROM through the internal test circuit ensures the security and confidentiality of the stored data in the ROM. The analysis module compares the read value and characteristic value of the memory cell to be tested to quickly and accurately locate storage faults in the ROM. The internal test circuit can access each ROM memory cell sequentially based on the memory cell address, thereby achieving a comprehensive test of the ROM. At the same time, the internal test process is simple, making it possible to more efficiently diagnose ROM storage faults.

[0080] Based on the above description, an embodiment of the present application further provides a schematic structural diagram of a self-test device for a chip. In an embodiment of the present application, the self-test device can be divided into functional modules according to the above method example. For example, each functional module can be divided corresponding to each function, or two or more functions can be integrated into one processing module. The above-mentioned integrated module can be implemented in the form of hardware or in the form of software functional modules. It should be noted that the division of modules in the embodiment of the present invention is schematic and is only a logical function division. In actual implementation, there may be other division methods.

[0081] In the case of dividing each functional module into corresponding functional modules, Figure 5 FIG. 1 is a schematic diagram showing a possible structure of the self-test device of the chip involved in the above embodiment. Figure 5 As shown, the self-test device is located in the chip, and the chip includes a read-only memory ROM and an internal test circuit. The self-test device of the chip includes:

[0082] The reading module 501 is used to read the read value corresponding to the memory cell to be tested in the ROM output by the self-test circuit. The self-test circuit is used to perform logical operations on the data stored in the memory cell to be tested.

[0083] The determination module 502 is configured to determine the failed bit of the actual stored data of the memory cell under test based on the read value and the characteristic value corresponding to the memory cell under test. The characteristic value is a value obtained by calculating the inherent value corresponding to the memory cell under test according to the operation logic corresponding to the operation module.

[0084] The determination module 502 is further configured to determine and output the coordinates of the failed bit in the chip according to the failed bit information, the location information of the memory cell to be tested in the ROM, and the location information of the ROM in the chip.

[0085] In an optional embodiment, the determination module 502 is specifically configured to determine the actual stored data of the memory cell under test based on the read value, the characteristic value, and the operation logic corresponding to the calculation module. The actual stored data is compared with the inherent value corresponding to the memory cell under test to determine the failed bit of the actual stored data.

[0086] In an optional implementation, the determination module 502 is further configured to determine and output the fail bit information corresponding to the memory cell to be tested according to the fail bit information and the inherent value corresponding to the memory cell to be tested.

[0087] In an optional implementation, the operation logic corresponding to the self-test circuit is: performing a bitwise AND operation with preset data.

[0088] In an optional embodiment, the operation logic corresponding to the self-test circuit is: compressing the values ​​corresponding to all storage cells between the starting storage cell and the storage cell to be tested of the ROM.

[0089] Figure 6 18 is a schematic structural diagram of a chip testing device provided in an embodiment of the present application. The chip testing device 1800 may include one or more central processing units (CPU) 1801 and a memory 1805. The memory 1805 stores one or more applications or data.

[0090] Memory 1805 may be volatile or persistent storage. The program stored in memory 1805 may include one or more modules, each of which may include a series of instruction operations on the management server. Furthermore, the central processing unit 1801 may be configured to communicate with memory 1805 and execute the series of instruction operations in memory 1805 on the bus controller 1800.

[0091] The central processing unit 1801 is used to execute the computer program in the memory 1805 so that the chip testing device 1800 is used to perform the above Figure 2 The steps in the embodiment shown are as follows. For specific implementation, please refer to Figure 2 The steps performed in the illustrated embodiment will not be repeated here.

[0092] The chip testing device 1800 may also include one or more power supplies 1802, one or more wired or wireless network interfaces 1803, one or more input and output interfaces 1804, and / or one or more operating systems, such as Windows Server™, Mac OS X™, Unix™, Linux™, FreeBSD™, etc.

[0093] The embodiment of the present application further provides a computer-readable storage medium in which at least one computer program instruction is stored. The computer program instruction is loaded and executed by a processor to implement the above Figure 2 The chip self-test method executed in any one of the embodiments will not be described in detail here.

[0094] The embodiment of the present application also provides a computer program product, including computer execution instructions, which, when executed on a computer, causes the computer to execute the above Figure 2 The chip self-test method implemented in the embodiment.

[0095] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using a software program, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes (or functions) described in the embodiments of the present application are implemented. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website, computer, server or data center to another website, computer, server or data center via a wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) method. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that contains one or more media that can be integrated. The available medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a magnetic tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid state disk (SSD)). In the embodiment of the present application, the computer may include the aforementioned device.

[0096] Although the present application is described herein in conjunction with various embodiments, in the process of implementing the claimed application, those skilled in the art can understand and implement other changes to the disclosed embodiments by reviewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude multiple situations. A single processor or other unit can implement several functions listed in the claims. Certain measures are recorded in different dependent claims, but this does not mean that these measures cannot be combined to produce good results.

Claims

1. A chip internal testing method, characterized in that: The chip includes a read-only memory (ROM) and an internal test circuit, and the method includes: The internal test circuit reads the memory cell to be tested in the ROM to obtain a read value corresponding to the memory cell to be tested; the internal test circuit is used to perform a logical operation on the data stored in the memory cell to be tested; Determining a failed bit of actual stored data of the memory cell to be tested based on the read value and a characteristic value corresponding to the memory cell to be tested; wherein the characteristic value is a value obtained by calculating the inherent value corresponding to the memory cell to be tested according to the operation logic corresponding to the internal test circuit; The coordinates of the failed bit in the chip are determined and output according to the failed bit information, the position information of the storage unit to be tested in the ROM, and the position information of the ROM in the chip.

2. The method according to claim 1, characterized in that The determining, based on the read value and the characteristic value corresponding to the memory cell to be tested, a failed bit in the data stored in the memory cell to be tested, includes: determining the actual storage data of the memory cell to be tested according to the read value, the characteristic value and the operation logic corresponding to the internal test circuit; The actual stored data is compared with the inherent value corresponding to the memory cell to be tested to determine the failed bit of the actual stored data.

3. The method according to claim 2, characterized in that The method further comprises: According to the fail bit information and the inherent value corresponding to the memory cell to be tested, the fail bit information corresponding to the memory cell to be tested is determined and output.

4. The method according to any one of claims 1 to 3, characterized in that The operation logic corresponding to the internal test circuit is: Performs a bitwise AND operation with the preset data.

5. The method according to any one of claims 1 to 3, characterized in that The operation logic corresponding to the internal test circuit is: The values ​​corresponding to all storage cells between the starting storage cell of the ROM and the storage cell to be tested are compressed.

6. A chip, characterized in that: The chip includes a read-only memory (ROM), an internal test circuit, and an analysis module; wherein the internal test circuit includes a control module and an operation module; The control module is used to read the read value corresponding to the storage unit to be tested in the ROM output by the operation module; the operation module is used to perform logical operations on the actual storage data of the storage unit to be tested; The analysis module is configured to determine a failed bit of the actual stored data of the memory cell to be tested based on the read value and a characteristic value corresponding to the memory cell to be tested; wherein the characteristic value is a value obtained by calculating the inherent value corresponding to the memory cell to be tested according to the operation logic corresponding to the operation module; The analysis module is further configured to determine and output the coordinates of the failed bit in the chip based on the failed bit information, the location information of the storage unit to be tested in the ROM, and the location information of the ROM in the chip.

7. The chip according to claim 6, characterized in that The analysis module is specifically used to determine the actual storage data of the storage unit to be tested based on the read value, the characteristic value and the operation logic corresponding to the calculation module; compare the actual storage data with the inherent value corresponding to the storage unit to be tested, and determine the failure bit of the actual storage data.

8. The chip according to claim 7, characterized in that The analysis module is further configured to determine and output the fail bit information corresponding to the memory cell to be tested based on the fail bit information and the inherent value corresponding to the memory cell to be tested.

9. The chip according to any one of claims 6 to 8, characterized in that: The operation logic corresponding to the operation module is: Performs a bitwise AND operation with the preset data.

10. The method according to any one of claims 6 to 8, characterized in that The operation logic corresponding to the operation module is: The values ​​corresponding to all storage cells between the starting storage cell of the ROM and the storage cell to be tested are compressed.

11. A chip testing device, characterized in that: The chip testing device includes a processor and a memory; the processor is coupled to the memory; the memory is used to store computer instructions, and the computer instructions are loaded and executed by the processor to enable the chip testing device to implement the method according to any one of claims 1 to 5.

12. A computer-readable storage medium storing computer instructions, characterized in that: include: Computer instructions, wherein when the computer instructions are executed, the computer is caused to perform the method according to any one of claims 1 to 5.

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