Packaging chip

Abstract

The invention provides a packaging chip. The packaging chip comprises a top layer and an interposer which are arranged in a stacked mode. The top layer comprises a first organic layer and at least three top layer chips arranged at intervals, and the first organic layer wraps the peripheries of the top layer chips. The interposer comprises a second organic layer and an interposer chip, the second organic layer wraps the periphery of the interposer chip, the interposer chip comprises at least one first interposer chip, the first interposer chip is electrically connected with the at least one top chip, and the first interposer chip is electrically connected with the at least one top chip in the stacking direction of the top chip and the interposer layer. The first medium chip is arranged opposite to the at least three top chips. According to the packaging chip provided by the invention, the first intermediary chip is arranged opposite to the at least three top-layer chips, so that the silicon content of the intermediary layers and the silicon content of the top layers are balanced, the warping risk of the packaging chip is reduced, and the reliability and the electrical performance of the packaging chip are improved.

Description

Technical Field

[0001] The present application relates to the field of chip packaging technology, and specifically designs a packaged chip. Background Art

[0002] With the continuous development of integrated electronic technology, the requirements for chip performance are also increasing, such as enhanced functionality, reduced size, reduced energy consumption and cost, which has spawned a variety of packaging technologies, such as three-dimensional integrated circuit (3D IC) technology, 2.5DIC packaging technology, 2D IC packaging technology, etc.

[0003] At present, packaged chips usually include a stacked top layer and an intermediate layer. Multiple top chips (Top die) are encapsulated in the top layer. Multiple top chips can be electrically interconnected with each other through micro bumps and the redistribution layer (RDL) and copper pillars in the intermediate layer, as well as the electrical connection between the top chips and the substrate.

[0004] However, in current packaged chips, the top structure is prone to warping, thereby affecting the reliability and electrical performance of the packaged chip. Summary of the Invention

[0005] The present application provides a packaged chip, which reduces the risk of warping of the packaged chip by arranging a first intermediate chip to face at least three top chips, thereby improving the reliability and electrical performance of the packaged chip.

[0006] The present application provides a packaged chip, comprising a stacked top layer and an interposer layer. The top layer comprises a first organic layer and at least three spaced-apart top-layer chips, with the first organic layer surrounding the periphery of the top-layer chips. The interposer layer comprises a second organic layer and an interposer chip, with the second organic layer surrounding the periphery of the interposer chip. The interposer chip comprises at least one first interposer chip, each first interposer chip being electrically connected to at least one top-layer chip, and each first interposer chip being arranged opposite the at least three top-layer chips in the stacking direction of the top layer and the interposer layer.

[0007] In the present application, since a first intermediate chip is arranged opposite to at least three top chips in the stacking direction of the top layer and the intermediate layer, the area of ​​the first intermediate chip is larger and can span at least two chip gaps (die gaps), thereby increasing the silicon content in the intermediate layer, and then balancing the silicon content of the intermediate layer and the silicon content of the top layer, which is beneficial to balancing the stress of the intermediate layer and the top layer, so as to reduce or even eliminate the warpage of the packaged chip, enhance the strength of the part located between two adjacent top chips, and improve the reliability of the packaged chip.

[0008] In some possible implementations, the first intermediary chip is electrically connected to at least three top-level chips that are arranged opposite to each other.

[0009] In this implementation, the first interposer chip is electrically connected to at least three top-layer chips positioned opposite each other, supporting high-quality signal transmission between the at least three top-layer chips. Compared to a redistribution layer, the first interposer chip provides better electrical interconnection between the top-layer chips, thereby improving the electrical performance of the packaged chips. Furthermore, the facing arrangement shortens the connection distance between the first interposer chip and the top-layer chips, thereby enhancing signal transmission between the two.

[0010] In some possible implementations, the interposer further includes a pad group, the pad group being located between the top layer and the first interposer chip, with one side of the pad group electrically connected to the top layer chip, and the other side of the pad group electrically connected to the first interposer chip. The pad group includes a first region and a second region, wherein the second region surrounds or semi-surrounds the first region. The pad group includes a plurality of first pads located in the first region and a plurality of second pads located in the second region. The pads located in the second region are larger than the pads located in the first region.

[0011] In this implementation, the pad group is divided into zones, which facilitates different structural and / or functional designs for different areas of the pad group. Due to the large size of the first intermediary chip, the first intermediary chip requires higher placement accuracy. A mixed design of pads with multiple diameters (Combo CD) can improve the placement accuracy requirements of the first intermediary chip, thereby reducing the area of ​​the first intermediary chip and increasing the requirements for the placement machine, thereby improving the placement yield and efficiency of the first intermediary chip.

[0012] In some possible implementations, the distribution density of the first pads in the first region is greater than the distribution density of the second pads in the second region.

[0013] In this implementation, it is beneficial to improve the signal interconnection capability between the first pad in the first region and the first intermediary chip.

[0014] In some possible implementations, the first interposer chip includes a third region and a fourth region, where the fourth region surrounds or semi-surrounds the third region. The first interposer chip includes a plurality of third pads located in the third region and a plurality of fourth pads located in the fourth region. The third pads are soldered to the first pads, and the fourth pads are soldered to the second pads. The third pads have the same size as the fourth pads.

[0015] In this implementation, since the size of the second pad is larger than that of the first pad, the welding difficulty between the fourth pad and the second pad is less than that between the third pad and the first pad, which is beneficial to reducing the overall mounting difficulty of the first intermediate chip and the pad group.

[0016] In some possible implementations, a high-density interconnect signal is transmitted between the third pad and the first pad.

[0017] In this implementation, since the distribution density of the first pads in the first area can be greater than the distribution density of the second pads in the second area, the signal interconnection capability between the first intermediate signal and the pad group in the first area and the third area is stronger than the signal interconnection capability between the second area and the fourth area. Therefore, transmitting high-density interconnection signals between the third pad and the first pad is beneficial to improving the electrical performance of the packaged chip.

[0018] In some possible implementations, a low-density interconnection signal is transmitted between the fourth pad and the second pad to assist in electrical interconnection between the first interposer chip and the at least three chips.

[0019] In some other possible implementations, the fourth pad and the second pad are used to transmit power signals to form a power supply area, which is beneficial to the integrity of electrical signals between at least three top-layer chips electrically connected to the first intermediate chip.

[0020] In some other possible implementations, the fourth pad and the second pad are grounded, which helps to improve the stability of signal transmission between at least three top-layer chips electrically connected to the first intermediate chip.

[0021] In some possible implementations, the at least three top-level chips electrically connected to the same first interposer chip include chips of at least two types.

[0022] In this implementation, at least two types of chips are electrically connected via the first intermediate chip, which is beneficial for integrating multiple functions of the packaged chip to improve the electrical performance of the packaged chip.

[0023] In some possible implementations, the interposer chip further includes a second interposer chip electrically connected to one of the at least three top-layer chips. Along the stacking direction of the top layer and the interposer layer, an orthographic projection of the second interposer chip on the top layer falls within the top-layer chip electrically connected to the second interposer chip.

[0024] In this implementation, the second intermediate chip does not span any die gap and can be used to encapsulate passive or active devices to improve the electrical performance of the top chip electrically connected to the second intermediate chip, for example, to improve the ability of the top chip electrically connected to the second intermediate chip to filter high-frequency noise.

[0025] There may be multiple second intermediary chips, and each second intermediary chip is electrically connected to a top chip.

[0026] In this implementation, by setting up multiple second intermediate chips, it is not only beneficial to balance the silicon content of the intermediate layer and the top layer to reduce the warping risk of the packaged chip, but also beneficial to improve the electrical performance of the top layer chip with the second intermediate chip, thereby improving the electrical performance of the packaged chip.

[0027] The plurality of second interposer chips may be electrically connected to the same top chip, and along the stacking direction of the top layer and the interposer layer, the orthographic projections of the plurality of second interposer chips on the top layer fall within the same top chip.

[0028] In this implementation, multiple second intermediate chips can be the same type of sealing devices or different types of sealing devices, so as to further improve the electrical performance of the top chip electrically connected to the multiple second intermediate chips, realize the collection of multiple functions, and help improve the electrical performance of the packaged chip.

[0029] In some possible implementations, along the stacking direction of the top layer and the interposer layer, a ratio of an area of ​​an orthographic projection of the interposer chip on the top layer to an area of ​​the top layer is in a range of 30% to 80%.

[0030] In this implementation, by designing the range of the ratio of the area of ​​the positive projection of the intermediate chip on the top layer to the area of ​​the top layer, it is beneficial to balance the silicon content in the top layer and the silicon content in the intermediate layer, thereby balancing the stress of the top layer and the intermediate layer, and further helping to reduce the risk of warping of the packaged chip.

[0031] In some possible implementations, the interposer further includes a redistribution layer (RDL), which is disposed between the top layer and the interposer. The RDL includes an electrical connection layer and an insulating layer encapsulating the electrical connection layer. The top chip is electrically connected to the first interposer chip via the electrical connection layer. Part of the at least three top chips are electrically connected via the electrical connection layer.

[0032] In this implementation, the redistribution layer can not only electrically connect the top chip through the electrical connection layer to achieve horizontal electrical interconnection, but also electrically connect the first intermediate chip and the top chip through the electrical connection layer to achieve vertical electrical interconnection, which is beneficial to improving the electrical performance of the packaged chip.

[0033] In some possible implementations, the interposer further includes a plurality of copper pillars, some of which are electrically connected to the electrical connection layer, and others of which are embedded in the first interposer chip. The packaged chip further includes a substrate, which is disposed on a side of the interposer facing away from the top layer and is soldered to ends of the plurality of copper pillars facing away from the top layer.

[0034] In this implementation, by embedding copper pillars in the first intermediate chip, the first intermediate chip can be directly electrically connected to the substrate through the copper pillars, thereby improving the vertical interconnection performance of at least three top chips and thus improving the electrical performance of the packaged chip.

[0035] In some possible implementations, a surface of the first organic layer facing away from the interposer is provided with a groove, the groove being provided along at least a portion of a periphery of the top chip. The top layer further includes a third organic layer, the third organic layer being filled in the groove.

[0036] In this implementation, a half-cut process can be used to cut at least a portion of the periphery of the top chip, thereby forming a groove in the first organic layer corresponding to at least a portion of the periphery of the top chip. This releases stress generated by curing shrinkage during the formation of the first organic layer, thereby reducing the risk of warping and improving the reliability of the packaged chip. By filling the groove with a third organic layer, the bonding strength of the periphery of the top chip can be improved, thereby improving the reliability of the packaged chip.

[0037] In some possible implementations, the third organic layer is made of a different material than the first organic layer.

[0038] In this implementation, by designing the third organic layer to have a different material from the first organic layer, the stress direction generated by the curing shrinkage during the formation of the third organic layer is different from that of the first organic layer, thereby avoiding stress concentration at the periphery of the top chip, reducing micro-area stress, improving bonding strength, and thereby reducing the risk of warping of the packaged chip and improving packaging reliability.

[0039] In some possible implementations, the groove is arranged at least between two adjacent top chips.

[0040] In this implementation, by setting a groove between two adjacent top-level chips, it is helpful to release the stress between the two adjacent top-level chips, thereby reducing the warping risk of the area between the two adjacent top-level chips, and further improving the structural stability of the area between the two adjacent top-level chips, thereby improving the reliability of the packaged chip.

[0041] In some possible implementations, the top chip includes a main control chip and other chips, and the other chips surround or semi-surround the main control chip. At least one first intermediate chip electrically connects the main control chip and the other chips located on one side of the main control chip.

[0042] In this implementation, placing the main control chip near the center of the top layer shortens the electrical connection distance between the main control chip and each other chip, improving the efficiency of the electrical connection between the main control chip and other chips. Electrically connecting the main control chip to other chips located on one side of the main control chip through at least one first intermediary chip strengthens the signal interconnection between the main control chip and other chips, facilitating the main control chip's coordination with other chips and improving the efficiency of the packaged chips.

[0043] In some possible implementations, at least one first intermediate chip is electrically connected to other chips located on both sides of the main control chip.

[0044] In this implementation, the first intermediate chip bridges the other chips on both sides of the main control chip, which is beneficial to strengthening the signal interconnection capability between the other chips on both sides of the main control chip, thereby further improving the efficiency of the main control chip in coordinating the work of other chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 is a schematic diagram of a top view of the packaged chip provided in some embodiments of the present application;

[0046] Figure 2 yes Figure 1 The packaged chip shown is a schematic cross-sectional structure diagram taken along line AA in some embodiments;

[0047] Figure 3A is a schematic top view of the packaged chip provided in the present application in some other embodiments;

[0048] Figure 3B is a schematic top view of the packaged chip provided in the present application in some further embodiments;

[0049] Figure 4A yes Figure 2 A schematic diagram showing the distribution of pad groups of an interposer in a packaged chip in some embodiments;

[0050] Figure 4B yes Figure 2 Schematic diagram of the distribution of pad groups of the interposer in the packaged chip in other embodiments;

[0051] Figure 4C yes Figure 2 Schematic diagram of the distribution of pad groups of the interposer in the packaged chip in some further embodiments;

[0052] Figure 5 yes Figure 2 A schematic diagram showing the distribution of pads of the first interposer chip in the packaged chip in some embodiments;

[0053] Figure 6This is a comparative example of the pad distribution of the pad group in the prior art;

[0054] Figure 7 yes Figure 4A Examples and Figure 6 Comparative example: a schematic diagram showing a simulation comparison of mounting with the first intermediate chip at different mounting accuracies;

[0055] Figure 8A yes Figure 1 The structure diagram of the packaged chip shown in some embodiments after the half-cut process is adopted;

[0056] Figure 8B yes Figure 8A The schematic diagram of the cross-sectional structure of the packaged chip shown is taken along line BB in some embodiments;

[0057] Figure 9 yes Figure 8A Schematic diagram of the process of using half-cutting process in part of the packaged chip;

[0058] Figure 10A yes Figure 1 The schematic cross-sectional structure diagram of the packaged chip taken along line AA in other embodiments is shown;

[0059] Figure 10B yes Figure 1 The packaged chip is shown as a schematic cross-sectional structure diagram along line AA in some other embodiments;

[0060] Figure 11 is a schematic top view of the packaged chip provided in the present application in some further embodiments;

[0061] Figure 12 yes Figure 11 The packaged chip shown is a schematic cross-sectional structure diagram of some embodiments when cut along line CC. DETAILED DESCRIPTION

[0062] The embodiments of the present application are described below in conjunction with the drawings in the embodiments of the present application.

[0063] In the description of the embodiments of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "installed" and "connected" should be understood in a broad sense. For example, "connected" can mean detachably connected or non-detachably connected; it can mean directly connected or indirectly connected through an intermediary. "Multiple" means at least two.

[0064] The directional terms mentioned in the embodiments of the present application, such as "upper", "lower", "inside", "outside", "top", "bottom", "side", etc., are only references to the directions in the drawings. Therefore, the directional terms used are for better and clearer explanation and understanding of the embodiments of the present application, rather than indicating or implying that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the embodiments of the present application.

[0065] In the embodiments of the present application, the limitations of the relative position relationship mentioned, such as parallel, perpendicular, aligned, etc., are all for the current state of the art, rather than absolutely strict limitations, and a small amount of deviation is allowed, and it is possible to be approximately parallel, approximately perpendicular, approximately aligned, etc. For example, A and B are parallel, which means that A and B are parallel or approximately parallel, and the angle between A and B can be between 0 degrees and 10 degrees. For example, A and B are perpendicular, which means that A and B are perpendicular or approximately perpendicular, and the angle between A and B can be between 80 degrees and 100 degrees.

[0066] In the embodiments of this application, the terms "first," "second," "third," and "fourth" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature specified as "first," "second," "third," or "fourth" may explicitly or implicitly include one or more of the features.

[0067] Please refer to Figure 1 and Figure 2 , Figure 1 is a schematic top view of the packaged chip 10 provided in the present application in some embodiments; Figure 2 yes Figure 1 The packaged chip 10 shown is a schematic cross-sectional structural diagram taken along line AA in some embodiments.

[0068] In some embodiments, the packaged chip 10 may include a top layer 1, an interposer 2, and a substrate 3 stacked in sequence. The interposer 2 is used to electrically connect the top layer 1 and the substrate 3 to achieve electrical interconnection and information exchange between the top layer 1 and the substrate 3.

[0069] Exemplarily, the top layer 1 may include a first organic layer 11 and at least three top chips (Topdie) 12 arranged at intervals, and the first organic layer 11 is arranged to wrap around the periphery of the top chip 12 .

[0070] It should be noted that the first organic layer 11 wraps the periphery of the top chip 12, which means that the first organic layer 11 wraps the periphery of the top chip 12 in a plane perpendicular to the stacking direction of the top layer 1 and the organic layer, and the top surface of the top chip 12 facing away from the intermediate layer 2 can be exposed in the first organic layer 11.

[0071] The first organic layer 11 may be a molding compound to provide structural support and chemical protection for the top chip 12. The molding compound may include silicon powder, resin, additives, and the like.

[0072] The top chip 12 may include a chip body 12a, pins 12b, and a metal microstructure 12c. The pins 12b may be electrically connected to the interposer 2 via the metal microstructure 12c to achieve electrical interconnection between the chip body 12a and the interposer 2. For example, the metal microstructure 12c may be a micro bump.

[0073] The top layer 1 may further include an underfill 13 , and the underfill 13 may wrap the metal microstructure 12 c to protect the metal microstructure 12 c.

[0074] The bottom filling material 13 and the first organic layer 11 can be prepared in an integrally formed manner to improve the structural stability of the top layer 1 .

[0075] For example, the interposer 2 may include a redistribution layer 21, an interposer chip 22, a second organic layer 23, and a plurality of copper pillars 24. In this case, the interposer 2 is also referred to as a heterogeneous interposer 2 because it includes materials other than silicon.

[0076] The redistribution layer (RDL) 21 can be located on top of the interposer 2 and extend along the arrangement direction of the at least three top chips 12. The RDL 21 is used to electrically connect the top chips 12, enabling interconnection between the at least three top chips 12, that is, achieving horizontal interconnection.

[0077] The intermediate chip 22 can be electrically connected to at least one top chip 12. The intermediate chip 22 can be made of one or more materials selected from silicon, glass, ceramic, organic matter, and metal. Figure 1 In the embodiment, since the interposer chip 22 is located below the top chip 12 , the interposer chip 22 is represented by a dotted frame. In subsequent drawings, the interposer chip 22 located below the top chip 12 is indicated by a dotted frame.

[0078] The second organic layer 23 is disposed around the periphery of the interposer chip 22. It should be noted that the bottom surface of the interposer chip 22 facing away from the top layer 1 may be exposed on the interposer layer 2.

[0079] The second organic layer 23 may be a molding compound to provide structural support and chemical protection for the interposer layer 2. The molding compound may include silicon powder, resin, additives, etc. It should be noted that the molding compound of the second organic layer 23 may be the same as or different from the molding compound of the first organic layer 11.

[0080] The copper pillars 24 can be partially embedded in the second organic layer 23 and partially exposed on the side of the interposer 2 facing away from the top layer 1. The portion of the copper pillars 24 embedded in the second organic layer 23 can be electrically connected to the redistribution layer 21, and the portion of the copper pillars 24 exposed on the interposer 2 can be soldered to the substrate 3 via micro-solder joints 25, thereby achieving electrical connection between the redistribution layer 21 and the substrate 3, and further realizing vertical interconnection between the top chip 12 and the substrate 3.

[0081] In some embodiments, the interposer chip 22 may include at least one first interposer chip 221. Each first interposer chip 221 may be electrically connected to at least one top chip 12. In the stacking direction of the top layer 1 and the interposer layer 2, each first interposer chip 221 is disposed opposite to at least three top chips 12.

[0082] It should be noted that the term "opposite arrangement" means that, in the stacking direction of the top layer 1 and the interposer 2, the orthographic projection of the first interposer chip 221 on the top layer 1 at least partially falls within the top layer chip 12. In other words, one first interposer chip 221 is arranged opposite at least three top layer chips 12, i.e., in the stacking direction of the top layer 1 and the interposer 2, the orthographic projection of one first interposer chip 221 on the top layer 1 at least partially falls within the at least three top layer chips 12.

[0083] In this embodiment, since a first intermediate chip 221 is arranged opposite to at least three top chips 12 in the stacking direction of the top layer 1 and the intermediate layer 2, the area of ​​the first intermediate chip 221 is larger and can span at least two chip gaps (die gaps), thereby increasing the silicon content in the intermediate layer 2, and further balancing the silicon content of the intermediate layer 2 with the silicon content of the top layer 1, which is beneficial to balancing the stress of the intermediate layer 2 and the top layer 1, so as to reduce or even eliminate the warpage (WPG) of the packaged chip 10, enhance the strength of the portion located between two adjacent top chips 12, and improve the reliability of the packaged chip 10.

[0084] In the stacking direction of the top layer 1 and the interposer 2 , the orthographic projection of the first interposer chip 221 on the top layer 1 may be in a strip shape, a T shape, a cross shape, or the like.

[0085] Exemplarily, the first interposer chip 221 may be electrically connected to at least three top chips 12 .

[0086] In this embodiment, the first intermediate chip 221 is electrically connected to at least three top-level chips 12 arranged opposite to each other, and can provide support for high-quality signal transmission between at least three top-level chips 12. Compared with the redistribution layer 21, the first intermediate chip 221 can provide better electrical interconnection between the top-level chips 12 to improve the electrical performance of the packaged chip 10.

[0087] The first intermediary chip 221 can be electrically connected to at least three opposite top chips 12 to shorten the connection distance between the first intermediary chip 221 and the top chip 12 , thereby improving the signal transmission effect between the first intermediary chip 221 and the top chip 12 .

[0088] It should be noted that Figure 2 The packaged chip 10 shown in the embodiment is illustrated by the first intermediate chip 221 being arranged opposite to the four top chips 12 and electrically connected to the four top chips 12 arranged opposite to each other. It can be understood that Figure 2 The packaged chip 10 shown in the embodiment does not limit the number of top chips 12 that the first interposer chip 221 is disposed opposite to and the number of top chips 12 that are electrically connected to the first interposer chip 221 .

[0089] Please refer to Figure 2 and Figure 3A , Figure 3A 1 is a schematic diagram of a top view of the packaged chip 10 provided in this application in other embodiments.

[0090] In some embodiments, the at least three top chips 12 electrically connected to the same first interposer chip 221 may include at least two types of chips.

[0091] In this embodiment, at least two types of chips are electrically connected via the first intermediary chip 221 , which is beneficial for integrating multiple functions of the packaged chip 10 , thereby improving the electrical performance of the packaged chip 10 .

[0092] For example, the top chip 12 may include a main control chip 121 and other chips 122, which surround or semi-surround the main control chip 121. At least one first intermediate chip 221 electrically connects the main control chip 121 and the other chips 122 located on one side of the main control chip 121.

[0093] In this embodiment, placing the main control chip 121 near the center of the top layer 1 helps shorten the electrical connection distance between the main control chip 121 and each of the other chips 122, thereby improving the electrical connection efficiency between the main control chip 121 and the other chips 122. The use of at least one first intermediary chip 221 to electrically connect the main control chip 121 and the other chips 122 located to one side of the main control chip 121 strengthens the signal interconnection capability between the main control chip 121 and the other chips 122, facilitates the coordination of the main control chip 121 with the other chips 122, and improves the operating efficiency of the packaged chip 10.

[0094] The at least one first intermediate chip 221 is electrically connected to the other chips 122 located on both sides of the main control chip 121 .

[0095] In this embodiment, the first intermediate chip 221 bridges the other chips 122 located on both sides of the main control chip 121, which is beneficial to strengthening the signal interconnection capability between the other chips 122 located on both sides of the main control chip 121, thereby further improving the efficiency of the main control chip 121 in coordinating the work of the other chips 122.

[0096] It should be noted that the two sides of the main control chip 121 may be two opposite sides of the main control chip 121 , or two adjacent sides of the main control chip 121 .

[0097] The size of the main control chip 121 may be larger than that of the other chips 122 , so that the main control chip 121 can be designed with more circuits, thereby improving electrical performance.

[0098] Among them, other chips 122 may include memory chips, system-on-chip (SoC), interface chips (IO), bare chips (Die), high-bandwidth memory chips (HBM), virtual chips (Dummy), etc.

[0099] It should be noted that the relative positions of the main control chip 121 and the other chips 122 may also be in other ways. For example, the other chips 122 may not surround the main control chip 121. Figure 3A The packaged chip 10 shown in the embodiment only illustrates some relative positional relationships between the main control chip 121 and other chips 122 , and does not limit them. In addition, in some other embodiments, the top chip 12 may not include the main control chip 121 .

[0100] Please refer to Figure 2 and Figure 3B , Figure 3B 1 is a schematic top view of the packaged chip 10 provided in the present application in some further embodiments.

[0101] In some embodiments, interposer chip 22 may further include a second interposer chip 222 electrically connected to one of the at least three top chips 12. Along the stacking direction of top layer 1 and interposer layer 2, the orthographic projection of second interposer chip 222 on top layer 1 falls within the top chip 12 electrically connected to second interposer chip 222.

[0102] In this embodiment, the second interposer chip 222 does not span any die gap and can be used to encapsulate passive or active devices to improve the electrical performance of the top chip 12 electrically connected to the second interposer chip 222 , for example, to improve the ability of the top chip 12 electrically connected to the second interposer chip 222 to filter high-frequency noise.

[0103] For example, the second interposer chip 222 can be an integrated voltage regulator (IVR), an integrated passive device with through silicon vias (Thin Interposer Package Die), a power management module (PMI), a capacitor device made using deep trench capacitor technology (DTC), etc.

[0104] Please refer to Figure 2 、 Figure 3A and Figure 3B In some embodiments, along the stacking direction of the top layer 1 and the interposer 2 , the ratio of the area of ​​the orthographic projection of the interposer chip 22 on the top layer 1 to the area of ​​the top layer 1 may be in a range of 30% to 80%.

[0105] In this embodiment, by designing the range of the ratio of the area of ​​the positive projection of the intermediate chip 22 on the top layer 1 to the area of ​​the top layer 1, it is beneficial to balance the silicon content in the top layer 1 and the silicon content in the intermediate layer 2, thereby balancing the stress of the top layer 1 and the intermediate layer 2, and further helping to reduce the warping risk of the packaged chip 10.

[0106] For example, along the stacking direction of the top layer 1 and the intermediate layer 2, the ratio of the area of ​​the positive projection of the intermediate chip 22 on the top layer 1 to the area of ​​the top layer 1 can be, but is not limited to, 30%, or 40%, or 50%, or 60%, or 70%, or 80%, or other values ​​between 30% and 80%, etc.

[0107] For example, at least three top chips 12 are connected across the first intermediate chip 221 (see Figure 3A ), it is possible to achieve that along the stacking direction of the top layer 1 and the interposer 2, the ratio of the area of ​​the orthographic projection of the interposer chip 22 on the top layer 1 to the area of ​​the top layer 1 is greater than 40%. For another example, at least three top layer chips 12 are connected across the first interposer chip 221, and the second interposer chip 222 is electrically connected to one top layer chip 12, and along the stacking direction of the top layer 1 and the interposer 2, the orthographic projection of the second interposer chip 222 on the top layer 1 falls within the top layer chip 12 electrically connected to the second interposer chip 222 (see Figure 3B ), it is possible to achieve that along the stacking direction of the top layer 1 and the intermediate layer 2, the ratio of the area of ​​the orthographic projection of the intermediate chip 22 on the top layer 1 to the area of ​​the top layer 1 is greater than 60%.

[0108] If the ratio of the area of ​​the orthographic projection of the intermediate chip 22 on the top layer 1 to the area of ​​the top layer 1 along the stacking direction of the top layer 1 and the intermediate layer 2 is less than 30%, the silicon content in the intermediate layer 2 will be too low compared to the silicon content in the top layer 1, resulting in the shrinkage force of the top layer 1 in the packaged chip 10 being too large relative to the intermediate layer 2, causing the packaged chip 10 to warp toward the top layer 1.

[0109] If the ratio of the area of ​​the orthographic projection of the intermediate chip 22 on the top layer 1 to the area of ​​the top layer 1 along the stacking direction of the top layer 1 and the intermediate layer 2 is greater than 80%, the silicon content in the intermediate layer 2 will be excessive compared to the silicon content in the top layer 1, thereby causing the shrinkage force of the intermediate layer 2 in the packaged chip 10 to be too large relative to the top layer 1, causing the packaged chip 10 to warp toward the intermediate layer 2, i.e., causing the packaged chip 10 to warp in the reverse direction.

[0110] Therefore, by designing the ratio of the area of ​​the orthographic projection of the interposer chip 22 on the top layer 1 to the area of ​​the top layer 1 to be within a range of 30% to 80%, the risk of warping of the packaged chip 10 is reduced.

[0111] Please refer to Figure 2 、 Figures 4A to 4C , Figure 4A yes Figure 2 Schematic diagram of the distribution of the pad group 26 of the interposer 2 in the packaged chip 10 in some embodiments; Figure 4B yes Figure 2 Schematic diagram of the distribution of the pad group 26 of the interposer 2 in the packaged chip 10 in other embodiments; Figure 4C yes Figure 2 Schematic diagrams of the distribution of the pad groups 26 of the interposer 2 in the packaged chip 10 in some further embodiments are shown.

[0112] In some embodiments, interposer 2 may further include pad group 26 . Pad group 26 is located between top layer 1 and first interposer chip 221 . One side of pad group 26 is electrically connected to top layer chip 12 , and the other side of pad group 26 is electrically connected to first interposer chip 221 .

[0113] In this embodiment, the first interposer chip 221 is soldered into the interposer 2 through the pad group 26 , so that the first interposer chip 221 can be electrically connected to the top chip 12 .

[0114] For example, pad group 26 may include a first region 261 and a second region 262 , and second region 262 may surround or semi-surround first region 261 . Pad group 26 includes a plurality of first pads 263 located in first region 261 and a plurality of second pads 264 located in second region 262 .

[0115] In this embodiment, the pad group 26 is divided into zones, which is beneficial for different structural designs and / or functional designs of the pad group 26 for different zones.

[0116] In some examples, the second region 262 may surround the entire first region 261 (see Figure 4A ).

[0117] In other examples, the second area 262 may half surround the first area 261. For example, the second area 262 may surround three sides of the first area 261 (see FIG. Figure 4B ), for example, the second region 262 may surround two opposite sides of the first region 261 (see Figure 4C ).

[0118] The size of the pad located in the second region 262 is larger than the size of the pad located in the first region 261 .

[0119] In this embodiment, due to the large size of the first intermediate chip 221, the mounting accuracy requirements of the first intermediate chip 221 are relatively high. Through the mixed design of pads with multiple diameters (Combo CD), the mounting accuracy requirements of the first intermediate chip 221 can be improved, thereby reducing the area of ​​the first intermediate chip 221 and increasing the requirements for the mounting machine, thereby improving the mounting yield and efficiency of the first intermediate chip 221.

[0120] The distribution density of the first pads 263 in the first region 261 may be greater than the distribution density of the second pads 264 in the second region 262 , which is beneficial for improving the signal interconnection capability between the first pads 263 in the first region 261 and the first interposer chip 221 .

[0121] It should be noted that Figures 4A to 4C The embodiment provides a mixed design of pads of two sizes. It is understandable that in some other embodiments, the pad group 26 may also be a mixed design of pads of three or more sizes.

[0122] Please refer to Figure 2 、 Figure 4A and Figure 5 , Figure 5 yes Figure 2 FIG. 1 is a schematic diagram illustrating the distribution of pads of the first interposer chip 221 in the packaged chip 10 in some embodiments.

[0123] In some embodiments, the first interposer chip 221 may include a third region 2211 and a fourth region 2212, where the fourth region 2212 surrounds or semi-surrounds the third region 2211. The first interposer chip 221 may include a plurality of third pads 2213 located in the third region 2211 and a plurality of fourth pads 2214 located in the fourth region 2212. The third pads 2213 are soldered to the first pads 263, and the fourth pads 2214 are soldered to the second pads 264. The third pads 2213 and the fourth pads 2214 have the same size.

[0124] In this embodiment, since the size of the second pad 264 is larger than that of the first pad 263, the difficulty of welding the fourth pad 2214 and the second pad 264 is less than the difficulty of welding the third pad 2213 and the first pad 263, which is beneficial to reducing the overall mounting difficulty of the first intermediate chip 221 and the pad group 26.

[0125] Among them, high-density interconnection signals can be transmitted between the third pad 2213 and the first pad 263.

[0126] In this embodiment, since the distribution density of the first solder pads 263 in the first area 261 can be greater than the distribution density of the second solder pads 264 in the second area 262, the signal interconnection capability between the first intermediate signal and the solder pad group 26 in the first area 261 and the third area 2211 is stronger than the signal interconnection capability between the second area 262 and the fourth area 2212. Therefore, the transmission of high-density interconnected signals between the third solder pad 2213 and the first solder pad 263 is beneficial to improving the electrical performance of the packaged chip 10.

[0127] In some examples, a low-density interconnect signal can be transmitted between the fourth pad 2214 and the second pad 264 to assist in electrical interconnection between the first interposer chip 221 and at least three chips.

[0128] It should be noted that in the embodiments of the present application, the terms "high density" and "low density" in high-density interconnect signals and low-density interconnect signals can be relative terms and can be distinguished by the relative density of pad distribution, the relative speed of signal transmission, and other aspects. For example, the pad density in the area transmitting high-density interconnect signals is greater than the pad density in the area transmitting low-density interconnect signals. For another example, the transmission speed of high-density interconnect signals is greater than the transmission speed of low-density interconnect signals.

[0129] In other examples, the fourth pad 2214 and the second pad 264 can be used to transmit power signals to form a power supply area, which is beneficial to the integrity of electrical signals between at least three top chips 12 electrically connected to the first interposer chip 221 .

[0130] In some other examples, the fourth pad 2214 and the second pad 264 may be grounded, which helps to improve the stability of signal transmission between the at least three top chips 12 electrically connected to the first interposer chip 221 .

[0131] It should be noted that Figure 5 In the embodiment, the first interposer chip 221 is illustrated as having the fourth region 2212 surrounding the third region 2211 . It is understandable that the fourth region 2212 in the first interposer chip 221 may also be configured to semi-surround the third region 2211 .

[0132] Please refer to Figure 4A 、 Figure 6 and Figure 7 , Figure 6 It is a comparative example of the pad distribution of the pad group 26 in the prior art; Figure 7 yes Figure 4A Examples and Figure 6 Comparative Example is a schematic diagram showing a simulation comparison of mounting with the first interposer chip 221 at different mounting accuracies.

[0133] Figure 6 In the comparative example shown, the size of the first pads 263 in the first region 261 of the pad group 26 is the same as the size of the second pads 264 in the second region 262 .

[0134] right Figure 4A The pad group 26 shown in the embodiment is Figure 6 The pads shown in the scale are simulated and compared with different mounting accuracies. Figure 7 If the small and medium circles are inside the large circle, that is, Min shift gap>0, it means that the placement requirements are met; if the small circle is at least partially outside the large circle, that is, Min shift gap<0, it means that the placement requirements are not met.

[0135] Through simulation calculation, it is found that when the placement accuracy is ±1μm, Figure 4A In the embodiment, Min shift gap = +6.281 μm, Figure 6 In the comparative example, the Min shift gap is +3.657μm; when the placement accuracy is ±2μm, Figure 4A In the embodiment, Min shiftgap=﹢3.562μm, Figure 6 In the comparative example, the Min shift gap is -0.186μm; when the placement accuracy is ±3μm, Figure 4A In the embodiment, Min shift gap = +0.842 μm, Figure 6 In the comparative example, the Min shift gap = -4.030 μm.

[0136] From the simulation results, we can see that Figure 6 In the comparative example, the pad group 26 is designed with the first pad 263 and the second pad 264 of the same size, which can only meet the mounting requirements of the first interposer chip 221 and the pad group 26 when the mounting accuracy is ±1 μm. Figure 4A The pad group 26 in the embodiment adopts a mixed design of pads with various diameters (Combo CD) that can meet the mounting requirements of the first interposer chip 221 and the pad group 26 when the mounting accuracy is ±1μm, ±2μm, and ±3μm. Therefore, the embodiment of the present application adopts a mixed design of pads with various diameters (Combo CD) that can improve the mounting accuracy requirement of the first interposer chip 221 from ±1μm to ±3μm, thereby significantly reducing the mounting accuracy requirement of the first interposer chip 221, reducing mounting costs and man-hours, and improving yield and efficiency.

[0137] Please refer to Figures 8A to 9 , Figure 8A yes Figure 1 The packaged chip 10 is a schematic structural diagram after adopting a half-cut process in some embodiments; Figure 8B yes Figure 8A The packaged chip 10 shown is a schematic diagram of a partial cross-sectional structure in some embodiments when cut along line BB; Figure 9 yes Figure 8A Schematic diagram of the process of using half-cutting process for part of the area of ​​the packaged chip 10.

[0138] It should be noted that Figure 8B FIG. 1 shows only a partial cross-sectional structure of the top layer 1 in the packaged chip 10 .

[0139] In some embodiments, a surface of the first organic layer 11 facing away from the interposer may be provided with a groove 111 , which is provided along at least a portion of the periphery of the top chip 12 . The top layer 1 further includes a third organic layer 14 , which fills the groove 111 .

[0140] In this embodiment, a half-cut process can be used to cut at least a portion of the periphery of the top chip 12, so that a groove 111 is formed in the first organic layer 11 corresponding to at least a portion of the periphery of the top chip 12. This releases stress generated by curing shrinkage during the formation of the first organic layer 11, thereby reducing the risk of warping and improving the reliability of the packaged chip 10. By filling the third organic layer 14 into the groove 111, the bonding strength of the periphery of the top chip 12 can be improved, thereby improving the reliability of the packaged chip 10.

[0141] It should be noted that the groove 111 can be provided on one edge, two edges, three edges, or four edges of the top chip 12 .

[0142] Illustratively, the third organic layer 14 is made of a different material from the first organic layer 11 .

[0143] In this embodiment, by designing the third organic layer 14 to be made of different materials from the first organic layer 11, the stress direction generated by the curing shrinkage during the formation of the third organic layer 14 is different from that of the first organic layer 11, thereby avoiding stress concentration at the periphery of the top chip 12, reducing micro-area stress, improving bonding strength, and thereby reducing the risk of warping of the packaged chip 10 and improving packaging reliability.

[0144] The material of the third organic layer 14 may be, but is not limited to, molding compound, underfill 13 , polyimide material, and the like.

[0145] Exemplarily, the groove 111 may be arranged at least between two adjacent top chips 12 .

[0146] In this embodiment, by setting the groove 111 between two adjacent top-level chips 12, it is beneficial to release the stress between the two adjacent top-level chips 12, thereby reducing the warping risk of the area between the two adjacent top-level chips 12, and further improving the structural stability of the area between the two adjacent top-level chips 12, thereby improving the reliability of the packaged chip 10.

[0147] Exemplarily, the process of packaging the chip 10 using the half cut process may include steps S10 , S20 , and S30 .

[0148] S10 , cutting the first organic layer 11 corresponding to the periphery of the top chip 12 to form a groove 111 .

[0149] The groove 111 may be formed in the first organic layer 11 by using laser, wafer dicing, dry etching, or corrosion.

[0150] S20 , filling the groove 111 with an organic material and curing the organic material.

[0151] The organic material partially overflows the groove 111 to prevent the groove 111 from being insufficiently filled.

[0152] S30 , grinding the organic material overflowing from the groove 111 to form a third organic layer 14 .

[0153] The top surface of the third organic layer 14 is flush with the top surface of the first organic layer 11 , which is beneficial to improving the reliability of the packaged chip 10 .

[0154] Please refer to Figure 2 、 Figure 10A and Figure 10B , Figure 10A yes Figure 1 The packaged chip 10 is shown as a schematic cross-sectional structure diagram of other embodiments when cut along line AA; Figure 10B yes Figure 1 The schematic cross-sectional structure diagram of the packaged chip 10 shown is taken along line AA in some other embodiments. Figure 10A and Figure 10B The packaged chip 10 shown in the embodiment may include Figure 2 Most of the technical features of the packaged chip 10 shown in the embodiment are mainly described below to explain the differences between the two, and most of the same contents between the two are not repeated here.

[0155] In some embodiments, the redistribution layer 21 may include an electrical connection layer 211 and an insulating layer 212 encapsulating the electrical connection layer 211. The top chip 12 may be electrically connected to the first interposer chip 221 via the electrical connection layer 211. Parts of at least three top chips 12 may be electrically connected via the electrical connection layer 211.

[0156] In this embodiment, the redistribution layer 21 can not only be electrically connected to the top chip 12 through the electrical connection layer 211 to achieve horizontal electrical interconnection, but can also be electrically connected to the first intermediate chip 221 and the top chip 12 through the electrical connection layer 211 to achieve vertical electrical interconnection, which is beneficial to improving the electrical performance of the packaged chip 10.

[0157] It should be noted that Figure 10A The packaged chip 10 shown in the embodiment is a cross-sectional diagram at AA. The electrical connection layer 211 also has other connection forms at other cross-sections. The electrical connection layer 211 does not connect all the pins 12b of the top chip 12 in series. There is a parallel circuit design in the electrical connection layer 211, so that there are parallel-designed pins 12b in the top chip 12.

[0158] The material of the electrical connection layer 211 may be copper, and the material of the insulating layer 212 may be polyimide.

[0159] In some embodiments, some of the copper pillars 24 among the plurality of copper pillars 24 are electrically connected to the electrical connection layer 211 , and other parts of the copper pillars 24 among the plurality of copper pillars 24 are embedded in the first interposer chip 221 .

[0160] In this embodiment, by embedding the copper pillars 24 in the first intermediate chip 221, the first intermediate chip 221 can be directly electrically connected to the substrate 3 through the copper pillars 24, thereby improving the vertical interconnection performance of at least three top-level chips 12, thereby improving the electrical performance of the packaged chip 10.

[0161] The copper pillars 24 embedded in the first interposer chip 221 may be electrically connected to the electrical connection layer 211 through signal traces within the first interposer chip 221 .

[0162] See also Figure 11 and Figure 12 , Figure 11 is a schematic top view of the packaged chip 10 provided in the present application in some other embodiments; Figure 12 yes Figure 11 The packaged chip 10 is shown as a schematic cross-sectional view of some embodiments when cut along line CC. Figure 11 and Figure 12 The packaged chip 10 shown in the embodiment may include Figure 2 Most of the technical features of the packaged chip 10 shown in the embodiment are mainly described below to explain the differences between the two, and most of the same contents between the two are not repeated here.

[0163] In some embodiments, there may be multiple second intermediary chips 222 , and each second intermediary chip 222 is electrically connected to one top chip 12 .

[0164] In this embodiment, by providing multiple second intermediate chips 222, it is not only beneficial to balance the silicon content of the intermediate layer 2 and the top layer 1 to reduce the warping risk of the packaged chip 10, but also beneficial to improve the electrical performance of the top layer chip 12 with the second intermediate chip 222, thereby improving the electrical performance of the packaged chip 10.

[0165] The plurality of second interposer chips 222 can be electrically connected to the same top chip 12 , and along the stacking direction of the top layer 1 and the interposer layer 2 , the orthographic projections of the plurality of second interposer chips 222 on the top layer 1 fall within the same top chip 12 .

[0166] In this embodiment, the multiple second intermediate chips 222 can be the same type of sealing devices or different types of sealing devices, so as to further improve the electrical performance of the top chip 12 electrically connected to the multiple second intermediate chips 222, and can realize the integration of multiple functions, which is beneficial to improving the electrical performance of the packaged chip 10.

[0167] It should be noted that the connection method between the second intermediate chip 222 and the redistribution layer 21 can be the same as or different from the connection method between the first intermediate chip 221 and the redistribution layer 21, and the connection method between the second intermediate chip 222 and the substrate 3 can be the same as or different from the connection method between the first intermediate chip 221 and the substrate 3.

[0168] The packaged chip 10 provided in the present application improves the reliability of the packaged chip 10, reduces the risk of warping, and improves electrical performance by increasing the area ratio of the intermediate chip 22, increasing the number of top chips 12 bridged by the first intermediate chip 221, designing the second intermediate chip 222 that does not cross any die gap, and using the halfcut process to improve the stress of the top layer 1. The packaged chip 10 provided in the present application can be applied to all structures using a heterogeneous intermediate layer 2. For example, high-performance computing chips, artificial intelligence chips, image processors, and other architectural scenarios that require higher integration density, electrical performance, and reliability. The packaged chip 10 provided in the present application has greater advantages and potential in large-size packaging. The packaged chip 10 provided in the present application has greater advantages and potential in heterogeneous top die integration.

[0169] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of this application can be combined with each other, and any combination of features in different embodiments is also within the scope of protection of this application. That is to say, the multiple embodiments described above can also be arbitrarily combined according to actual needs.

[0170] It should be noted that all the above drawings are for illustrative purposes only and do not represent the actual size of the product. Furthermore, the dimensional ratios between the components in the drawings are not intended to limit the actual product of the present application.

[0171] The above are only some of the embodiments and implementations of this application. The scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A packaged chip, characterized in that: Includes top and intermediate layers of the stacked setup; The top layer includes a first organic layer and at least three top chips arranged at intervals, and the first organic layer wraps around the periphery of the top chip; The intermediate layer includes a second organic layer and an intermediate chip, the second organic layer is arranged to wrap the periphery of the intermediate chip, the intermediate chip includes at least one first intermediate chip, one first intermediate chip is electrically connected to at least one top chip, and in the stacking direction of the top layer and the intermediate layer, one first intermediate chip is arranged opposite to at least three top chips.

2. The packaged chip according to claim 1, wherein: The first intermediate chip is electrically connected to at least three of the top chips that are arranged opposite to each other.

3. The packaged chip according to claim 1 or 2, wherein: The interposer further includes a pad group, the pad group being located between the top layer and the first interposer chip, one side of the pad group being electrically connected to the top layer chip, and the other side of the pad group being electrically connected to the first interposer chip; The pad group includes a first area and a second area, and the second area is arranged to surround or semi-surround the first area; The pad group includes a plurality of first pads located in the first area and a plurality of second pads located in the second area; The size of the pad located in the second area is larger than the size of the pad located in the first area.

4. The packaged chip according to claim 3, wherein: The distribution density of the first pads in the first region is greater than the distribution density of the second pads in the second region.

5. The packaged chip according to claim 3 or 4, wherein: The first interposer chip includes a third area and a fourth area, and the fourth area surrounds or semi-surrounds the third area; The first interposer chip includes a plurality of third pads located in a third area and a plurality of fourth pads located in a fourth area, the third pads being soldered to the first pads, and the fourth pads being soldered to the second pads; The size of the third pad is the same as the size of the fourth pad.

6. The packaged chip according to claim 5, wherein: A high-density interconnect signal is transmitted between the third pad and the first pad; A low-density interconnect signal is transmitted between the fourth pad and the second pad, or the fourth pad and the second pad are used to transmit a power signal, or the fourth pad and the second pad are grounded.

7. The packaged chip according to any one of claims 2 to 4, wherein: The at least three top chips electrically connected to the same first interposer chip include chips of at least two types.

8. The packaged chip according to any one of claims 1 to 7, wherein: The intermediary chip further includes a second intermediary chip, wherein the second intermediary chip is electrically connected to one of the top chips of the at least three top chips; Along the stacking direction of the top layer and the interposer, an orthographic projection of the second interposer chip on the top layer falls within the top layer chip electrically connected to the second interposer chip.

9. The packaged chip according to any one of claims 1 to 8, wherein: Along a stacking direction of the top layer and the interposer layer, a ratio of an area of ​​an orthographic projection of the interposer chip on the top layer to an area of ​​the top layer is in a range of 30% to 80%.

10. The packaged chip according to any one of claims 1 to 9, wherein: The interposer further includes a redistribution layer, which is disposed between the top layer and the interposer. The redistribution layer includes an electrical connection layer and an insulating layer wrapping the electrical connection layer. The top chip is electrically connected to the first intermediate chip through the electrical connection layer; Part of the at least three top-layer chips are electrically connected via the electrical connection layer.

11. The packaged chip according to claim 10, wherein: The interposer layer further includes a plurality of copper pillars, some of the copper pillars are electrically connected to the electrical connection layer, and other parts of the copper pillars are embedded in the first interposer chip; The packaged chip further includes a substrate, which is arranged on a side of the intermediary layer away from the top layer, and is soldered to ends of a plurality of copper pillars away from the top layer.

12. The packaged chip according to any one of claims 1 to 11, wherein: A groove is provided on a surface of the first organic layer facing away from the interposer, and the groove is provided along at least a portion of a periphery of the top chip; The top layer further includes a third organic layer, and the third organic layer is filled in the groove.

13. The packaged chip according to claim 12, wherein: The third organic layer is made of a material different from that of the first organic layer.

14. The packaged chip according to claim 12 or 13, wherein: The groove is arranged at least between two adjacent top-layer chips.

15. The packaged chip according to any one of claims 1 to 14, wherein: The top chip includes a main control chip and other chips, and the other chips surround or semi-surround the main control chip; At least one of the first intermediate chips is electrically connected to the main control chip and the other chips located on one side of the main control chip.

16. The packaged chip according to claim 15, wherein: At least one of the first intermediate chips is electrically connected to the other chips located on both sides of the main control chip.

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