Cutting channel testing structure and cutting method
By setting L-shaped test keys at the edge of the wafer exposure area, the problem of difficult dies around the test keys is solved, the wafer utilization rate is improved and the comparability of the test methods is maintained.
Patent Information
- Application Number
- CN202510725714.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-30
- Publication Date
- 2025-09-05
AI Technical Summary
In the dicing lane, the die around the test keys are difficult to remove during dicing, especially when using dicing lanes below 20 μm. The existing arrangement of the test keys leads to stress problems.
By setting test keys at the boundary of the exposure area of the wafer and adopting an L-shaped cutting path test structure, the area occupied by the test keys is reduced, and a second area is set in the cutting path for placing the test keys, avoiding the large-scale layout of the test keys and solving the stress problem.
It effectively reduces the area occupied by the test key, solves the problem of difficulty in picking the die around the test key, improves the utilization rate of the wafer area, and maintains the original test method and data comparability.
Smart Images
Figure CN120600730A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a cutting path test structure and a cutting method. Background Art
[0002] Wafer Acceptance Test (WAT), also known as Process Control Monitoring (PCM), tests the test keys on the wafer scribe lines. It monitors the normality and stability of each process step by measuring electrical parameters, including capacitance, resistance, contact, and metal traces. These parameters are crucial indicators that require monitoring during the manufacturing process. They reflect the electrical characteristics of semiconductor devices, such as current conduction and voltage withstand capabilities. Typically performed before wafer fabrication, the test involves inserting a probe card into the metal pad of the test key. The other end of the probe card is connected to the WAT tester, which automatically controls the test position and content. After completing a test key, the probe card automatically moves to the next test key until the entire wafer is tested. The commonly used cutting line width in mass production of process technology is generally 80μm or 60μm, but for very small chips, cutting lines below 20μm will be considered to maximize the utilization of the area of each wafer.
[0003] At present, products with cutting paths below 20μm cannot place regular-sized WAT / RE TestKeys in the cutting paths. In order to ensure the original test method, the TestKeys are often placed in the four corners and center of the Shot (exposure area). Figure 1 However, this test key arrangement makes it difficult to remove the die around the test key due to stress during cutting.
[0004] It should be noted that the information disclosed in the background technology section of the invention is only intended to deepen the understanding of the general background technology of the invention, and should not be regarded as an admission or any form of implication that the information constitutes prior art already known to those skilled in the art. Summary of the Invention
[0005] The object of the present invention is to provide a dicing street test structure and a dicing method to solve the problem that dies around the test key are difficult to remove when dicing.
[0006] In order to solve the above technical problems, the present invention provides a cutting path test structure, including several exposure areas arranged on a wafer, a second area with a predetermined width arranged along the boundary of the exposure area, for setting a test key, and the remaining area of the exposure area is the first area, for arraying several chips, and there are cutting paths between the chips.
[0007] Preferably, the width of the test key is not greater than the length of the die, and the size of the die is the sum of the sizes of the chip and the dicing street.
[0008] Preferably, the exposure area is rectangular and has boundaries along a first direction and a second direction.
[0009] Preferably, the second region has a first segment and a second segment facing each other, the first segment is arranged at the first direction boundary, and the second segment is arranged at the second direction boundary.
[0010] Preferably, the ends of the first section and the second section are connected.
[0011] Preferably, the length of the first segment is equal to the boundary length of the exposure area in the first direction.
[0012] Preferably, the length of the second segment is equal to the boundary length of the exposure area in the second direction.
[0013] Preferably, the width of the cutting street is less than 20 μm.
[0014] Preferably, the test keys are rectangular and arranged in an array in the second area, and the size of the test keys is 60 μm*1300 μm.
[0015] A cutting method is provided for cutting a wafer along a cutting path, wherein the wafer is provided with the cutting path test structure as described above.
[0016] In a cutting lane test structure provided by the present invention, the distribution area of the test keys in the entire test structure is adjusted and the test keys are placed at the boundary of the exposure area, thereby maintaining the original test keys and test methods, breaking the large-scale layout of the test keys, and solving the problem that the grains in the area around the test keys are difficult to pick. Compared with the existing test key arrangement method, the area occupied by the test keys can be greatly reduced.
[0017] In a cutting method provided by the present invention, a second area is provided at the boundary of an exposure area, and test keys are placed in the second area. Compared with existing test key arrangements, this method significantly reduces the area occupied by the test keys and also alleviates the stress issues associated with the large layout of the test keys. The cutting method provided by the present invention and the cutting lane test structure provided by the present invention are based on the same inventive concept. Therefore, the cutting method provided by the present invention has at least all the advantages of the cutting lane test structure provided by the present invention, and will not be further described here. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] Those skilled in the art will appreciate that the accompanying drawings are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention.
[0019] Figure 1 It is a schematic diagram of the distribution of chips and test structures in the prior art;
[0020] Figure 2 It is a structural diagram of an embodiment of the present invention;
[0021] Figure 3 It is a schematic diagram of the internal structure of the second area according to an embodiment of the present invention.
[0022] In the attached figure:
[0023] 100, first area; 200, second area; 300, third area; 400, fourth area; 500, test key. DETAILED DESCRIPTION
[0024] To make the objects, advantages, and features of the present invention more clearly apparent, the present invention is further described below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale. They are only used to conveniently and clearly assist in illustrating the purposes of the embodiments of the present invention. In addition, the structures shown in the drawings are often part of the actual structure. In particular, different drawings may need to illustrate different focuses and sometimes use different scales.
[0025] As used in the present invention, the singular forms "a", "an" and "the" include plural objects, the term "or" is generally used in a sense including "and / or", the term "several" is generally used in a sense including "at least one", and the term "at least two" is generally used in a sense including "two or more". In addition, the terms "first", "second" and "third" are used for descriptive purposes only and cannot be understood as indicating or suggesting relative importance or implicitly indicating the number of the indicated technical features. Therefore, features defined as "first", "second", and "third" may explicitly or implicitly include one or at least two of such features. The term "proximal end" generally refers to the end closest to the operator, and the term "distal end" generally refers to the end closest to the patient. "One end" and "the other end" as well as "proximal end" and "distal end" generally refer to two corresponding parts, which include not only endpoints. The terms "mounted", "connected", and "connected" should be understood in a broad sense. For example, they can be fixedly connected, detachably connected, or integrated; they can be mechanically connected or electrically connected; they can be directly connected or indirectly connected through an intermediate medium; they can be internal communication between two elements or an interactive relationship between two elements. In addition, as used in the present invention, "one element is arranged on another element" generally only means that there is a connection, coupling, cooperation, or transmission relationship between the two elements, and the connection, coupling, cooperation, or transmission between the two elements can be direct or indirect through an intermediate element, and it should not be understood to indicate or imply a spatial positional relationship between the two elements, that is, one element can be in any position such as inside, outside, above, below, or to the side of another element, unless the content clearly indicates otherwise. For those skilled in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.
[0026] The inventors discovered that scribe lines and test keys are two key elements used for WAT testing in the semiconductor manufacturing process. Scribe lines are narrow strips along the edge of the wafer used for the subsequent dicing process. Test keys are generally located within the scribe lines for WAT testing. However, as chip process sizes shrink, the scribe line size on small chips also shrinks. To maximize wafer utilization, when the scribe line size is smaller than the test key size, the test keys are generally placed at the four corners and center of the exposure area. However, this arrangement makes it difficult to remove the die around the test key due to stress during dicing.
[0027] Based on this, the core idea of the present invention is to adjust the distribution area of the test keys in the entire test structure and place the test keys at the boundary of the exposure area, thereby maintaining the original test keys and test methods, breaking the large-scale layout of the test keys, and solving the problem that the grains in the area around the test keys are difficult to pick.
[0028] For details, please refer to Figure 2-Figure 3 , which is a schematic diagram of an embodiment of the present invention. Figure 2 As shown, a cutting path test structure includes several exposure areas (Shot) arranged on a wafer, a second area 200 with a predetermined width is set along the boundary of the exposure area, for setting a test key 500, and the remaining area of the exposure area is the first area 100, for arraying several chips (Chip), with cutting paths between the chips.
[0029] like Figure 2 The exposure area has a relative first area 100 and a second area 200. The green area is the first area 100, the yellow area is the second area 200, and the grid lines are cutting paths. The second area 200 is set at the boundary of an exposure area, and the test key 500 is placed in the second area 200. Compared with the existing arrangement of the test keys 500, the area occupied by the test keys 500 can be greatly reduced, and the stress problem caused by the large-scale layout of the test keys 500 can also be solved.
[0030] In the semiconductor manufacturing process, a wafer shot (also known as the nominal exposure size) refers to the complete step of projecting the pattern of the mask on the lithography machine onto the silicon wafer. Simply put, a wafer shot is an exposure point on the silicon wafer, which determines the size and density of the circuit pattern.
[0031] It is understandable that the width of the test key 500 is not greater than the length of the die, and the size of the die is the sum of the size of the chip and the scribe line. Die size = Chip size + Scribe Line.
[0032] like Figure 2 As shown, the chip is divided by dicing lines, and the width of the second region 200 is often the length or width of the die region where it is located. Correspondingly, the width of the test key 500 is less than or equal to the length of the die. Exemplarily, the width of the dicing lines is less than 20 μm.
[0033] like Figure 2As shown, the exposure area is rectangular and has boundaries along a first direction and a second direction. The first direction is the X direction, and the second direction is the Y direction. The cutting paths are the grid lines in the figure. The multiple grids divided by the cutting paths are the corresponding grain areas. Here, the dividing boundary of the second area 200 can be set according to the layout of the cutting paths, and the morphology of the second area 200 is set based on the shape of the grains. For example, at the boundary of the exposure area, a row of grain areas divided along the X direction is set as the second area 200, and a column of grain areas divided along the Y direction is set as the second area 200 for setting the test key 500. In other embodiments, several rows of grain areas along the X direction or several columns of grain areas along the Y direction can also be set as the second area 200.
[0034] Since the large area layout of the test key 500 is the main reason why the surrounding die are difficult to pick, the test key 500 is set along the boundary of the exposure area to avoid the stacking and concentrated layout of the test keys 500 and avoid stress problems when cutting the die around the test key 500.
[0035] Specifically, the second region 200 has a first segment (not labeled) and a second segment (not labeled) that are opposite each other. The first segment is located at the boundary of the first direction, and the second segment is located at the boundary of the second direction. The ends of the first segment and the second segment are connected. The first segment occupies a row of die areas in the X direction, while the second segment occupies a column of die areas in the Y direction. The long sides of the test keys 500 in the first segment are arranged along the X direction, while the long sides of the test keys 500 in the second segment are arranged along the Y direction.
[0036] like Figure 3 As shown, for the convenience of cutting, the long side of the test key 500 of the test structure, that is, the basic test unit (12PIN), is placed in the width direction of 3 to 5 die areas. Here, the length direction of the test key 500 is the same as the length direction of the die area. The test keys 500 are placed in groups along the X direction or the Y direction.
[0037] Understandably, in order to match the BLTest key structure as closely as possible and ensure data comparability, the original Test Key design is maintained and an L-shaped test structure layout is adopted.
[0038] Specifically, the length of the first segment is equal to the length of the boundary of the exposure area in the first direction. The length of the second segment is equal to the length of the boundary of the exposure area in the second direction. The ends of the first segment and the second segment overlap.
[0039] The lengths of the first and second sections match the boundary lengths of the exposure area. In a single exposure area, an L-shaped test structure layout is adopted. Multiple exposure areas can be spliced together to form a surrounding test structure layout. On both sides of the outside of the exposure area in the horizontal and vertical directions, such as Figure 2 A horizontal and a vertical area are provided below and to the right of the exposure area to place a test key 500. In addition, a third area 300 is provided at the center of the exposure area, and a fourth area 400 is provided at the upper left corner of the exposure area. The third area 300 and the fourth area 400 can also be provided with corresponding test keys 500 as needed.
[0040] like Figure 3 As shown, the test key 500 is rectangular and has a size of 60 μm*1300 μm. In the first section, the length direction of the test key 500 is in the same direction as the X direction, and in the second section, the length direction of the test key 500 is in the same direction as the Y direction.
[0041] In one embodiment, taking a product with a chip size of 390μm*295μm as an example, the device combination is HV+RV, and a test structure is set at the boundary of the exposure area. For example, a horizontal and a vertical test key 500 are placed in the L-shaped second area 200. The width of the test key 500 in the X direction is no greater than the length of a die in the X direction, and the width of the test key 500 in the Y direction is no greater than the length of a die in the Y direction. According to the solution provided in this case, the TK of a shot occupies the area of approximately 176 dies, saving approximately 80 dies compared to the original solution, and also solving the problem of large-area layout of TKs.
[0042] Based on the same technical concept, the present disclosure provides a dicing method for dicing a wafer along dicing streets, wherein the wafer is provided with a dicing street test structure as described above. The dicing street test structure includes a plurality of exposure areas (shots) provided on the wafer, a second area 200 of a certain width provided along the boundary of the exposure area for setting test keys 500, and the remaining area of the exposure area serving as a first area 100 for arranging a plurality of chips (chips) in an array with dicing streets between the chips.
[0043] The second area 200 is set to be L-shaped along the exposure area. Compared with the existing test key 500 arrangement, it solves the stress problem caused by the large layout of the test key 500. Furthermore, the size of the second area 200 is set along the cutting path of the chip, which greatly improves the utilization rate of the wafer area and reduces the area occupied by the test key 500. At the same time, it can match the BLTest key structure as much as possible and ensure data comparability, and maintains the original shape design of the test key 500 without adjusting the test method.
[0044] like Figure 2 As shown, the exposure area is rectangular and has boundaries along a first direction and a second direction. The first direction is the X direction, and the second direction is the Y direction. The cutting paths are the grid lines in the figure. The multiple grids divided by the cutting paths are corresponding to the grain areas. Here, the dividing boundary of the second area 200 can be set according to the layout of the cutting paths. The morphology of the second area 200 is set based on the shape of the grains as the basic unit to improve the utilization of the wafer area. For example, at the boundary of the exposure area, a row of grain areas divided along the X direction is set as the second area 200, and a column of grain areas divided along the Y direction is set as the second area 200 for setting the test key 500.
[0045] In the dicing lane test structure and dicing method provided by the present invention, since the large-area layout of the test key 500 is the main reason why the surrounding die are difficult to remove, the test key 500 is arranged along the boundary of the exposure area to avoid stacking and concentrating the test keys 500, thereby avoiding stress problems when cutting the die around the test key 500. Furthermore, an L-shaped test structure layout is adopted to match the BL test key structure as much as possible to ensure data comparability, maintain the original test key design, and the dividing boundary of the second area 200 can be set according to the layout of the dicing lane. The morphology of the second area 200 is set based on the shape of the die, which can maximize the utilization of the wafer. Taking a product with a chip size of 390μm*295μm as an example, the test structure is set at the boundary of the exposure area, and a horizontal and a vertical test key 500 are placed in the L-shaped second area 200. The TK of a shot occupies the area of approximately 176 dies, saving approximately 80 dies compared to the original solution, while also solving the problem of large-area layout of the TK.
[0046] The above description is only a description of the preferred embodiment of the present invention and does not limit the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure are within the scope of protection of the technical solution of the present invention.
Claims
1. A cutting line test structure, characterized in that: It includes several exposure areas set on the wafer, a second area with a predetermined width is set along the boundary of the exposure area for setting a test key, and the remaining area of the exposure area is the first area for arraying several chips with cutting lanes between the chips.
2. The scribe line test structure according to claim 1, wherein: The width of the test key is not greater than the length of the die, and the size of the die is the sum of the sizes of the chip and the dicing street.
3. The scribe line test structure according to claim 1, wherein: The exposure area is rectangular and has boundaries along a first direction and a second direction.
4. The dicing street test structure according to claim 3, wherein: The second region has a first segment and a second segment facing each other, the first segment is arranged at the first direction boundary, and the second segment is arranged at the second direction boundary.
5. The dicing street test structure according to claim 4, wherein: The ends of the first section and the second section are connected.
6. The scribe line test structure according to claim 4, wherein: The length of the first segment is equal to the boundary length of the exposure area in the first direction.
7. The scribe line test structure according to claim 4, wherein: The length of the second segment is equal to the boundary length of the exposure area in the second direction.
8. The scribe line test structure according to claim 1, wherein: The width of the cutting street is less than 20 μm.
9. The scribe line test structure according to claim 1, wherein: The test keys are rectangular and arranged in an array in the second area. The size of the test keys is 60 μm*1300 μm.
10. A cutting method, characterized in that: Used for cutting a wafer along a cutting street, and the wafer is provided with a cutting street test structure according to any one of claims 1 to 9.