Semiconductor test structure and semiconductor test method

Abstract

The invention provides a semiconductor test structure and a semiconductor test method, the semiconductor test structure comprises a test structure, and the test structure comprises a substrate; the first dielectric layer and the semiconductor layer are stacked on the first surface of the substrate; the second dielectric layer is located on the first surface of the substrate, and the second dielectric layer further covers the semiconductor layer and the first dielectric layer; the first through hole extends from the second surface of the substrate to the semiconductor layer, the first surface is opposite to the second surface, and the depth change trend of the first through hole is obtained by monitoring the resistance change trend of the semiconductor layer. According to the technical scheme of the invention, the etching amount of the through silicon via etching process can be monitored, so that batch abnormity of the through silicon via etching process can be avoided.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a semiconductor test structure and a semiconductor test method. Background Art

[0002] Currently, 3D-IC bonding technology widely uses through silicon via (TSV) structures to achieve electrical connections between bonding substrates.

[0003] When etching a substrate to form a through silicon via (TSV), it is generally required that the over-etching stop at a shallow trench isolation structure in the substrate. However, in actual production, there is a lack of effective means to monitor the amount of over-etching.

[0004] Therefore, how to monitor the etching amount of the through silicon via etching process is an urgent problem that needs to be solved. Summary of the Invention

[0005] The object of the present invention is to provide a semiconductor test structure and a semiconductor test method, which can monitor the etching amount of a through silicon via etching process to avoid batch abnormalities in the through silicon via etching process.

[0006] To achieve the above object, the present invention provides a semiconductor test structure, including a test structure, wherein the test structure includes:

[0007] substrate;

[0008] A first dielectric layer and a semiconductor layer are stacked on the first surface of the substrate;

[0009] a second dielectric layer, located on the first surface of the substrate, the second dielectric layer also covering the semiconductor layer and the first dielectric layer;

[0010] The first through hole extends from the second surface of the substrate toward the semiconductor layer, the first surface and the second surface are opposite to each other, and the depth variation trend of the first through hole is obtained by monitoring the resistance variation trend of the semiconductor layer.

[0011] Optionally, a shallow trench isolation structure and a second through hole are formed in the substrate outside the test structure, the shallow trench isolation structure extends from the first surface of the substrate into the substrate, and the second through hole extends from the second surface of the substrate toward the shallow trench isolation structure. The second through hole and the first through hole are formed using the same process, and whether the position of the second through hole in the substrate or the shallow trench isolation structure is within a predetermined range is determined by the depth change trend of the first through hole.

[0012] Optionally, the test structure further includes:

[0013] A first conductive structure and a second conductive structure are formed in the second dielectric layer at both ends of the semiconductor layer, so as to apply a potential difference to both ends of the semiconductor layer through the first conductive structure and the second conductive structure.

[0014] Optionally, the width of the semiconductor layer in the first direction is less than or equal to the width of the portion of the first through hole located in the substrate in the first direction, and / or the lengths of the semiconductor layer and the first through hole in the second direction are respectively greater than the widths of the semiconductor layer and the first through hole in the first direction; the first direction is perpendicular to the second direction, and the first direction and the second direction are parallel to the first surface of the substrate.

[0015] Optionally, a first insulating layer is formed at least on the bottom of the first through hole, and the first insulating layer seals the first through hole to form an air gap in the first through hole; or, the first insulating layer fills the first through hole.

[0016] Optionally, a second insulating layer is formed on the sidewall of the second through hole, a through hole conductive structure is filled in the second through hole, a third conductive structure is formed in the second dielectric layer, and the third conductive structure is electrically connected to the through hole conductive structure.

[0017] Optionally, the first through hole is only located in the substrate, or the first through hole penetrates the substrate and enters the first dielectric layer, and when the depth of the first through hole changes, the resistance of the semiconductor layer remains unchanged; or the first through hole penetrates the substrate, the first dielectric layer and enters the semiconductor layer, and as the depth of the first through hole in the semiconductor layer gradually increases, the resistance of the semiconductor layer gradually increases; or the first through hole penetrates the substrate, the first dielectric layer and the semiconductor layer, and the resistance of the semiconductor layer is infinite.

[0018] The present invention also provides a semiconductor testing method, comprising:

[0019] Providing a substrate to be tested, wherein a test structure is formed in the substrate to be tested, the test structure comprising a substrate, a first dielectric layer and a semiconductor layer stacked on a first surface of the substrate, a second dielectric layer located on the first surface of the substrate, and a first through hole extending from the second surface of the substrate toward the semiconductor layer, wherein the second dielectric layer further covers the semiconductor layer and the first dielectric layer, and the first surface is opposite to the second surface;

[0020] The resistance variation trend of the semiconductor layer is monitored to obtain the depth variation trend of the first through hole.

[0021] Optionally, a shallow trench isolation structure and a second through hole are formed in the substrate outside the test structure, the shallow trench isolation structure extends from the first surface of the substrate into the substrate, and the second through hole extends from the second surface of the substrate toward the shallow trench isolation structure. The second through hole and the first through hole are formed using the same process, and whether the position of the second through hole in the substrate or the shallow trench isolation structure is within a predetermined range is determined by the depth change trend of the first through hole.

[0022] Optionally, the test structure further includes:

[0023] A first conductive structure and a second conductive structure are formed in the second dielectric layer at both ends of the semiconductor layer, so as to apply a potential difference to both ends of the semiconductor layer through the first conductive structure and the second conductive structure.

[0024] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0025] 1. The semiconductor test structure of the present invention includes a test structure comprising: a substrate; a first dielectric layer and a semiconductor layer stacked on a first surface of the substrate; a second dielectric layer located on the first surface of the substrate, the second dielectric layer also covering the semiconductor layer and the first dielectric layer; and a first through-hole extending from the second surface of the substrate toward the semiconductor layer, with the first surface and the second surface facing away from each other. By monitoring the resistance variation trend of the semiconductor layer, the depth variation trend of the first through-hole is obtained. This enables monitoring of the etching amount during the through-silicon via etching process to avoid batch anomalies in the through-silicon via etching process.

[0026] 2. The semiconductor testing method of the present invention comprises: providing a substrate to be tested, wherein the substrate to be tested has a test structure formed therein, the test structure comprising a substrate, a first dielectric layer and a semiconductor layer stacked on a first surface of the substrate, a second dielectric layer located on the first surface of the substrate, and a first through-hole extending from the second surface of the substrate toward the semiconductor layer, wherein the second dielectric layer also covers the semiconductor layer and the first dielectric layer, and the first surface and the second surface are opposite to each other; and monitoring the resistance variation trend of the semiconductor layer to obtain the depth variation trend of the first through-hole. This enables monitoring the etching amount of the through-silicon via etching process to avoid batch anomalies in the through-silicon via etching process. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1a-1b is a structural schematic diagram of a semiconductor test structure before forming a first through hole and a second through hole according to an embodiment of the present invention;

[0028] Figure 2a-2bis a schematic structural diagram of a semiconductor test structure after forming a first through hole and a second through hole according to an embodiment of the present invention;

[0029] Figure 3 is a flow chart of a semiconductor testing method according to an embodiment of the present invention.

[0030] Among them, Figure 1a to Figure 3 The reference numerals are described as follows:

[0031] 10-substrate; 101-shallow trench isolation structure; 11-first dielectric layer; 12-semiconductor layer; 13-second dielectric layer; 141-first through hole; 142-second through hole; 15-insulating layer; 151-through hole conductive structure; 161-first conductive plug; 162-first conductive layer; 171-second conductive plug; 172-second conductive layer; 181-third conductive plug; 182-third conductive layer. DETAILED DESCRIPTION

[0032] To further clarify the objectives, advantages, and features of the present invention, the semiconductor test structure and semiconductor test method proposed in the present invention are described in further detail below. It should be noted that the accompanying drawings are highly simplified and not to exact scale, and are only used to facilitate and clearly illustrate the objectives of the embodiments of the present invention.

[0033] An embodiment of the present invention provides a semiconductor test structure, including a test structure, wherein the test structure includes: a substrate; a first dielectric layer and a semiconductor layer stacked on a first surface of the substrate; a second dielectric layer located on the first surface of the substrate, the second dielectric layer also covering the semiconductor layer and the first dielectric layer; and a first through-hole extending from the second surface of the substrate toward the semiconductor layer, the first surface being opposite to the second surface, and the depth variation trend of the first through-hole is obtained by monitoring the resistance variation trend of the semiconductor layer.

[0034] See below Figure 1a-1b and Figure 2a-2b The semiconductor test structure provided by this embodiment is described in detail, wherein: Figure 1b yes Figure 1a Schematic diagram of the cross section along the AA' direction, Figure 2b yes Figure 2a A schematic cross-sectional view along the AA' direction; and, in order to facilitate the description of the semiconductor test structure, Figure 1a-1b and Figure 2a-2b A rectangular coordinate system (X, Y, Z) is established in the matrix, wherein the X-axis direction is the first direction, the Y-axis direction is the second direction, and the Z-axis direction is the third direction. The first direction X and the second direction Y are parallel to the first surface of the substrate 10, and the third direction Z is perpendicular to the first surface of the substrate 10.

[0035] Preferably, the test structure is located in a scribe line area of ​​the substrate to be tested, the scribe line area being located between adjacent device areas, and devices can be obtained by cutting along the scribe line area. The substrate to be tested can be a wafer, and the device area can be a chip area. The test structure does not occupy the area of ​​the device area, thereby avoiding affecting the wiring design of the device area, thereby avoiding affecting device performance and increasing production costs.

[0036] In other embodiments, the test structure may also be located in a non-street area of ​​the substrate to be tested.

[0037] The substrate to be tested may be a single-layer substrate or at least two layers of substrates stacked together.

[0038] In the embodiment of the present disclosure, the substrate to be tested includes a substrate 10 and the first dielectric layer 11 , the semiconductor layer 12 , and the second dielectric layer 13 formed on one side of the substrate 10 .

[0039] The substrate 10 may be a single-layer structure or a multi-layer structure composed of the same or different materials. The substrate 10 may be made of a semiconductor material such as Si, SiGe, SiGeC, SiC, GaAs, InAs, InP, and other III / V or II / VI compound semiconductors. It may also include a layered substrate such as Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator. It may also include other materials besides semiconductor materials, which are not limited in this application.

[0040] The first dielectric layer 11 and the semiconductor layer 12 are stacked on the first surface of the substrate 10 .

[0041] The second dielectric layer 13 is located on the first surface of the substrate 10 , and the second dielectric layer 13 also covers the semiconductor layer 12 and the first dielectric layer 11 .

[0042] The first dielectric layer 11 may be located only between the semiconductor layer 12 and the substrate 10; or Figure 1a and Figure 1b As shown, the first dielectric layer 11 may extend laterally from between the semiconductor layer 12 and the substrate 10 to between the second dielectric layer 13 and the substrate 10 .

[0043] The semiconductor layer 12 is made of semiconductor materials, including but not limited to single crystal silicon, polycrystalline silicon, and amorphous silicon.

[0044] The material of the first dielectric layer 11 and the second dielectric layer 13 includes but is not limited to at least one of insulating materials such as silicon oxide, silicon oxynitride and silicon nitride. The first dielectric layer 11 and / or the second dielectric layer 13 can be a single layer or a stack of at least two layers of the same or different materials.

[0045] The first through hole 141 extends from the second surface of the substrate 10 toward the semiconductor layer 12 . The first surface is opposite to the second surface. The depth variation trend of the first through hole 141 is obtained by monitoring the resistance variation trend of the semiconductor layer 12 .

[0046] The first surface is the front side of the substrate 10 , and the second surface is the back side of the substrate 10 ; or the first surface is the back side of the substrate 10 , and the second surface is the front side of the substrate 10 .

[0047] The first through-hole 141 is formed in the substrate 10 using any method known in the art. For example, the first through-hole 141 is formed by an etching process. In actual production, the etching amount of each layer structure may vary due to the fluctuation of the etching process. That is, the depth of the first through-hole 141 may vary due to the fluctuation of the etching process. As a result, the position of the bottom of the first through-hole 141 in the substrate 10, the first dielectric layer 11, or the semiconductor layer 12 may vary, resulting in different etching conditions for the substrate 10, the first dielectric layer 11, or the semiconductor layer 12. For example, the first through-hole 141 may be located only in the substrate 10, or the first through-hole 141 may penetrate the substrate 10 and enter the first dielectric layer 11, or the first through-hole 141 may penetrate the substrate 10, the first dielectric layer 11, and enter the semiconductor layer 12, or the first through-hole 141 may penetrate the substrate 10, the first dielectric layer 11, and the semiconductor layer 12. Among them, before the first through hole 141 enters the semiconductor layer 12, since the semiconductor layer 12 has not been etched, when the depth of the first through hole 141 changes, the resistance of the semiconductor layer 12 remains unchanged; after the first through hole 141 enters the semiconductor layer 12, since the semiconductor layer 12 is etched, the height of the semiconductor layer 12 decreases, and then as the depth of the first through hole 141 in the semiconductor layer 12 gradually increases, that is, as the height of the semiconductor layer 12 gradually decreases, the resistance of the semiconductor layer 12 gradually increases; when the first through hole 141 penetrates the semiconductor layer 12, the measured resistance of the semiconductor layer 12 is infinite.

[0048] In one embodiment, after the resistance R of the semiconductor layer 12 is measured, since the resistivity ρ, the length L in the second direction Y, the width in the first direction X, and the height in the third direction Z of the semiconductor layer 12 are known during design, the height of the semiconductor layer 12 remaining after etching is completed (i.e., after the first through hole 141 is formed) can be calculated according to the calculation formula of the resistance R: R=ρ*L / S, where S is the cross-sectional area of ​​the semiconductor layer 12, and S is the product of the width and height of the semiconductor layer 12.

[0049] Moreover, since the heights of the substrate 10, the first dielectric layer 11 and the semiconductor layer 12 in the third direction Z before etching are known during design, the depth of the first through hole 141 in the semiconductor layer 12 and the depth of the first through hole 141 can be calculated based on the height of the semiconductor layer 12 remaining after etching obtained by the above calculation, thereby realizing the monitoring of the depth change trend of the first through hole 141 by monitoring the resistance change trend of the semiconductor layer 12.

[0050] A shallow trench isolation structure 101 and a second through-hole 142 are formed in the substrate 10 at the periphery of the test structure, and the periphery of the test structure is other locations in the cutting path area of ​​the substrate to be tested, or the device area of ​​the substrate to be tested. For example, in the device area of ​​the substrate to be tested, the device area also includes the substrate 10 and the second dielectric layer 13, and a shallow trench isolation structure 101 and a second through-hole 142 are formed in the substrate 10 of the device area, wherein the shallow trench isolation structure 101 extends from the first surface of the substrate 10 into the substrate 10, and the second through-hole 142 extends from the second surface of the substrate 10 toward the shallow trench isolation structure 101. The second through-hole 142 and the first through-hole 141 are formed using the same process, so that it is possible to determine whether the position of the second through-hole 142 in the substrate 10 or the shallow trench isolation structure 101 is within a predetermined range based on the depth variation trend of the first through-hole 141. The predetermined range refers to the stopping position of the second through hole 142 in the substrate 10 or the shallow trench isolation structure 101 when the second through hole 142 is formed, whether it stops at a suitable position, for example, whether it stops inside the shallow trench isolation structure 101 (the second through hole 142 enters the shallow trench isolation structure 101 and does not penetrate the shallow trench isolation structure 101).

[0051] A plurality of second through holes 142 need to be made at different positions of the substrate 10, and the second through holes 142 at different positions need to at least penetrate the substrate 10 to expose the shallow trench isolation structure 101. However, due to factors such as differences in the height of the shallow trench isolation structure 101 in the substrate 10 at different positions and fluctuations in the etching process, when the plurality of second through holes 142 are formed using the same etching process, some of the second through holes 142 may not expose the shallow trench isolation structure 101. To avoid this, the substrate 10 needs to be over-etched when etching to form the second through holes 142, and the amount of over-etching needs to be controlled within a certain range to ensure the stability of the etching process, avoid the situation where the amount of over-etching is too little, resulting in some of the second through holes 142 still not exposing the shallow trench isolation structure 101, and avoid the situation where the amount of over-etching is too much (for example, etching through the shallow trench isolation structure 101) and affecting the electrical performance.

[0052] Since the heights of the substrate 10, the shallow trench isolation structure 101, the first dielectric layer 11, and the semiconductor layer 12 in the third direction Z before etching are known during design, and the etching selectivity ratios of the shallow trench isolation structure 101 to the substrate 10, the first dielectric layer 11, and the semiconductor layer 12 are also known during design, the depth of the second through hole 142 in the shallow trench isolation structure 101 after etching, and the depth of the second through hole 142, can be calculated based on the depth of the first through hole 141 after etching is completed, and the depth of the second through hole 142 can also be calculated. Therefore, it is possible to determine whether the position of the second through hole 142 in the substrate 10 or the shallow trench isolation structure 101 is within a predetermined range by measuring the depth of the first through hole 141, and to determine the depth change trend of the second through hole 142 by monitoring the depth change trend of the first through hole 141, thereby achieving the purpose of monitoring the stability and specific etching amount of the silicon via etching process in the periphery of the test structure (for example, the device area) by setting the test structure in the cutting lane area, so as to avoid batch abnormalities in the silicon via etching process in the device area.

[0053] In other embodiments, the stability of the through silicon via etching process can be directly monitored by directly using the measured change trend of the resistance of the semiconductor layer 12, so that there is no need to calculate the specific etching amount, that is, there is no need to calculate the specific depths of the first through hole 141 and the second through hole 142.

[0054] In one embodiment, a potential difference may be applied to both ends of the semiconductor layer 12, and the current may be measured to calculate the resistance of the semiconductor layer 12 by dividing the potential difference by the current. The two ends of the semiconductor layer 12 may be the two ends of the semiconductor layer 12 in the second direction Y.

[0055] In one embodiment, applying a potential difference to both ends of the semiconductor layer 12 may include: connecting one end of the semiconductor layer 12 to a positive voltage, and connecting the other end of the semiconductor layer 12 to a negative voltage or grounding.

[0056] Preferably, the width of the semiconductor layer 12 in the first direction X is less than or equal to the width of the portion of the first through hole 141 located in the substrate 10 in the first direction X, so as to avoid the width of the semiconductor layer 12 in the first direction X being too large, resulting in the depth change of the first through hole 141 in the semiconductor layer 12 having too little effect on the resistance change of the semiconductor layer 12, thereby avoiding inaccurate resistance change test of the semiconductor layer 12 and inaccurate depth calculation result of the first through hole 141; and / or, the lengths of the semiconductor layer 12 and the first through hole 141 in the second direction Y are respectively greater than the widths of the semiconductor layer 12 and the first through hole 141 in the first direction X, so that the total resistance of the semiconductor layer 12 increases and the influence of the depth change of the first through hole 141 in the semiconductor layer 12 on the resistance change of the semiconductor layer 12 increases, thereby making the resistance change test of the semiconductor layer 12 more accurate, and thus making the calculation result of the depth of the first through hole 141 more accurate.

[0057] The length of the semiconductor layer 12 in the second direction Y may be greater than, equal to, or less than the length of the first through hole 141 in the second direction Y.

[0058] In a cross section parallel to the first surface or the second surface of the substrate 10 , the cross section of the semiconductor layer 12 may be a straight line or a curved line.

[0059] The test structure further includes a first conductive structure and a second conductive structure formed in the second dielectric layer 13 at both ends of the semiconductor layer 12 , so as to apply a potential difference to both ends of the semiconductor layer 12 through the first conductive structure and the second conductive structure.

[0060] The first conductive structure may include at least one first conductive plug 161 and at least one first conductive layer 162. The first conductive layer 162 is electrically connected to the semiconductor layer 12 via the first conductive plug 161. The first conductive layers 162 in adjacent layers are also electrically connected via the first conductive plug 161. The first conductive layer 162 farthest from the substrate 10 may be located on the surface of the second dielectric layer 13. The second conductive structure may include at least one second conductive plug 171 and at least one second conductive layer 172. The second conductive layer 172 is electrically connected to the semiconductor layer 12 via the second conductive plug 171. The second conductive layers 172 in adjacent layers are also electrically connected via the second conductive plug 171. The second conductive layer 172 farthest from the substrate 10 may be located on the surface of the second dielectric layer 13.

[0061] A second insulating layer is formed on the sidewall of the second through hole 142 . The second through hole 142 is filled with a through hole conductive structure 151 . A third conductive structure is formed in the second dielectric layer 13 . The third conductive structure is electrically connected to the through hole conductive structure 151 .

[0062] The third conductive structure may include at least one third conductive plug 181 and at least one third conductive layer 182. The third conductive layer 182 is electrically connected to the through-hole conductive structure 151 through the third conductive plug 181. The third conductive layers 182 of adjacent layers are also electrically connected through the third conductive plug 181. The third conductive layer 182 farthest from the substrate 10 may be located on the surface of the second dielectric layer 13, and the third conductive plug 181 closest to the substrate 10 may enter the shallow trench isolation structure 101.

[0063] The widths of the second through hole 142 and the first through hole 141 may be the same or different.

[0064] A first insulating layer is formed at least at the bottom of the first through-hole 141. The first insulating layer seals the first through-hole 141 to form an air gap in the first through-hole 141; alternatively, the first insulating layer completely fills the first through-hole 141. Therefore, when the second insulating layer at the bottom wall of the second through-hole 142 and the underlying shallow trench isolation structure 101 are etched to expose the third conductive structure, the first insulating layer in the first through-hole 141 can protect the semiconductor layer 12 at the bottom wall of the first through-hole 141 from being etched, thereby preventing the subsequent test results of the resistance of the semiconductor layer 12 from being affected, thereby preventing the depth assessment of the first through-hole 141 from being affected.

[0065] Preferably, the first insulating layer and the second insulating layer are made of the same material and formed by the same process, so as to simplify the process steps.

[0066] In one embodiment, after etching to form the first through-hole 141 and the second through-hole 142, an insulating layer 15 is formed in the first through-hole 141 and on the sidewalls and bottom wall of the second through-hole 142. The insulating layer 15 may also extend to the second surface of the substrate 10. Then, the insulating layer 15 on the bottom wall of the second through-hole 142 and the shallow trench isolation structure 101 thereunder are etched to expose the third conductive structure. Then, the through-hole conductive structure 151 is filled in the second through-hole 142, and the through-hole conductive structure 151 also extends to electrically connect with the exposed third conductive structure. The insulating layer 15 in the first through-hole 141 serves as the first insulating layer, and the insulating layer 15 on the sidewalls and bottom wall of the second through-hole 142 serves as the second insulating layer.

[0067] In one embodiment, the through-hole conductive structure 151 may further extend to the second surface of the substrate 10 .

[0068] The material of the first insulating layer and the second insulating layer includes but is not limited to at least one of insulating materials such as silicon oxide, silicon oxynitride and silicon nitride.

[0069] As can be seen from the foregoing, the semiconductor test structure provided by the present invention includes a test structure comprising: a substrate; a first dielectric layer and a semiconductor layer stacked on a first surface of the substrate; a second dielectric layer located on the first surface of the substrate, the second dielectric layer also covering the semiconductor layer and the first dielectric layer; and a first through-hole extending from the second surface of the substrate toward the semiconductor layer, with the first surface and the second surface facing away from each other. By monitoring the resistance variation trend of the semiconductor layer, the depth variation trend of the first through-hole is obtained. The semiconductor test structure provided by the present invention can monitor the etching amount of a through-silicon via (TSV) etching process to avoid batch anomalies in the TSV etching process.

[0070] Based on the same inventive concept, an embodiment of the present invention provides a semiconductor testing method, referring to Figure 3 ,from Figure 3 As can be seen from FIG, the semiconductor testing method includes:

[0071] Step S1, providing a substrate to be tested, wherein a test structure is formed in the substrate to be tested, the test structure comprising a substrate, a first dielectric layer and a semiconductor layer stacked on a first surface of the substrate, a second dielectric layer located on the first surface of the substrate, and a first through hole extending from the second surface of the substrate toward the semiconductor layer, wherein the second dielectric layer further covers the semiconductor layer and the first dielectric layer, and the first surface and the second surface are opposite to each other;

[0072] Step S2: monitoring the resistance variation trend of the semiconductor layer to obtain the depth variation trend of the first through hole.

[0073] See below Figure 1a-1b and Figure 2a-2b The semiconductor testing method provided by this embodiment is described in detail, wherein: Figure 1b yes Figure 1a Schematic diagram of the cross section along the AA' direction, Figure 2b yes Figure 2a A schematic cross-sectional view along the AA' direction; and, in order to facilitate the description of the semiconductor test method, Figure 1a-1b and Figure 2a-2b A rectangular coordinate system (X, Y, Z) is established in the matrix, wherein the X-axis direction is the first direction, the Y-axis direction is the second direction, and the Z-axis direction is the third direction. The first direction X and the second direction Y are parallel to the first surface of the substrate 10, and the third direction Z is perpendicular to the first surface of the substrate 10.

[0074] According to step S1, a substrate to be tested is provided, wherein a test structure is formed on the substrate to be tested. The test structure includes a substrate 10, a first dielectric layer 11 and a semiconductor layer 12 stacked on a first surface of the substrate 10, a second dielectric layer 13 located on the first surface of the substrate 10, and a first through hole 141 extending from the second surface of the substrate 10 toward the semiconductor layer 12. The second dielectric layer 13 also covers the semiconductor layer 12 and the first dielectric layer 11, and the first surface and the second surface are opposite to each other.

[0075] The test structure can be found in the above detailed description of the test structure in the semiconductor test structure of the present invention, which will not be described again here.

[0076] According to step S2, the resistance variation trend of the semiconductor layer 12 is monitored to obtain the depth variation trend of the first through hole 141. The specific process is described in detail above with respect to the semiconductor test structure of the present invention, which will not be repeated here.

[0077] As can be seen from the above, the semiconductor testing method provided by the present invention includes: providing a substrate to be tested, wherein the substrate to be tested has a test structure formed therein, the test structure comprising a substrate, a first dielectric layer and a semiconductor layer stacked on a first surface of the substrate, a second dielectric layer located on the first surface of the substrate, and a first through-hole extending from the second surface of the substrate toward the semiconductor layer, wherein the second dielectric layer also covers the semiconductor layer and the first dielectric layer, and the first surface and the second surface are opposite to each other; monitoring the resistance variation trend of the semiconductor layer to obtain the depth variation trend of the first through-hole. The semiconductor testing method provided by the present invention can monitor the etching amount of the through-silicon via etching process to avoid batch anomalies in the through-silicon via etching process.

[0078] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A semiconductor test structure, characterized in that: A test structure is included, the test structure including: substrate; A first dielectric layer and a semiconductor layer are stacked on the first surface of the substrate; a second dielectric layer, located on the first surface of the substrate, the second dielectric layer also covering the semiconductor layer and the first dielectric layer; The first through hole extends from the second surface of the substrate toward the semiconductor layer, the first surface and the second surface are opposite to each other, and the depth variation trend of the first through hole is obtained by monitoring the resistance variation trend of the semiconductor layer.

2. The semiconductor test structure according to claim 1, wherein: A shallow trench isolation structure and a second through-hole are formed in the substrate outside the test structure. The shallow trench isolation structure extends from the first surface of the substrate into the substrate, and the second through-hole extends from the second surface of the substrate toward the shallow trench isolation structure. The second through-hole and the first through-hole are formed using the same process. Whether the position of the second through-hole in the substrate or the shallow trench isolation structure is within a predetermined range is determined by the depth change trend of the first through-hole.

3. The semiconductor test structure according to claim 1, wherein: The test structure also includes: A first conductive structure and a second conductive structure are formed in the second dielectric layer at both ends of the semiconductor layer, so as to apply a potential difference to both ends of the semiconductor layer through the first conductive structure and the second conductive structure.

4. The semiconductor test structure according to claim 1, wherein: The width of the semiconductor layer in the first direction is less than or equal to the width of the portion of the first through hole located in the substrate in the first direction, and / or the lengths of the semiconductor layer and the first through hole in the second direction are respectively greater than the widths of the semiconductor layer and the first through hole in the first direction; the first direction is perpendicular to the second direction, and the first direction and the second direction are parallel to the first surface of the substrate.

5. The semiconductor test structure according to claim 1, wherein: A first insulating layer is formed at least on the bottom of the first through hole, and the first insulating layer seals the first through hole to form an air gap in the first through hole; or the first insulating layer fills the first through hole.

6. The semiconductor test structure according to claim 2, wherein: A second insulating layer is formed on the sidewall of the second through hole, a through hole conductive structure is filled in the second through hole, a third conductive structure is formed in the second dielectric layer, and the third conductive structure is electrically connected to the through hole conductive structure.

7. The semiconductor test structure according to claim 1, wherein: The first through hole is located only in the substrate, or the first through hole penetrates the substrate and enters the first dielectric layer, and when the depth of the first through hole changes, the resistance of the semiconductor layer remains unchanged; or the first through hole penetrates the substrate, the first dielectric layer, and enters the semiconductor layer, and as the depth of the first through hole in the semiconductor layer gradually increases, the resistance of the semiconductor layer gradually increases; or the first through hole penetrates the substrate, the first dielectric layer, and the semiconductor layer, and the resistance of the semiconductor layer is infinite.

8. A semiconductor testing method, characterized in that: include: Providing a substrate to be tested, wherein a test structure is formed in the substrate to be tested, the test structure comprising a substrate, a first dielectric layer and a semiconductor layer stacked on a first surface of the substrate, a second dielectric layer located on the first surface of the substrate, and a first through hole extending from the second surface of the substrate toward the semiconductor layer, wherein the second dielectric layer further covers the semiconductor layer and the first dielectric layer, and the first surface is opposite to the second surface; The resistance variation trend of the semiconductor layer is monitored to obtain the depth variation trend of the first through hole.

9. The semiconductor testing method according to claim 8, wherein: A shallow trench isolation structure and a second through-hole are formed in the substrate outside the test structure. The shallow trench isolation structure extends from the first surface of the substrate into the substrate, and the second through-hole extends from the second surface of the substrate toward the shallow trench isolation structure. The second through-hole and the first through-hole are formed using the same process. Whether the position of the second through-hole in the substrate or the shallow trench isolation structure is within a predetermined range is determined by the depth change trend of the first through-hole.

10. The semiconductor testing method according to claim 8, wherein: The test structure also includes: A first conductive structure and a second conductive structure are formed in the second dielectric layer at both ends of the semiconductor layer, so as to apply a potential difference to both ends of the semiconductor layer through the first conductive structure and the second conductive structure.

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