A random modulation clock spread spectrum device and switching power supply chip

Abstract

The application discloses a random modulation clock spread spectrum device and a power supply chip, wherein the device comprises a random modulation clock spread spectrum device, characterized in that comprising: a frequency divider circuit used for receiving a first pulse signal output by an oscillator circuit in a t-1 modulation period; an M sequence generation circuit used for generating a random digital sequence of the t-1 modulation period according to the first pulse signal; wherein the period of the random digital sequence is 2 n , n is an integer greater than or equal to 4; a current bias circuit used for generating a first bias current of the t-1 modulation period according to the random digital sequence; and an oscillator circuit used for generating a clock spread spectrum signal of a t modulation period according to the first bias current, t being an integer greater than or equal to 2. The application can be widely applied in the technical field of electronic circuits.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic circuits, and particularly relates to a clock spread spectrum device with random modulation and a switching power supply chip. BACKGROUND

[0002] At present, a common method for reducing EMI of a switching power supply chip is to use a clock spread spectrum technology with periodic modulation. The clock spread spectrum technology with periodic modulation uses a periodic waveform as a modulation waveform to modulate a clock generation circuit, so that a fixed frequency clock is dithered within a certain range. The clock signal is changed from numerical discrete and energy concentrated to numerical continuous and energy average in the frequency domain, thereby achieving the goal of reducing EMI related to the switching frequency in the circuit.

[0003] However, although the clock spread spectrum technology with periodic modulation can achieve the goal of reducing EMI related to the switching frequency in the circuit, at the same time, it generates audible frequencies that can be heard by the human ear, which greatly reduces the application scenarios of the product. Therefore, there are still technical problems to be solved in the related art. SUMMARY

[0004] The present application aims to at least partly solve one of the technical problems in the prior art.

[0005] To this end, one purpose of an embodiment of the present application is to provide a clock spread spectrum device with random modulation and a switching power supply chip, which can reduce the generation of audible frequencies that can be heard by the human ear and improve the practicality of related products.

[0006] In order to achieve the above technical purpose, the technical solution adopted by the embodiment of the present application comprises: a clock spread spectrum device with random modulation, comprising: a frequency divider circuit configured to receive a first pulse signal output by an oscillator circuit in a t-1 modulation period; an M sequence generation circuit configured to generate a random digital sequence of a t-1 modulation period according to the first pulse signal; wherein the random digital sequence is a random digital sequence of 2 n n periods, and n is an integer greater than or equal to 4; a current bias circuit configured to generate a first bias current of a t-1 modulation period according to the random digital sequence; and an oscillator circuit configured to generate a clock spread spectrum signal of a t modulation period according to the first bias current.

[0007] In addition, the clock spread spectrum device with random modulation according to the above-mentioned embodiment of the present application can further have the following additional technical features:

[0008] Further, in the embodiment of the present application, the M sequence generation circuit comprises a sequence generation network and a feedback network.

[0009] The feedback network comprises a logic processing module and n-T D flip-flops;

[0010] The sequence generation network comprises T D flip-flops; the sequence generation network is used to generate a random digital reverse sequence of t-2 modulation periods; the random digital reverse sequence is a digital sequence obtained by performing logical NOT operation on the output signal of each D flip-flop in the T D flip-flops in the t-2 modulation periods;

[0011] The n-T D flip-flops are used to generate a first feedback signal set of t-1 modulation periods according to a pulse signal of t-2 modulation periods;

[0012] The logic processing module is used to perform logical conversion processing on the first feedback signal set and the random digital reverse sequence to obtain a second feedback signal output to the sequence generation network in t-1 modulation periods;

[0013] The sequence generation network is further used to generate the random digital sequence according to the first pulse signal and the second feedback signal; wherein the random digital sequence is a digital sequence composed of the output signal of each D flip-flop in the T D flip-flops.

[0014] Further, in the embodiment of the application, the current bias circuit comprises a decoder and a current converter;

[0015] The decoder is used to convert the random digital sequence into a target driving signal of t-1 modulation periods;

[0016] The current converter is used to convert the target driving signal into a first bias current of t-1 modulation periods.

[0017] Further, in the embodiment of the application, the current converter comprises:

[0018] a current generation module, two T resistance modules and a resistance selection module; the current generation module is connected with the resistance selection module; the resistance selection module is used to determine any one resistance module and the current generation module to form a closed loop and form the first bias current from the two T resistance modules according to the target driving signal.

[0019] Further, in the embodiment of the application, the resistance values of any two resistance modules in the T resistance modules are different.

[0020] Further, in the embodiment of the application, the decoder is used to convert T signals into a 2 T bit binary number and output a target driving signal corresponding to the 2 T bit binary number.

[0021] Further, in the embodiment of the present application, the frequency divider circuit comprises Y frequency dividers; any two adjacent frequency dividers in the Y frequency dividers are connected in series with each other; wherein Y is a positive integer greater than or equal to 2.

[0022] Further, in the embodiment of the present application, the oscillator circuit comprises two current mirror modules connected in parallel with each other, a gating module, an energy storage module and an inverter module.

[0023] The current mirror module is configured to receive the first bias current and generate a charging current with a t modulation period.

[0024] The gating module is configured to gate any one of the current mirror modules in the t modulation period and charge the energy storage module by the charging current.

[0025] The inverter module is configured to generate a control signal according to the voltage of the energy storage module, so that the gating module gates another current mirror module in the t modulation period, charges the energy storage module by the charging current, and generates a clock spread spectrum signal with a t modulation period.

[0026] The feedback network comprises a logic processing module and four D flip-flops; the sequence generation network comprises four D flip-flops; the second feedback signal satisfies the following formula:

[0027]

[0028] wherein F is the second feedback signal, B1', B2', B3', B4' are outputs of the Q' end of each D flip-flop in the random digital reverse sequence, B5', B6', B7', B8' are outputs of the Q' end of each D flip-flop in the first feedback signal set, B5, B6, B8 are outputs of the Q end of each D flip-flop in the first feedback signal set; B1'B2'B3'B4'B5'B6'B7'B8'in the formula represents that B1', B2', B3', B4', B5', B6', B7', B8' are subjected to AND operation two by two; the symbol ⊕ represents XOR operation, and the symbol + represents OR operation.

[0029] In addition, the present application also provides a switching power supply chip comprising the random modulation clock spread spectrum device according to any one of the preceding embodiments.

[0030] The advantages and beneficial effects of the present application will be partially given in the following description, partially will become obvious from the following description, or will be understood by the practice of the present application:

[0031] The application can generate a random number sequence with 2n periods of t-1 modulation periods through the M sequence generation circuit, and use the random number sequence for subsequent clock spread spectrum modulation, so that the circuit reduces the risk of generating audible frequency. The application can reduce the possibility of generating audible frequency by the random modulation clock spread spectrum device, and improve the practicability of the device product, because the random number sequence generated by the M sequence generation circuit has the pseudo-random characteristics of balance characteristics and run characteristics, so that the period of the modulation signal is not fixed. BRIEF DESCRIPTION OF DRAWINGS

[0032] Figure 1 Waveform diagram of EMI problem of prior art switching power supply;

[0033] Figure 2 Time domain diagram of period modulation clock spread spectrum technology in prior art;

[0034] Figure 3 Module diagram of random modulation clock spread spectrum device in a specific embodiment of the application;

[0035] Figure 4 Circuit structure diagram of random modulation clock spread spectrum device in a specific embodiment of the application;

[0036] Figure 5 Module diagram of random modulation clock spread spectrum device in another specific embodiment of the application. DETAILED DESCRIPTION

[0037] The following describes the random modulation clock spread spectrum device in the embodiment of the application, and the principle and process of the switching power supply chip, in combination with the drawings.

[0038] The following describes the terms appearing in the application:

[0039] The common method for reducing the EMI of the switching power supply chip at present is to use the period modulation clock spread spectrum technology. This technology uses a period waveform as a modulation waveform to modulate the clock generation circuit, so that the clock with fixed frequency is dithered within a certain range, and the clock signal in the frequency domain changes from discrete values and concentrated energy to continuous values and average energy, thereby reducing the EMI problem related to the switching frequency in the circuit.

[0040] Referring to Figure 1 and Figure 2 , Figure 1 is an EMI energy spectrum diagram of a switching power supply. In Figure 1In the figure, the dashed line is the noise distribution curve of the constant frequency clock, and the solid line is the noise distribution curve of the clock modulated by the spread spectrum technology. The unmodulated clock noise spectrum energy distribution is narrow, the energy is concentrated, and the energy peak value reaches A at fclk(clock frequency). The clock modulated by the spread spectrum technology has frequency fluctuation, so the noise spectrum is wide, the energy distribution is average, and the energy peak value is reduced from A to Ae. Figure 2 is a timing diagram of the clock spread spectrum technology of periodic modulation. The principle is to modulate the clock generation circuit with a constant period modulation waveform, so that the clock frequency changes periodically with the modulation waveform, so that the performance in the frequency domain changes from discrete values to continuous values, and the energy is evenly distributed, achieving the goal of improving and optimizing the EMI problem of the switching power supply.

[0041] However, the clock spread spectrum technology using periodic waveform as the modulation waveform has the disadvantage of producing audible frequency. Specifically, to ensure that the clock frequency jitter range is small and the EMI is significantly reduced, a lower modulation frequency is required. When the modulation frequency is lower than 20kHz, the sound that human ears can hear is produced, which greatly reduces the product application scenario. For example, a triangular modulation wave generating circuit suitable for fixed-frequency Buck spread spectrum mode (CN114629344B) is disclosed. The patent uses a periodic wave of triangular waveform to modulate the clock generation circuit. The patent method mentions that the modulation frequency needs to be around 10kHz, but this frequency is within the frequency range that human ears can hear, which greatly reduces the product application scenario. Therefore, there are still problems in related technologies that need to be solved.

[0042] In view of the defects of the above prior art, with reference to Figure 3 , Figure 3 is a structure diagram of a random modulation clock spread spectrum device provided by an embodiment of the present application. In Figure 3 , the random modulation clock spread spectrum device can include a frequency divider circuit 1, an M sequence generation circuit 2, a current bias circuit 3, and an oscillator circuit 4. The frequency divider circuit 1 can be used to receive the first pulse signal output by the oscillator circuit 4 in the t-1 modulation period. Specifically, in the current modulation period, the frequency divider circuit 1 can receive the pulse signal of the last period of the current modulation period. The M sequence generation circuit 2 can be used to generate a random digital sequence in the t-1 modulation period according to the first pulse signal. Specifically, the M sequence generation circuit 2 can generate a random digital sequence in the last modulation period according to the first pulse signal of the last modulation period. Wherein, the random digital sequence is a period of 2 n , n can be an integer greater than or equal to 4, and the random digital sequence is a period of 2 nThe all-zero state also means an output state of the random digital sequence. The current biasing circuit 3 can be configured to generate a first biasing current of a t-1th modulation period according to the random digital sequence. Specifically, the current biasing circuit 3 can generate the first biasing current of the t-1th modulation period according to the random digital sequence of a previous modulation period. The oscillator circuit 4 can be configured to generate a clock spread spectrum signal of a tth modulation period according to the first biasing current. Specifically, the oscillator circuit 4 can generate the clock spread spectrum signal of the tth modulation period according to the first biasing current of the previous modulation period. The tth modulation period and the t-1th modulation period can be two adjacent modulation periods.

[0043] Further, the M-sequence generating circuit includes a sequence generating network and a feedback network. The feedback network includes a logic processing module and n-T D flip-flops. The sequence generating network includes T D flip-flops. The sequence generating network is configured to generate a random digital anti-sequence of a t-2th modulation period. The random digital anti-sequence is a digital sequence obtained by performing a logical NOT operation on an output signal of each of the T D flip-flops in the t-2th modulation period. The n-T D flip-flops are configured to generate a first feedback signal set of a t-1th modulation period according to a pulse signal of the t-2th modulation period. The logic processing module is configured to perform a logical conversion process on the first feedback signal set and the random digital anti-sequence to obtain a second feedback signal output to the sequence generating network in the t-1th modulation period. The sequence generating network is configured to generate a random digital sequence according to the first pulse signal and the second feedback signal. The random digital sequence is a digital sequence composed of output signals of each of the T D flip-flops.

[0044] Specifically, referring to Figure 4 , in Figure 4 , n is 8, T is 4, the feedback network can include Figure 4 four flip-flops with serial numbers B5-B8, a first AND gate AND1, a second AND gate AND2, a third AND gate AND3, a NAND gate NAND1, a first OR gate OR1, a first XOR gate XOR1, and a second XOR gate XOR2. The sequence generating network can include four flip-flops B1-B4. In Figure 4In the embodiment, the D terminal of the D flip-flop numbered B1 is connected with the output of the first OR gate OR1 in the feedback network, and the D terminals of B2-B8 are all connected with the Q terminal of the D flip-flop in the previous stage, so that B1-B8 form a cascade structure. The 4 Q terminal outputs of the flip-flops B1-B4, the 3 Q terminal outputs of B5, B6 and B8, and the 4 Q' terminal outputs of B5'-B8' altogether 11 terminal outputs can be used as the input signals of the logic operation of the feedback network. The clock signals of the 8 D flip-flops of B1-B8 are all derived from the signal output of the frequency divider circuit. When the signal modulation is performed in t modulation periods, the flip-flops B1-B4 of the sequence generation network can generate a random digital reverse sequence composed of B1'-B4' in t-2 modulation periods; the 4 D flip-flops of B5-B8 can generate a first feedback signal set in t-1 modulation periods according to the pulse signal from the frequency divider in t-2 modulation periods. The first feedback signal set includes the 3 Q terminal outputs of B5, B6 and B8, and the 4 Q' terminal outputs of B5'-B8'. The logic processing module can perform logic conversion processing on the 3 Q terminal outputs of B5, B6 and B8, the 4 Q' terminal outputs of B5'-B8', and the random digital reverse sequence composed of B1'-B4' in t-1 modulation periods, to obtain a second feedback signal F output to the sequence generation network in t-1 modulation periods. The sequence generation network can generate the Q terminal outputs of the 4 D flip-flops of B1-B4 in t modulation periods according to the first pulse signal of the frequency divider output in t modulation periods and the second feedback signal F in t-1 modulation periods.

[0045] The logic of generating the random digital sequence: the OSC clock passes through the frequency divider to generate a clock signal CLK_div, which is connected to the CLK pin of all the D flip-flops in the M sequence generation circuit module. When the rising edge of CLK comes, the data of the D flip-flop of the M sequence generation circuit module is shifted to the right by 1 time. The input of the leftmost D flip-flop, i.e. the first D flip-flop, is the output of the logic circuit. The input of the logic circuit is the Q terminal of part of the D flip-flop (random digital reverse sequence), and the output is 1-bit data, which is connected to the first D flip-flop.

[0046] The overall action can be summarized as follows: several D flip-flops always shift data from left to right, and the feedback network combines the data of the several D flip-flops to obtain a result, which is fed to the first D flip-flop, so as to realize the pseudo-random sequence when there are multiple-bit D flip-flops.

[0047] Further, the current bias circuit includes a decoder and a current converter; the decoder can convert the random digital sequence into a target driving signal in t-1 modulation periods. The current converter can convert the target driving signal into a first bias current in t-1 modulation periods.

[0048] Specifically, referring to Figure 4, the input of the decoder is the Q terminal output of the four D flip-flops B1-B4, and the output terminal is a 2 4 bit digital signal, that is, a 16-bit digital signal. Specifically, when the Q terminals of the four D flip-flops B1-B4 respectively output four signals 1001 (binary representation of the decimal number 9), the output of the decoder is 0000000010000000, that is, the 9th port of the decoder outputs a high level. Similarly, when the Q terminals of the four D flip-flops B1-B4 respectively output four signals 0111 (binary representation of the decimal number 7), the output of the decoder is 0000001000000000, that is, the 7th port of the decoder outputs a high level. The current converter can convert the output of the decoder into the current of the circuit and make the current transmitted to the oscillator circuit. Specifically, each output terminal of the decoder can be connected to a resistance selection module. The resistance selection module can include a plurality of NMOS tubes equal to the number of output terminals of the decoder. The gate of an NMOS tube connected to each output terminal of the decoder can be grounded, and the drain of each NMOS tube can be connected to a current generating module. Figure 3 In the current generating module, the current generating module can be composed of an operational amplifier OP1, two serially connected field effect tubes and a resistor Rb. Between each NMOS tube and the current generating module, a resistance module equal to the number of output terminals of the decoder is further provided, and the number of resistors in each resistance module can be different or the same, and the resistance value of each resistance module can be different. Figure 3 In the current generating module, the current generating module can be composed of an operational amplifier OP1, two serially connected field effect tubes and a resistor Rb. Between each NMOS tube and the current generating module, a resistance module equal to the number of output terminals of the decoder is further provided, and the number of resistors in each resistance module can be different or the same, and the resistance value of each resistance module can be different.

[0049] Further, the frequency divider circuit includes Y two-dividers. Any two adjacent two-dividers in the Y two-dividers are connected in series; wherein Y is a positive integer greater than or equal to 2.

[0050] Specifically, in the Figure 4 , the number of two-dividers is 8, which are A1-A8. In any two adjacent two-dividers among A1-A8, the output terminal of the previous two-divider is the input terminal of the current two-divider. In the Figure 4 , the output terminal of the two-divider A1 is the clock terminal of the two-divider A2, and the output terminal of the last two-divider A8 is the output terminal of the frequency divider circuit and outputs the first pulse signal of the M sequence generation circuit.

[0051] It can be understood that the number of frequency dividers in the frequency divider circuit can be designed according to user requirements. The specific number is not limited here.

[0052] Further, the oscillator circuit can include two current mirror modules connected in parallel with each other, a gating module, an energy storage module, and an inverter module; the current mirror modules can receive a first bias current and generate a charging current of a t modulation period. The gating module can gate any one of the current mirror modules in the t modulation period, and charge the energy storage module through the charging current. The inverter module can generate a control signal according to the voltage of the energy storage module, so that the gating module gates the other current mirror module in the t modulation period, charges the energy storage module through the charging current, and generates a clock spread spectrum signal of the t modulation period.

[0053] Specifically, in Figure 4 , one current mirror module can include four field effect tubes T1, T2, T3, and T4. The other current mirror module can include four field effect tubes T5, T6, T7, and T8. The gating module can include two on-transmission gates G1 and G2. The energy storage module can include a capacitor C1. The inverter module can include two inverters D1 and D2 connected in series.

[0054] The oscillator circuit is described as follows:

[0055] The left T1, T3, T5, T7 is a branch for generating a bias voltage for the right T2, T4, G1, G2, T6, T8, the gate end of T1 is connected to the PMOS gate end of the bias circuit, which is equivalent to copying the current of the bias circuit, T3, T5, T7 are connected to the gate end and the drain end, so as to determine VGS according to the current flowing through, thereby providing a bias voltage;

[0056] The middle node of the right T2, T4, G1, G2, T6, T8 branch is connected to a ground capacitor, and G1 and G2 are transmission tubes. It is noted that the enable positions of G1 and G2 are different, that is, they are adjusted (G1 left side is low level effective, G2 left side is high level effective). Since G1 left side and G2 left side are connected, G1 right side and G2 right side are connected, therefore only one transmission tube is working at each moment.

[0057] Two inverters are connected behind the ground capacitor, which provide enable signals for G1 and G2 while adjusting the waveform; the output of inverter D2 is the clock output of the OSC oscillator;

[0058] The signal generation process of the oscillator circuit is as follows:

[0059] The outputs of D1 and D2 are either high, low or low, high at any time, so that either the upper part of the current mirror T2 and T4 works or the lower part of the current mirror T6 and T8 works. Taking the case of D1 output high and D2 output low (the voltage of the upper plate of C1 is low), G1 works and G2 does not work, so that the upper part of the current mirror T2 and T4 works, charging the upper plate of C1, until the voltage of the upper plate of C1 is high enough to make D1 flip. Then D1 output low and D2 output high, G2 works and G1 does not work, the lower part of the current mirror T6 and T8 draws current from the upper plate of C1, which is equivalent to discharging the charge of the upper plate of C1, until the voltage of the upper plate of C1 is low enough to make D1 flip, so as to realize the generation of clock in this way. The oscillation frequency of OSC is mainly determined by the current mirror current and C1 capacitor, so that the clock frequency can be changed by changing the bias current when C1 is unchanged.

[0060] Further, in Figure 4 , the feedback network comprises a logic processing module and four D flip-flops B1-B4. The sequence generation network comprises four D flip-flops. The second feedback signal satisfies the following formula:

[0061] F=B4⊕B5⊕B6⊕B8+B1′B2′B3′B4′B5′B6′B7′B8′

[0062] Wherein, F is the second feedback signal, B1', B2', B3', B4' are the outputs of the Q' end of each D flip-flop corresponding to the random digital reverse sequence, B5', B6', B7', B8' are the outputs of the Q' end of each D flip-flop in the first feedback signal set, B5, B6, B8 are the outputs of the Q end of each D flip-flop in the first feedback signal set; B1'B2'B3'B4'B5'B6'B7'B8' in the formula represents the AND operation between B1', B2', B3', B4', B5', B6', B7', B8' two by two. Symbol ⊕ represents XOR operation, and symbol + represents OR operation.

[0063] Specifically, the implementation process of the present application will be described below in conjunction with the accompanying Figure 5

[0064] ​The logic control based current bias circuit (IBIAS) of the embodiment takes 4-bit digital signals as input, which are converted into 16-bit digital sequences with only one bit being 1 and the rest being 0 by a 4-16 decoder. The 16 bits control 16 NMOS transistors respectively. For each NMOS transistor, it is turned on when the digital signal is 1 and turned off when the digital signal is 0. The on and off of the NMOS transistors control the actual number of series resistors. For example, M8 is turned on, and R8-R16 resistors are disconnected, and the actual working resistors are Rb and R0-R7, and the voltage of the operational amplifier is unchanged, thereby realizing the change of the bias current. Therefore, this part can realize a bias circuit for generating 16 kinds of bias currents controlled by 4-bit digital signals. The voltage dividing resistors R1-R16 in the example do not have to be equal, and can be randomly set according to the needs, so that the 16-stage bias currents are non-uniformly distributed.

[0065] The current control oscillator (ICO) circuit, the current mirror replicates the current of the bias circuit, and is used as the pull-up current and the pull-down current respectively. The two parts of current are respectively connected with a transmission gate, and only one of the two transmission gates is in the on state at any time. The current connected with the on transmission gate charges and discharges the capacitor, and when the capacitor is charged, the voltage rises; when the capacitor is discharged, the voltage decreases. The voltage of the capacitor is connected to a circuit composed of two inverters in series, and the outputs of the two series inverters are used as the control signals of the two transmission gates. In this way, an oscillator circuit capable of controlling the frequency by current is realized.

[0066] The frequency divider can be realized by connecting 8 two-dividers end to end to realize 2 8 times frequency division. The frequency divider can divide the pulse signal output by the current control oscillator. The low-speed pulse after frequency division is used as the clock signal of the M sequence generation circuit.

[0067] The 8-bit M sequence generation circuit is composed of an 8-bit shift register and a combination logic circuit. The 8-bit shift register performs digital sequence shift operation according to the low-speed pulse from the frequency divider as the clock. The combination logic circuit takes the output signals of the 8 D flip-flops constituting the shift register as input, and feeds back to the input of the first D flip-flop of the 8-bit shift register after logic operation, realizes a closed loop, and generates an M sequence with a period of 2 8 . The feedback circuit logic expression is formula (1). B1-B4 are selected as the input signals of the logic control based current bias circuit.

[0068] F=B4⊕B5⊕B6⊕B8+B1′B2′B3′B4′B5′B6′B7′B8′#(1)

[0069] The operation logic between the modules is summarized as follows: the logic-controllable bias circuit generates bias currents of different sizes according to a 4-bit digital signal, the current-controlled oscillator replicates the bias circuit current to generate a series of pulse square wave signals, the frequency divider divides the pulse square wave signals to generate a low-speed pulse square wave signal as the clock of the M-sequence generating circuit, the output of the first 4-bit D flip-flop in the M-sequence generating circuit is taken as the input signal of the logic-controllable bias circuit, and the logic closed loop of the entire circuit is realized. This modulation mode reduces the generation of audible frequencies while reducing the EMI peak value of the switching power supply.

[0070] Corresponding to the device of Figure 1 The embodiments of the present application also provide a switching power supply chip, comprising the random modulation clock spread spectrum device according to any one of the preceding.

[0071] In addition, although the present application is described in the context of functional modules, it should be understood that, unless otherwise stated to the contrary, one or more of the functions and / or features can be integrated in a single physical device and / or software module, or one or more functions and / or features can be implemented in separate physical devices or software modules. It can also be understood that detailed discussion of the actual implementation of each module is unnecessary for understanding the present application. Rather, given the properties, functions and internal relationships of the various functional modules in the devices disclosed herein, the actual implementation of the module will be understood within the ordinary skill of an engineer. Therefore, those skilled in the art can implement the present application as set forth in the claims using ordinary skill without undue experimentation. It can also be understood that the specific concepts disclosed are merely illustrative and are not intended to limit the scope of the present application, which is determined by the full scope of the appended claims and their equivalents.

[0072] In the above description of the present specification, the description of the terms "one embodiment", "another embodiment" or "certain embodiments" and the like means that the specific features, structures, materials or characteristics described in connection with the embodiments or examples are included in at least one embodiment or example of the present application. In the present specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0073] Although the embodiments of the present application have been shown and described, those skilled in the art can understand that various changes, modifications, replacements and variations can be made to these embodiments without departing from the principles and purposes of the present application, and the scope of the present application is defined by the claims and their equivalents.

[0074] The above describes the preferred embodiments of the present application, but the present application is not limited to the described embodiments, and those skilled in the art can make various equivalent modifications or replacements without departing from the spirit of the present application, and these equivalent modifications or replacements are all included in the scope defined by the claims of the present application.

Claims

1. A randomly modulated clock spread spectrum device, comprising: The method comprises the following steps: a frequency divider circuit, configured to receive a first pulse signal output by an oscillator circuit in a t-1 modulation period; The M sequence generating circuit is used for generating a random digital sequence of t-1 modulation periods according to the first pulse signal; wherein the period of the random digital sequence is 2 n , and n is an integer greater than or equal to 4. a current biasing circuit, configured to generate a first biasing current in a t-1 modulation period according to a random digital sequence; an oscillator circuit, configured to generate a clock spread spectrum signal in a t modulation period according to the first biasing current, t being an integer greater than or equal to 2; the M sequence generating circuit comprises a sequence generating network and a feedback network; the feedback network comprises a logic processing module and n-T D flip-flops; the sequence generating network comprises T D flip-flops; the sequence generating network is configured to generate a random digital inverse sequence in a t-2 modulation period; the random digital inverse sequence is a digital sequence obtained by performing logical NOT operation on the output signal of each D flip-flop in the T D flip-flops in the t-2 modulation period; the n-T D flip-flops are configured to generate a first feedback signal set in a t-1 modulation period according to a pulse signal in a t-2 modulation period; the logic processing module is configured to perform logical conversion processing on the first feedback signal set and the random digital inverse sequence to obtain a second feedback signal output to the sequence generating network in a t-1 modulation period; the sequence generating network is further configured to generate the random digital sequence according to the first pulse signal and the second feedback signal; wherein the random digital sequence is a digital sequence composed of the output signal of each D flip-flop in the T D flip-flops.

2. The randomly modulated clock spread spectrum apparatus of claim 1 wherein, the current biasing circuit comprises a decoder and a current converter; the decoder is configured to convert the random digital sequence into a target driving signal in a t-1 modulation period; the current converter is configured to convert the target driving signal into the first biasing current in a t-1 modulation period.

3. A randomly modulated clock spread spectrum apparatus as defined in claim 2, wherein, the current converter comprises: A current generating module, 2 T resistance modules and a resistance selection module; the current generating module is connected with the resistance selection module; the resistance selection module is used for determining any one resistance module from the 2 T resistance modules to form a closed loop with the current generating module and to form the first bias current according to the target driving signal.

4. A randomly modulated clock spread spectrum apparatus as defined in claim 3, wherein, resistance values of any two resistance modules in the T resistance modules are different from each other.

5. The randomly modulated clock spread spectrum apparatus of claim 2 wherein, The decoder is used to convert T signals into 2 T bit binary numbers and output target drive signals corresponding to the 2 T bit binary numbers.

6. The randomly modulated clock spread spectrum apparatus of claim 1 wherein, the frequency divider circuit comprises Y two-frequency dividers; any two adjacent two-frequency dividers in the Y two-frequency dividers are connected in series with each other; wherein Y is a positive integer greater than or equal to 2.

7. The randomly modulated clock spread spectrum apparatus of claim 1 wherein, the oscillator circuit comprises two current mirror modules connected in parallel with each other, a gating module, an energy storage module, and an inverter module; the current mirror module is configured to receive the first biasing current and generate a charging current in a t modulation period; the gating module is configured to gate any one of the current mirror modules in a t modulation period and charge the energy storage module through the charging current; the inverter module is configured to generate a control signal according to the voltage of the energy storage module, so that the gating module gates another current mirror module in a t modulation period, charges the energy storage module through the charging current, and generates a clock spread spectrum signal in a t modulation period.

8. The randomly modulated clock spread spectrum apparatus of claim 2 wherein, the feedback network comprises a logic processing module and four D flip-flops; the sequence generating network comprises four D flip-flops; the second feedback signal satisfies the following formula: Wherein, F is the second feedback signal, B1', B2', B3', B4' are the outputs of the Q' end of each D flip-flop corresponding to the random number reverse sequence, B5', B6', B7', B8' are the outputs of the Q' end of each D flip-flop in the first feedback signal set, B5, B6, B8 are the outputs of the Q end of each D flip-flop in the first feedback signal set; B1'B2'B3'B4'B5'B6'B7'B8' in the formula represents that B1', B2', B3', B4', B5', B6', B7', B8' are operated with each other; the symbol represents XOR operation, and the symbol + represents OR operation.

9. A switching power supply chip comprising a random modulation clock spread spectrum device according to any one of claims 1-8.

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