A glink bus testing method, system and chassis

Abstract

The application relates to the field of photoelectric detection-based test systems, in particular to a GLink bus test method, a GLink bus test system and a case; the GLink bus test method comprises the following steps: configuring and distributing a listening card, an exchange card and first node card and second node card IDs to make the first node card and the second node card belong to the same network domain; controlling the first node card to send preset self-check test data once, and acquiring whether the first node card sending state word is normal; in the case that the first node card sending state is normal, controlling the second node card to receive the self-check test data, and judging whether the sending and receiving data are consistent; if the sending and receiving data are consistent, it is determined that one detection is completed, and whether the preset working duration is met at the current time is judged; in the case that the preset working duration is met, it is determined that the self-check is completed; in the case that the self-check is completed, the test terminal to be detected is tested through the exchange card and the listening card; the self-check function is added, and the stability and reliability of the test system are improved.

Description

Technical Field

[0001] The present invention relates to the field of test systems based on photoelectric detection, and in particular to a GLink bus test method, system and chassis. Background Art

[0002] As a key tool for ensuring the quality and performance of communication systems, optimizing the core performance indicators of test equipment is crucial. Given the essential function of test equipment, the stability and reliability of its own system are fundamental to ensuring accurate test results. During the testing process, the test equipment must operate continuously and stably, accurately collecting and processing various self-test data. If the test equipment itself suffers from system instability, frequent hardware failures, or topology errors, this will directly lead to deviations, loss, or errors in the collected data, causing the test results to deviate significantly from the actual performance of the device under test.

[0003] The GLink network system, in particular, boasts significant advantages in data transmission efficiency, system scalability, and fault tolerance thanks to its multi-node topology. It is widely used in fields with stringent communication performance requirements, such as aerospace. Currently, the GLink protocol primarily utilizes electrical interfaces to maintain compatibility with hardware interfaces like 1553B. Therefore, maintaining the stability of the device under test in a network environment with multiple nodes operating in parallel is a pressing technical challenge for the GLink test system. Summary of the Invention

[0004] In light of the above, the multi-node topology of the GLink network increases system complexity while improving transmission efficiency. If the test equipment itself has hardware failures, topology configuration errors, or protocol compatibility issues, it will lead to data collection deviations, transmission interruptions, or increased bit error rates, directly affecting the accuracy of the test results. In particular, for testing in the aerospace field, the system's fault tolerance, scalability, and real-time performance are extremely high, and support for fault node traceability is required. Therefore, the present application provides a GLink bus testing method, system, and chassis.

[0005] In response to the above, the first aspect of the present application provides a GLink bus testing method, which includes: configuring and allocating the monitoring card, the switching card, and the first node card and the second node card ID so that they are in the same network domain; controlling the first node card to send a preset self-test test data once, and obtaining whether the first node card sending status word is normal; when the sending status of the first node card is normal, controlling the second node card to receive the self-test test data, and judging whether the received and sent data are consistent; if the received and sent data are consistent, determining that a test is completed, and judging whether the current moment meets the preset working time; when the preset working time is met, determining that the self-test is completed; when the self-test is completed, testing the terminal to be tested through the switching card and the monitoring card.

[0006] In a further optional scheme of the present application, the GLink bus testing method also includes: when the sending status of the first node card is abnormal, controlling the monitoring card to read the path data corresponding to the first node card to the second node card, wherein the path data includes a status frame, a command frame and a data frame; when receiving a command frame and a data frame, determining whether the status frame is received; if the command frame and the data frame are received, but the status frame is not received, determining that the configuration parameters of the first node card and the second node card do not match; if the command frame, the data frame and the status frame are received, determining that the link is abnormal and analyzing the abnormality based on at least one of the command frame, the data frame and the status frame.

[0007] In a further optional scheme of the present application, the GLink bus testing method also includes: if the received and sent data are inconsistent, controlling the monitoring card to read the path data corresponding to the first node card to the second node card, wherein the path data includes a status frame, a command frame and a data frame; judging whether the data frame is consistent with the original self-test data frame; if the data frame is inconsistent with the original self-test data frame, determining that the first node card link is abnormal; if the data frame is consistent with the original self-test data frame, determining that the second node card link is abnormal.

[0008] In a further optional scheme of the present application, the terminal to be tested is tested through a switching card and a listening card, including: obtaining the corresponding network domain ID and terminal ID based on the ID of the terminal to be tested; obtaining any terminal under the network domain ID, and connecting any terminal to the bus port; configuring the network domain ID of the switching card and the listening card, monitoring the data sending and receiving status of the tested terminal through the listening card, and controlling the switching card to send terminal detection data to verify the test of the terminal to be tested.

[0009] In a further optional solution of the present application, the GLink bus testing method further includes: when the preset working time is not met, controlling the first node card to cyclically send preset self-test data to continue self-testing.

[0010] A second aspect of the present application further provides a GLink bus test system, comprising: a mainboard unit, comprising a controller encapsulated with preset application software; a board unit, comprising a monitoring card, a switching card, a first node card, and a second node card; wherein the monitoring card, the switching card, the first node card, and the second node card are all connected to the mainboard unit via a PCIe bus, and the monitoring card, the switching card, the first node card, and the second node card each include at least one FMC daughter card unit;

[0011] The controller is configured to be able to execute the above-mentioned GLink bus testing method.

[0012] In a further optional solution of the present application, the monitoring card includes a first FPGA main control baseboard, the first FPGA main control baseboard includes a first FPGA processor, a first GLink data conversion module and a first clock circuit, the first FPGA processor is connected to the PXIE interface through a PXIE bus, and the first FPGA processor and the first GLink data conversion module are connected through an EMIF interface and at least one FIFO interface, and the first GLink data conversion module is connected to the corresponding FMC daughter card unit;

[0013] In a further optional solution of the present application, the switching card includes a second FPGA main control baseboard, the second FPGA main control baseboard includes a second FPGA processor, a second GLink data conversion module and a second clock circuit, the second FPGA processor is connected to the PXIE interface through the PXIE bus, and the second FPGA processor and the second GLink data conversion module are connected through an EMIF interface and at least one GPIO interface, and the second GLink data conversion module is connected to the corresponding FMC daughter card unit.

[0014] In a further optional solution of the present application, the FMC daughter card unit includes a first FMC daughter card and a second FMC daughter card; the first FMC daughter card includes a first interface composed of an optoelectronic module capable of adapting to optical fiber, and the second FMC daughter card includes a second interface composed of a transformer module capable of adapting to copper axis cable.

[0015] In a further optional solution of the present application, the monitoring card is connected to the first port of the switch card according to a preset topology, and the first node card and the second node card are connected to the remaining ports of the switch card.

[0016] The present application also provides a chassis, including a shell and a GLink bus test system as described above, which is arranged in the shell.

[0017] Compared with the prior art, the present invention has the following beneficial effects:

[0018] 1. By setting a self-check control strategy, it is possible to promptly detect faults or problems in the link, avoid data transmission errors during testing or operation, improve the stability of the test system itself, detect and meet the preset working time multiple times, ensure the reliability of the bus under long-term operation, and reduce the risk of system crash or data loss due to bus failure.

[0019] 2. By configuring the devices in the hardware framework to be in the same network domain, there is no need to search for the terminals to be tested one by one in a complex network. Instead, testing can be performed based on the division of the network domain, which simplifies the testing process. For example, batch testing can be performed on specific network domains, and multiple devices in the same network domain can be tested at the same time, reducing testing time and labor costs.

[0020] 3. In the process of determining whether the sent and received data are consistent, analyzing and statistically analyzing the GLink data protocol can provide a deeper understanding of the data transmission process and accurately identify specific problems in the data protocol. It can also quickly locate the root cause of the problem and determine whether the problem occurs at the sending end, the receiving end, or the link process.

[0021] In summary, the GLink bus testing method provided by the present application adds a self-test function, which improves the stability and reliability of the test system. At the same time, for a complex GLink network structure, there is no need to find the terminal to be tested. It is only necessary to locate the network domain of the terminal to be tested to accurately test the status of the inspection device. Based on the above-mentioned comparison of the GLink network receiving and sending data, the analysis and statistics of the GLink data protocol are added, which can more accurately assist the tested device in discovering problems, locating problems, and solving problems.

[0022] Other features and advantages of the embodiments of the present invention will be described in the subsequent specific implementation examples. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the specific implementation methods or the description of the prior art. Obviously, the drawings described below are some implementation methods of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without any creative work.

[0024] Figure 1 The connection topology diagram of the GLink bus test system provided in this application;

[0025] Figure 2 The connection topology diagram of the monitoring card in the GLink bus test system provided by this application;

[0026] Figure 3The connection topology diagram of the switch card in the GLink bus test system provided by this application;

[0027] Figure 4 A connection topology diagram of the first FMC daughter card and the second FMC daughter card in the GLink bus test system provided by this application;

[0028] Figure 5 A connection topology diagram of the switch card, monitor card, first node card, and second node card in the GLink bus test system provided in this application;

[0029] Figure 6 This is the overall flow chart of the GLink bus testing method provided in this application;

[0030] Figure 7 The control decision roadmap of the GLink bus test method provided in this application;

[0031] Figure 8 This is a schematic diagram of the first interface of the GLink bus test system provided in this application;

[0032] Figure 9 This is a schematic diagram of the second interface of the GLink bus test system provided in this application. DETAILED DESCRIPTION

[0033] The terms "second direction", "first direction", "third direction", "inside", "outside" and the like that appear below to indicate directions or positional relationships, unless otherwise specified, are to be understood as being based on the directions or positional relationships shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction. Therefore, they should not be understood as limiting this application.

[0034] Furthermore, the use of "first" or "second" in describing features is for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features identified. Features identified as "first" or "second" may explicitly or implicitly include at least one of the identified features. The use of the word "plurality" generally implies at least two, such as two or three, unless otherwise specifically defined.

[0035] In this application, unless otherwise specified or limited, terms such as "mounted," "connected," "connect," and "fixed" should be interpreted broadly. For example, they can refer to fixed connections, removable connections, or integration; mechanical connections, electrical connections, direct connections, or indirect connections through an intermediary; and internal connections between two components or interactions between two components. Those skilled in the art will understand the specific meanings of these terms in this application based on the specific circumstances.

[0036] In the description of this specification, if the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" appear, it means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and features of different embodiments or examples without contradiction.

[0037] [System Example]

[0038] Please refer to Figure 1 The present application provides a GLink bus test system 100 , which includes a mainboard unit 10 and a board unit 20 connected to the mainboard unit 10 .

[0039] Specifically, the motherboard unit 10 includes a controller 11 encapsulated with preset application software; the board unit 20 includes a monitoring card 21, a switching card 22, a first node card 23 and a second node card 24; wherein the monitoring card 21, the switching card 22, the first node card 23 and the second node card 24 are all connected to the motherboard unit 10 through a PCIe bus, and the monitoring card 21, the switching card 22, the first node card 23 and the second node card 24 each include an FMC daughter card unit A.

[0040] In this application, the monitoring card 21 and the switching card 22 are both developed based on FPGA. The monitoring card 21 is mainly used to capture and monitor the data traffic in the system where the mainboard unit 10 is located or the network connected to it in real time, and can analyze the source, destination, protocol type, data size and other information of the network data packet.

[0041] It can be understood by those skilled in the art that, in the GLink bus test system 100, GLink bus data transmission is established through ID identification. Generally speaking, the ID includes an 8-bit network domain ID and a 4-bit terminal ID. For the topology structure, the network domain ID of the same terminal must be consistent; at the same time, the GLink bus protocol consists of a command frame, a data frame and a status frame; and communication is established through ID identification (8-bit network domain ID and 4-bit terminal ID).

[0042] According to the above-mentioned features of GLink, the GLink bus test system 100 provided by the present application, the mainboard unit 10 adopts a PCIe bus computing mainboard, and the application software of the GLink bus test system can be encapsulated in the mainboard unit 10. It can exchange data with each board (listening card 21, switching card 22, first node card 23 and second node card 24) through the PCIe bus of the mainboard unit 10, and configure the working mode and parameters of each board. At the same time, it can generate self-test data, receive data, etc., and parse all GLink protocol data in the network domain.

[0043] The motherboard unit 10 uses a PCIe bus computing motherboard, and the application software is encapsulated in the motherboard unit 10 to exchange data with each board, configure working mode and parameters, generate self-test data, receive data and parse all GLink protocol data in the network domain.

[0044] In a further solution of the present application, the first node card 23, the second node card 24 and the monitoring card 21 all adopt the same hardware platform.

[0045] In order to be compatible with optical fiber and copper axis cable, the FMC interface is used on the hardware to lead out the Serdes signal, and the corresponding FMC daughter card unit A is designed according to different transmission media; Figure 1 As shown, each FMC daughter card unit A is configured to be compatible with optical fiber and copper axis cables, enabling the system to adapt to different application scenarios and transmission requirements, and enhancing hardware versatility and compatibility.

[0046] The GLink monitoring card needs to be configured through application software to implement the monitoring function. At the same time, the GLink monitoring card can collect command frames, data frames, and status frames of the GLink protocol. Each frame data contains the time information of the frame generation, the source terminal ID and the destination terminal ID, and the error frame information. The above information makes it easy to know the data transmission path and status, and accurately determine which path's data is abnormal and when, providing a detailed basis for fault diagnosis and system performance optimization.

[0047] Please refer to Figure 2Specifically, the monitoring card 21 includes a first FPGA main control baseboard 211, which includes a first FPGA processor 211a, a first GLink data conversion module 211b and a first clock circuit 211c; the first FPGA processor 211a is connected to the PXIE interface through a PXIE high-speed bus, and the first FPGA processor 211a and the first GLink data conversion module 211b are connected through an EMIF interface and at least one FIFO interface. The first GLink data conversion module 211b is connected to the corresponding FMC daughter card unit A (FMC plug-in).

[0048] It should be noted that PXIE is shown as an instrument expansion bus based on PCIe, which is a high-performance industrial bus standard; the PXIE interface refers to the connection between the monitoring card 21 and the mainboard unit 10 through the PXIE bus to achieve high-speed data transmission (bandwidth can reach several GB / s) and control instruction interaction; the EMIF interface is shown as an external memory interface, which is a high-speed data interface designed for the first FPGA processor 211a and the external memory (such as DDR, SRAM) or other devices (such as GLINK module). In this application, it is used as a parallel data transmission between the FPGA processor 211a and the GLINK data conversion module 211b to support large-bandwidth communication; FIFO is shown in this application as a first-in-first-out queue interface, which serves as a data buffering mechanism to solve the problem of mismatch between different clock domains or processing speeds; further in this application, a FIFO interface is inserted between the first FPGA processor 211a and the first GLink data conversion module 211b to ensure reliable transmission of data between asynchronous clock domains (such as preventing data loss or conflict); for example: when the FPGA write speed is faster than the GLINK module sending speed, the FIFO caches data at this time.

[0049] Furthermore, the FMC daughter card unit A is designed as an FPGA mezzanine card, which is an expansion interface used to add a daughter card with specific functions to the FPGA mainboard, providing bus signal level conversion, isolation or optical fiber interface, and high-speed copper cable interface; the first clock circuit 211c can ensure the clock synchronization of the FPGA, GLINK module, and FMC daughter card unit A to avoid data sampling errors.

[0050] In summary, the architectural workflow of the entire monitoring card 21 can be simplified as follows: the GLINK bus signal is accessed through the FMC subcard A, converted into parallel data by the first GLINK data conversion module 211b, and the data is transmitted to the first FPGA processor 211a via the EMIF interface and / or the FIFO interface for protocol parsing or storage. The first FPGA processor 211a uploads the data to the host computer through the PXIE interface, or reversely controls the GLINK device of the terminal through the first GLINK data conversion module 211b. In the above process, the first clock circuit 211c ensures that the timing of each module is consistent.

[0051] It can be understood that based on the parallel processing capability of the first FPGA processor 211a, a large amount of GLink bus data can be quickly processed. The first FPGA processor 211a and the first GLink data conversion module 211b are connected through an EMIF interface and at least one FIFO interface; the EMIF interface provides a high-speed data transmission channel, and the FIFO interface can realize data buffering and synchronization, ensuring stable transmission of data between different modules, avoiding data loss and conflict, and improving the efficiency and accuracy of data processing; the first GLink data conversion module 211b is connected to the corresponding FMC sub-card unit A, and can lead out the Serdes signal through the FMC interface, and connect to the corresponding interface according to different transmission media (optical fiber and copper axis cable), so that the monitoring card 21 can flexibly adapt to different transmission environments. The first clock circuit 211c provides a stable clock signal for the monitoring card 21 to ensure data synchronization and coordination between various modules.

[0052] Please refer to Figure 3 Similarly, the switching card 22 includes a second FPGA main control baseboard 221, the second FPGA main control baseboard 221 includes a second FPGA processor 221a, a second GLink data conversion module 221b and a second clock circuit 221c, the second FPGA processor 221a is connected to the PXIE interface through the PXIE bus, and the second FPGA processor 221a and the second GLink data conversion module 221b are connected through an EMIF interface and at least one GPIO interface, and the second GLink data conversion module 221b is connected to the corresponding FMC daughter card unit A.

[0053] It should be noted that the GPIO interface is a general input / output interface used for the transmission of low-bandwidth control signals, such as triggering the reset signal of the GLINK module or reading the status signal of the FMC daughter card; in the switching card 22, the GPIO interface is configured so that the controllable signal does not require high-speed buffering, which saves more FPGA logic resources than the FIFO interface GPIO interface.

[0054] Similarly, its architectural workflow can be simplified as follows: the GLINK signal is accessed through the FMC daughter card A, converted into parallel data by the second GLINK data conversion module 221b, and the data is transmitted to the FPGA processor 221a via the EMIF interface to parse the target address. At the same time, the FPGA triggers the GLINK module of the target port through GPIO, converts the data back into a GLINK signal and sends it to the NT node. Similarly, the second clock circuit 221c ensures that the clocks of the FPGA and GLINK modules are aligned to avoid data sampling errors.

[0055] It can be understood that the switching card 22 also adopts a modular design. The second FPGA main control baseboard 221 includes a second FPGA processor 221a, a second GLink data conversion module 221b and a second clock circuit 221c. The second FPGA processor 221a and the second GLink data conversion module 221b are connected through an EMIF interface and at least one GPIO interface; the EMIF interface is based on the guarantee of high efficiency of data transmission, and the GPIO interface provides more control signals and status feedback, so that the switching card 22 can interact and communicate with other devices more flexibly. Similar to the monitoring card 21, the second GLink data conversion module 221b is connected to the corresponding FMC sub-card unit A. Through the FMC interface and the corresponding FMC sub-card unit A, it can be compatible with different transmission media such as optical fiber and copper axis cable, supporting 16-channel optical fiber data transmission, and the data transmission rate of each channel supports up to 6.25Gbps.

[0056] In this application, the monitoring card 21 and the switching card 22 also include a board-level management unit and a debugging interface. The board-level management unit can monitor various hardware parameters and operating status on the monitoring card 21 and the switching card 22 in real time. The debugging interface provides developers and operation and maintenance personnel with a convenient way to access various debugging tools for flexible configuration of system parameters.

[0057] In a preferred solution of the present application, the first node card 23 and the second node card 24 mentioned above are mainly composed of an FPGA chip XC7K325T and an interface bridge chip JLK1263.

[0058] In summary, the monitoring card 21 and the switching card 22 adopt similar architectural designs and are based on the same hardware platform, so that the two can be better integrated and work together in the GLink bus test system 100, thereby improving the overall efficiency of the system; at the same time, the monitoring card 21 is responsible for data collection and monitoring, and the switching card 22 is responsible for forwarding data in the entire network domain. The collaborative work of the two can realize comprehensive monitoring and management of GLink bus data.

[0059] Please refer to Figure 4 as well as Figure 5In a specific embodiment, the FMC daughter card unit A includes a first FMC daughter card A1 and a second FMC daughter card A2; the first FMC daughter card A1 includes a first interface a1 composed of an optoelectronic module capable of adapting to optical fiber, and the second FMC daughter card A2 includes a second interface a2 composed of a transformer module capable of adapting to copper coaxial cable.

[0060] Considering the above, different test application scenarios have different requirements for transmission media. Users can adapt to different transmission media by simply inserting the first FMC daughter card A1 or the second FMC daughter card A2 according to their actual needs. This simplifies the system's hardware architecture, reduces the number and complexity of hardware devices, reduces system deployment costs and time, and also facilitates system maintenance and management.

[0061] It should be noted that, due to GLink's characteristics, the ID of switch card 22 is represented by 0xN, where N is a hexadecimal number (range: 0 to FF). Examples include 0x3A, 0xFF, 0x05, and so on. The IDs of the first and second node cards are both 12 bits, with the upper 8 bits matching the switch card ID and the lower 4 bits matching the port number to which they are connected. For example, if the switch card ID is 0x3A and the port number is 0x5, the node card ID is 0x3A5. If the switch card ID is 0xFF and the port number is 0xE, the node card ID is 0xFFE.

[0062] The monitor card 21 is connected to the first port of the switch card 22 according to a preset topological connection relationship. The first node card 23 and the second node card 24 are connected to the remaining ports of the switch card 22. Taking the switch card 22 using the 0x20 domain as an example, the monitor card must be connected to port 0 of the switch card (starting from 0), and the node cards can be connected to any of the remaining 15 ports of the switch card. This achieves fault location and isolation, helping to quickly locate the source of the fault when a system fault occurs, while also improving data transmission efficiency, reducing signal interference, and facilitating system expansion.

[0063] [Method Example]

[0064] See also Figure 6 as well as Figure 7 Based on the above-mentioned GLink bus test system 100, the present application further provides a GLink bus test method, which includes the following steps:

[0065] Step S10: Configure and allocate the monitoring card, the switching card, the first node card, and the second node card IDs so that they are in the same network domain;

[0066] In this GLink bus test system, specific IDs (identity identifiers) need to be configured and assigned to the monitoring card, switching card, first node card, and second node card. The "ID" needs to follow certain coding rules to ensure uniqueness in the system network. Through ID configuration, the above-mentioned monitoring card, switching card, first node card, and second node card are included in the same network domain. A network domain refers to a group of devices that communicate with each other and share specific network protocols and configurations. Devices in the same network domain can follow the same communication rules and address allocation mechanism to achieve normal communication and collaborative work between devices.

[0067] For example, in a GLink bus network, the monitoring card, the switching card, the first node card, and the second node card are all configured in the same network domain, using the same communication protocol (such as a specific data frame format, communication rate, etc.) and address allocation mechanism (such as an ID-based address mapping rule), so that devices can accurately identify and exchange data.

[0068] Step S20: Control the NC node of the first node card to send a preset self-test data, and obtain whether the status word sent by the NC node is normal;

[0069] Send instructions to the NC node of the first node card to make it send preset self-test data, and at the same time obtain the sending status word of the NC node; its purpose is to check whether there is a hardware fault or software problem in the sending module of the first node card, and judge whether the data is sent successfully or whether there is an error by sending the status word.

[0070] Step S30: When the NC node sends the status word normally, control the NT node of the second node card to receive the self-test data and determine whether the sent and received data are consistent;

[0071] When the NC node of the first node card sends the status word normally, the NT node of the second node card is controlled to receive the self-test data, and the received data is compared with the self-test data sent by the NC node; the accuracy and integrity of the data during the transmission process are verified; technical personnel in this field should know that the NC node can be understood as a network controller node, and the NT node is a network terminal node.

[0072] Step S40: If the sent and received data are consistent, it is determined that one test is completed, and whether the current time meets the preset working time;

[0073] If the received and sent data are consistent, it is determined that a test is completed, and then it is determined whether the system has worked for the preset working time. The current moment is used for judgment. A feasible method is: start timing from the initial zero moment when the NC node is controlled for the first time to send the preset self-test test data to obtain the current moment. The preset working time is to ensure the stability and reliability of the bus under long-term operation. Whether the working time is met is determined by the current moment to determine whether further self-test is needed or to enter the subsequent test process.

[0074] Step S50: If the preset working time is met, determine that the self-check is completed;

[0075] Step S60: After the self-test is completed, the terminal to be tested is tested through the switching card and the monitoring card.

[0076] Only when the working time requirements are met, it is determined that the system has no faults or problems during long-term operation and the self-test process is complete and effective. After the self-test is completed, the switching card and monitoring card are used to test the terminal to obtain relevant data and status information of the terminal, and a comprehensive performance and function test is performed on the terminal to ensure that the terminal can work normally and meet the system requirements.

[0077] It can be understood that the present application can timely detect faults or problems in the link through the self-test function in steps S20 to S50, avoid data transmission errors during testing or operation, improve system stability, detect and meet the preset working time multiple times, ensure the reliability of the bus under long-term operation, and reduce the risk of system crash or data loss due to bus failure.

[0078] In step S10, by configuring the devices in the same network domain, there is no need to search for the terminals to be tested one by one in a complex network. It is only necessary to perform tests according to the division of the network domain, which simplifies the testing process. For example, batch testing can be performed on a specific network domain, and multiple devices in the same network domain can be tested at the same time, which reduces testing time and labor costs.

[0079] In step S30 and thereafter, when determining whether the sent and received data are consistent, the GLink data protocol is analyzed and counted, which can provide a deeper understanding of the data transmission process and accurately identify specific problems in the data protocol. The root cause of the problem can be quickly located to determine whether the problem occurs at the sending end, the receiving end, or the link process.

[0080] In summary, the GLink bus testing method provided by the present application adds a self-test function, which improves the stability and reliability of the test system. At the same time, for a complex GLink network structure, there is no need to find the terminal to be tested. It is only necessary to locate the network domain of the terminal to be tested to accurately test the status of the inspection device. Based on the above-mentioned comparison of the GLink network receiving and sending data, the analysis and statistics of the GLink data protocol are added, which can more accurately assist the tested device in discovering problems, locating problems, and solving problems.

[0081] Furthermore, the GLink bus testing method further includes:

[0082] Step S21: When the NC node does not send the status word normally, the monitoring card is controlled to read the path data from the corresponding NC node to the NT node, where the path data includes a status frame, a command frame, and a data frame.

[0083] Step S22: upon receiving a command frame and a data frame, determining whether a status frame is received;

[0084] Step S23: If a command frame and a data frame are received but a status frame is not received, it is determined that the configuration parameters of the first node card and the second node card do not match;

[0085] Step S24: If a command frame, a data frame, and a status frame are received, determine that the link is abnormal and analyze the abnormality based on at least one of the command frame, the data frame, and the status frame.

[0086] As you can understand, when the first node card's NC node transmits an abnormal status, the control monitoring card reads the path data from the first node card to the second node card. This path data consists of status frames, command frames, and data frames. Status frames typically contain information about the communication process, such as whether communication is normal or error-free. Command frames instruct nodes to perform specific operations, while data frames carry the actual data being transmitted. Reading this data provides detailed information for subsequent problem analysis.

[0087] When receiving command frames and data frames, it is determined whether the status frame is received. The generation and transmission of the status frame depends on the configuration parameters of the node card. If the configuration parameters of the first node card and the second node card do not match, the status frame may not be generated or transmitted correctly. The command frame and data frame may still be able to be transmitted according to certain rules, but due to the lack of feedback from the status frame, the communication process may be abnormal; when all types of frames are received, it means that the basic communication process is normal, but anomalies still occur, which may be a problem at the link level. Link anomalies may include signal interference, line failure, etc. By analyzing the specific content of the command frame, data frame and status frame, the specific cause of the anomaly can be further mapped. (such as Figure 8 and Figure 9interface shown).

[0088] The mapping rules can be exemplified by the following situations: link layer interference: signal attenuation or EMI causes frame content errors (such as a byte in the data frame is flipped); timing asynchrony: the generation delay of the status frame exceeds the protocol window (such as GLINK requires the status frame to be replied within 2ms); or protocol logic conflict: for example, the "busy status" (0xC3=Busy) of the status frame is not handled correctly, causing a deadlock. The mapping relationship of the fault diagnosis table is established through the above situations; for example: a command frame, data frame and status frame are received, but the system still tries to send the next command, and analyzes the "cause of the exception" corresponding to the error code in the status frame.

[0089] Through step S23, it is possible to quickly determine that the communication anomaly is caused by the mismatch of the configuration parameters of the first node card and the second node card; unnecessary troubleshooting at the link level is avoided, saving time and energy. For example, in a large GLink bus network, if traditional troubleshooting methods are used, it may be necessary to check the devices and lines on the link one by one, which is inefficient. By determining whether the status frame is received, the configuration parameter problem can be quickly located and adjusted in time; step S24 can determine the link anomaly and further analyze the cause of the anomaly. By analyzing the frame data, the specific manifestations of the anomaly, such as data transmission errors, signal loss, etc., can be understood, so that targeted repairs can be made. It can promptly detect problems when communication anomalies occur, analyze and solve them, improve the transmission quality and stability of the link, and enhance the reliability of the entire GLink bus system.

[0090] In the further application, the GLink bus test method also includes:

[0091] Step S31: If the sent and received data are inconsistent, the monitoring card is controlled to read the path data from the corresponding NC node to the NT node, where the path data includes a status frame, a command frame, and a data frame;

[0092] Step S32: determine whether the data frame is consistent with the original self-test data frame;

[0093] Step S33: If the data frame is inconsistent with the original self-test data frame, it is determined that the NC node link is abnormal;

[0094] Step S34: If the data frame is consistent with the original self-test data frame, it is determined that the NT node link is abnormal.

[0095] If it is found in step S30 that the NC node's transmission status is normal, but the data received by the NT node is inconsistent with the self-test data sent by the NC node, the control monitoring card reads the path data from the corresponding NC node to the NT node. Similarly, this path data includes status frames, command frames, and data frames.

[0096] The read data frame is compared with the original self-test data frame to determine whether the two are consistent. After the data is sent from the NC node, it is first transmitted through the NC node link. If the read data frame is inconsistent with the original data frame, it is determined that the NC node link is abnormal; when the data frame is consistent with the original data frame, it means that there is no problem with the data during transmission on the NC node link; but if the data received by the NT node is inconsistent with the data sent by the NC node, then it is determined that the NT node link is abnormal.

[0097] By breaking down data inconsistency issues into NC node link anomalies and NT node link anomalies, the specific location of the fault can be quickly determined. This avoids blind troubleshooting throughout the entire bus network, significantly saving time and effort in troubleshooting. For example, in a large GLink bus network, if you use traditional methods to troubleshoot data inconsistencies, you may need to check all nodes and links. However, with the newly added steps, you can directly locate the NC node link or NT node link, improving troubleshooting efficiency. Accurately locating the fault location can reduce interference with other normal parts of the system. Only the link with the problem needs to be inspected and repaired, which will not affect other normally operating nodes and links, ensuring the overall stability of the system.

[0098] In a further solution of the application, the terminal to be detected is tested by the switching card and the monitoring card in step S60, including:

[0099] Step S61: Obtain the corresponding network domain ID and terminal ID according to the acquired ID of the terminal to be detected;

[0100] Step S62: Acquire any terminal under the network domain ID and connect the terminal to the bus port;

[0101] Step S63: configure the network domain IDs of the switch card and the monitoring card, monitor the data transmission and reception of the tested terminal through the monitoring card, and control the switch card to send terminal detection data to verify the tested terminal.

[0102] Based on the ID of the terminal to be detected, the corresponding network domain ID and terminal ID are obtained. In the GLink bus network, each terminal has a unique ID, and the network domain to which the terminal belongs also has a specific ID. The terminal ID can be traced back to its network domain ID. This is because during network planning, there is a specific mapping relationship between the terminal ID and the network domain ID. For example, a corresponding table of terminal IDs and network domain IDs is stored in the database, and relevant information can be quickly obtained by querying the table.

[0103] Get any terminal under the network domain ID and connect it to the bus port (except port 0 which is used to connect to its own monitoring card). To test the terminal to be tested, it is necessary to simulate an actual communication environment and select other terminals under the same network domain to connect to the bus port. The terminals in the same network domain follow the same communication protocols and rules and can effectively interact with the terminal to be tested. Port 0 is specifically used to connect to the monitoring card to monitor the bus communication, and other ports are used to connect to other terminals for testing. Configure the network domain ID of the switching card and the monitoring card, monitor the data sending and receiving of the tested terminal through the monitoring card, and control the switching card to send terminal detection data to verify the test of the terminal to be tested.

[0104] Specifically, the ID of the terminal to be tested is obtained through the test system's input interface or pre-stored information. Then, based on the preset correspondence between the terminal ID and the network domain ID, its network domain ID and terminal ID are determined. After determining the network domain ID, a terminal is randomly selected from the terminal list within the network domain and connected to an idle port of the bus test system via a physical cable. Network domain ID configuration parameters for the switching card and the monitoring card are input through the bus test system's application software interface. The application software transmits these parameters to the switching card and the monitoring card, completing the network domain ID configuration. The monitoring card then begins operating, capturing data sent and received by the terminal under test on the bus in real time. The application software analyzes and displays the captured data, including information such as data type, content, and send and receive times.

[0105] Specifically, the control switching card sends terminal detection data to verify the test terminal to be tested, and adopts steps similar to the above-mentioned steps S30 to S50: the control switching card sends preset detection data to the terminal to be tested, and obtains whether the sending status word of the switching card is normal. If the sending status is normal, the control monitoring card reads the path data from the switching card to the terminal to be tested, and determines whether the sent and received data are consistent. If they are inconsistent, further analyze whether the abnormality is in the switching card link or the terminal to be tested link. If the sent and received data are consistent, determine whether the preset working time is met at the current moment. If it is met, it is determined that the terminal to be tested is working normally.

[0106] GLink bus test methods also include:

[0107] Step S70: If the preset working time is not met, control the first node card to cyclically send preset self-test data to continue self-test.

[0108] When the preset working time is not met during the test of the terminal to be tested, the system will control the first node card to cyclically send the preset self-test test data and continue to execute the self-test process. The cyclic sending of data is equivalent to increasing the sample size of the self-test, making the self-test result more accurate.

[0109] The present application also provides a chassis, including a shell (not shown) and a GLink bus test system arranged in the shell.

[0110] As a preferred solution of this application, the chassis adopts a PXIE industrial computer, which is used as a carrier for the operation of the host computer test application software, and completes the control and data interaction with other functional modules. The appearance of the module can be designed based on the requirements. In a specific configuration, it can insert a 3U standard board card, and the chassis is equipped with 6 peripheral slots, including 1 slot for the controller and 5 slots for peripherals.

[0111] The various technical features described above can be combined arbitrarily. Although not all possible combinations of these technical features are described, any combination of these technical features should be considered to be covered by this specification as long as such combination does not conflict.

[0112] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still adjust the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these adjustments or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A GLink bus testing method, characterized in that: include: Configure and assign the monitoring card, the switching card, the first node card, and the second node card IDs so that they are in the same network domain; Control the NC node of the first node card to send a preset self-test data, and obtain whether the status word sent by the NC node is normal; When the NC node sends the status word normally, it controls the NT node of the second node card to receive the self-test data and determines whether the sent and received data are consistent; If the sent and received data are consistent, a test is completed to determine whether the current time meets the preset working time; When the preset working time is met, the self-inspection is determined to be completed; After the self-test is completed, the terminal to be tested is tested by the switching card and the monitoring card; When the NC node sends an abnormal status word, the control monitoring card reads the path data from the corresponding NC node to the NT node, where the path data includes status frames, command frames and data frames; When receiving a command frame and a data frame, determine whether a status frame is received; If a command frame and a data frame are received but a status frame is not received, it is determined that the configuration parameters of the first node card and the second node card do not match; If a command frame, a data frame, and a status frame are received, a link abnormality is determined and the abnormality is analyzed based on at least one of the command frame, the data frame, and the status frame.

2. The GLink bus testing method according to claim 1, wherein: Also includes: If the sent and received data are inconsistent, the control monitoring card reads the path data from the corresponding NC node to the NT node, where the path data includes status frames, command frames and data frames; Determine whether the data frame is consistent with the original self-test data frame; If the data frame is inconsistent with the original self-test data frame, it is determined that the NC node link is abnormal; If the data frame is consistent with the original self-test data frame, it is determined that the NT node link is abnormal.

3. The GLink bus testing method according to claim 1, wherein: The testing of the terminal to be detected by using the switching card and the monitoring card includes: According to the obtained ID of the terminal to be detected, the corresponding network domain ID and terminal ID are obtained; Acquire any terminal under the network domain ID, and connect the arbitrary terminal to the bus port; Configure the network domain ID of the switching card and the monitoring card, monitor the data sent and received by the tested terminal through the monitoring card, and control the switching card to send terminal detection data to verify the test terminal.

4. The GLink bus testing method according to claim 1, wherein: Also includes: When the preset working time is not met, the first node card is controlled to cyclically send preset self-test data to continue self-test.

5. A GLink bus test system, characterized in that: include: A mainboard unit including a controller encapsulated with preset application software; The board unit includes a monitoring card, a switching card, a first node card, and a second node card; The monitoring card, the switch card, the first node card and the second node card are all connected to the mainboard unit through a PCIe bus, and the monitoring card, the switch card, the first node card and the second node card each include an FMC daughter card unit; The controller is configured to execute the GLink bus testing method according to any one of claims 1 to 4.

6. The GLink bus test system according to claim 5, characterized in that: The monitoring card includes a first FPGA main control baseboard, which includes a first FPGA processor, a first GLink data conversion module and a first clock circuit. The first FPGA processor is connected to the PXIE interface through a PXIE bus, and the first FPGA processor and the first GLink data conversion module are connected through an EMIF interface and at least one FIFO interface. The first GLink data conversion module is connected to the corresponding FMC daughter card unit; The switching card includes a second FPGA main control baseboard, which includes a second FPGA processor, a second GLink data conversion module and a second clock circuit. The second FPGA processor is connected to the PXIE interface through a PXIE bus, and the second FPGA processor and the second GLink data conversion module are connected through an EMIF interface and at least one GPIO interface. The second GLink data conversion module is connected to the corresponding FMC daughter card unit.

7. The GLink bus test system according to claim 5, characterized in that: The FMC daughter card unit includes a first FMC daughter card and a second FMC daughter card; The first FMC daughter card includes a first interface formed by an optoelectronic module capable of adapting to optical fibers, and the second FMC daughter card includes a second interface formed by a transformer module capable of adapting to copper cables.

8. The GLink bus test system according to claim 5, characterized in that: The monitoring card is connected to the first port of the switch card according to a preset topology, and the first node card and the second node card are connected to the remaining ports of the switch card.

9. A chassis, characterized in that: It comprises a housing and a GLink bus test system as claimed in any one of claims 5 to 8 arranged in the housing.

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