Light detection device and electronic apparatus

Abstract

The invention relates to a light detection device and an electronic apparatus. The light detection apparatus includes: a comparison section including a power supply circuit configured to generate a first power supply voltage based on a power supply voltage supplied from a first power supply node and a bias voltage, and output the first power supply voltage from an output terminal, and a comparison circuit configured to compare the first power supply voltage with the first power supply node; the comparison circuit is configured to operate based on the first power supply voltage and perform a comparison operation based on a pixel signal and a reference signal.

Description

[0001] This application is a divisional application of the patent application with application number 202080013552.X, filed on March 6, 2020, and with the invention name “Light detection device and electronic device”. Technical Field

[0002] The present disclosure relates to a light detection device capable of detecting light and an electronic device including the light detection device. Background Art

[0003] In a photodetection device, pixels typically generate pixel signals corresponding to the amount of light they receive, and an analog-to-digital (A / D) conversion circuit converts the pixel signals into digital codes. For example, Patent Document 1 discloses an imaging device that performs A / D conversion based on a ramp waveform signal and the pixel signals.

[0004] List of citations

[0005] Patent Literature

[0006] Patent Document 1: Japanese Unexamined Patent Application Publication No. 2007-19682 Summary of the Invention

[0007] Incidentally, in the light detection device, high image quality is desired, and further improvement of the image quality is desired.

[0008] It is desirable to provide a light detection device and an electronic device capable of improving image quality.

[0009] According to an embodiment of the present disclosure, a light detection device includes a first pixel, a reference signal generating unit, and a first comparing unit. The first pixel is configured to generate a first pixel signal. The reference signal generating unit is configured to generate a reference signal. The first comparing unit includes a first power supply circuit and a first comparing circuit. The first power supply circuit is configured to generate a first power supply voltage based on a power supply voltage and a bias voltage supplied from a first power supply node, and is configured to output the first power supply voltage from an output terminal. The first comparing circuit operates based on the first power supply voltage and is configured to perform a comparison operation based on the first pixel signal and the reference signal.

[0010] An electronic device according to an embodiment of the present disclosure includes the above-described light detection device, and corresponds to, for example, a smartphone, a digital camera, a video camera, a notebook personal computer, or the like.

[0011] In a light detection device and an electronic device according to an embodiment of the present disclosure, the first pixel generates a first pixel signal, and the reference signal generating unit generates a reference signal. The first power supply circuit generates a first power supply voltage based on a power supply voltage and a bias voltage supplied from a first power supply node. A first comparison circuit operable based on the first power supply voltage then performs a comparison operation based on the first pixel signal and the reference signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a block diagram illustrating a configuration example of an image pickup apparatus according to an embodiment of the present disclosure.

[0013] Figure 2 It shows Figure 1 A circuit diagram showing an example of the configuration of a pixel is shown.

[0014] Figure 3 It shows Figure 1 A block diagram showing an example of the configuration of a readout unit is shown.

[0015] Figure 4A It shows Figure 3 A circuit diagram showing an example of the configuration of a comparison section is shown.

[0016] Figure 4B It shows Figure 3 A circuit diagram of another configuration example of a comparison section is shown.

[0017] Figure 5 It shows Figure 3 A circuit diagram showing an example configuration of a readout section is shown.

[0018] Figure 6 It shows Figure 1 An explanatory diagram of an embodiment of an imaging device shown.

[0019] Figure 7 It shows Figure 1 An explanatory diagram of another embodiment of the imaging device shown.

[0020] Figure 8 It shows Figure 1 A timing chart showing an example of the operation of the imaging device shown.

[0021] Figure 9 It shows Figure 1 The timing waveform diagram of the operation example of the imaging device shown is shown.

[0022] Figure 10A is a circuit diagram showing a configuration example of a comparison section according to a modification.

[0023] Figure 10B is a circuit diagram showing a configuration example of a comparison section according to another modification.

[0024] Figure 11A is a circuit diagram showing a configuration example of a comparison section according to another modification.

[0025] Figure 11B is a circuit diagram showing a configuration example of a comparison section according to another modification.

[0026] Figure 12A is a circuit diagram showing a configuration example of a comparison section according to another modification.

[0027] Figure 12B is a circuit diagram showing a configuration example of a comparison section according to another modification.

[0028] Figure 13 is a circuit diagram showing a configuration example of a comparison section according to another modification.

[0029] Figure 14 is a circuit diagram showing a configuration example of a comparison section according to another modification.

[0030] Figure 15 is a circuit diagram showing a configuration example of a comparison section according to another modification.

[0031] Figure 16 is a circuit diagram showing a configuration example of a comparison section according to another modification.

[0032] Figure 17 is a circuit diagram showing a configuration example of a comparison section according to another modification.

[0033] Figure 18 is a circuit diagram showing a configuration example of a comparison section according to another modification.

[0034] Figure 19 is a circuit diagram showing a configuration example of a comparison section according to another modification.

[0035] Figure 20 is a circuit diagram showing a configuration example of a comparison section according to another modification.

[0036] Figure 21 is a circuit diagram showing a configuration example of a readout section according to another modification.

[0037] Figure 22 is a circuit diagram showing a configuration example of a readout section according to another modification.

[0038] Figure 23 It shows Figure 22 A circuit diagram showing an example configuration of a readout section is shown.

[0039] Figure 24is a circuit diagram showing a configuration example of a readout section according to another modification.

[0040] Figure 25 is a circuit diagram showing a configuration example of a readout section according to another modification.

[0041] Figure 26 It shows Figure 25 A circuit diagram showing an example configuration of a readout section is shown.

[0042] Figure 27 is a circuit diagram showing a configuration example of a readout section according to another modification.

[0043] Figure 28 is a circuit diagram showing a configuration example of a readout section according to another modification.

[0044] Figure 29 is a circuit diagram showing a configuration example of a readout section according to another modification.

[0045] Figure 30A is a circuit diagram showing a configuration example of a comparison section according to another modification.

[0046] Figure 30B is a circuit diagram showing a configuration example of a comparison section according to another modification.

[0047] Figure 31A is a circuit diagram showing a configuration example of a comparison section according to another modification.

[0048] Figure 31B is a circuit diagram showing a configuration example of a comparison section according to another modification.

[0049] Figure 32 It is an explanatory diagram showing an example of use of the imaging device.

[0050] Figure 33 is a block diagram showing an example of a schematic configuration of a vehicle control system.

[0051] Figure 34 It is a diagram for assisting in explaining an example of the installation positions of the vehicle exterior information detection unit and the imaging unit.

[0052] Figure 35 is a block diagram illustrating a configuration example of a distance measuring device according to an application example.

[0053] Figure 36 It shows Figure 35 A block diagram showing an example of the configuration of a light detection unit is shown.

[0054] Figure 37 It shows Figure 36 A circuit diagram showing an example of the configuration of a pixel is shown.

[0055] Figure 38 It shows Figure 35 The waveform diagram of the operation example of the ranging device shown. DETAILED DESCRIPTION

[0056] Hereinafter, some embodiments of the present disclosure are described in detail with reference to the accompanying drawings. It should be noted that the description is given in the following order.

[0057] 1. Example

[0058] 2. Example of using the camera device

[0059] 3. Application examples for mobile objects

[0060] 4. Application examples of distance measuring devices

[0061] <1. Example>

[0062] [Construction example]

[0063] Figure 1 The image pickup device 1 includes a pixel array 11 , a drive section 12 , a reference signal generation section 13 , a readout section 20 , a signal processing section 14 , and an image pickup control section 15 .

[0064] The pixel array 11 includes a plurality of pixels P arranged in a matrix. The pixels P are each configured to generate a pixel voltage Vpix corresponding to the amount of light received.

[0065] Figure 2 FIG. 1 shows an example of a configuration of a pixel P. The pixel array 11 includes a plurality of control lines TGL, a plurality of control lines RSTL, a plurality of control lines SELL, and a plurality of signal lines VSL. The control lines TGL are arranged in a horizontal direction ( Figure 2 The control lines RSTL extend in the horizontal direction and are connected to the drive section 12 at one end. The control signal SRST is provided to the control lines RSTL by the drive section 12. The control lines SELL extend in the horizontal direction and are connected to the drive section 12 at one end. The control signal SSEL is provided to the control lines SELL by the drive section 12. The signal lines VSL extend in the vertical direction ( Figure 2 The signal lines VSL extend in the longitudinal direction (in the horizontal direction) and one end thereof is connected to the readout section 20. The signal lines VSL transmit the signals SIG generated by the pixels to the readout section 20. Figure 1 and Figure 2 A plurality of pixels P arranged side by side in a row (in the horizontal direction) constitute a pixel line L.

[0066] Each pixel P includes a photodiode PD, a transistor TG, a floating diffusion FD, and transistors RST, AMP, and SEL. The transistors TG, RST, AMP, and SEL in this example are N-type MOS (Metal Oxide Semiconductor) transistors.

[0067] The photodiode PD is a photoelectric conversion unit that generates an amount of charge corresponding to the amount of received light and accumulates the charge therein. The anode of the photodiode PD is grounded, and the cathode is connected to the source of the transistor TG.

[0068] The transistor TG has a gate connected to the control line TGL, a source connected to the cathode of the photodiode PD, and a drain connected to the floating diffusion FD.

[0069] The floating diffusion portion FD is configured to accumulate charges transferred from the photodiode PD via the transistor TG. The floating diffusion portion FD is formed by using, for example, a diffusion layer formed on the front surface of the semiconductor substrate. Figure 2 In FIG. 1 , the floating diffusion FD is shown using the symbol of a capacitor.

[0070] The transistor RST has a gate connected to the control line RSTL, a drain supplied with the power supply voltage VDD, and a source connected to the floating diffusion FD.

[0071] The transistor AMP has a gate connected to the floating diffusion FD, a drain supplied with the power supply voltage VDD, and a source connected to the drain of the transistor SEL.

[0072] The transistor SEL has a gate connected to the control line SELL, a drain connected to the source of the transistor AMP, and a source connected to the signal line VSL.

[0073] With this configuration, in the pixel P, the transistor SEL is turned on based on the control signal SSEL supplied to the control line SELL, thereby electrically connecting the pixel P to the signal line VSL. This causes the transistor AMP to be connected to the constant current source CS (described later) of the readout section 20 and to operate as a so-called source follower. The pixel P then outputs a signal SIG to the signal line VSL, the signal SIG including a voltage corresponding to the voltage of the floating diffusion FD. Specifically, as described later, the pixel P outputs a reset voltage Vreset in the P-phase period TP of the two periods (P-phase period TP and D-phase period TD) in which the readout section 20 performs AD conversion, and outputs a pixel voltage Vpix corresponding to the amount of received light in the D-phase period TD. The pixel P outputs the signal SIG including the reset voltage Vreset and the pixel voltage Vpix to the signal line VSL.

[0074] Drive unit 12 ( Figure 1) is configured to sequentially drive the plurality of pixels P in the pixel array 11 in units of pixel lines L based on an instruction from the imaging control section 15. Specifically, the driving section 12 supplies a plurality of control signals STG to the plurality of control lines TGL in the pixel array 11 on a one-to-one basis, supplies a plurality of control signals SRST to the plurality of control lines RSTL on a one-to-one basis, and supplies a plurality of control signals SSEL to the plurality of control lines SELL on a one-to-one basis, thereby driving the plurality of pixels P in the pixel array 11 on a one-to-one basis.

[0075] The reference signal generating section 13 is configured to generate a reference signal RAMP based on an instruction from the imaging control section 15. The reference signal RAMP has a so-called ramp waveform in which the voltage level gradually changes over time during the two periods (P-phase period TP and D-phase period TD) during which the readout section 20 performs AD conversion. The reference signal generating section 13 supplies the reference signal RAMP to the readout section 20.

[0076] The readout section 20 is configured to generate an image signal DATA0 by performing AD conversion based on a signal SIG supplied from the pixel array 11 via a signal line VSL, based on an instruction from the imaging control section 15 .

[0077] Figure 3 FIG shows a configuration example of the readout section 20. Note that, in addition to the readout section 20, Figure 3 Also shown are a reference signal generating unit 13, a signal processing unit 14, and an imaging control unit 15. The readout unit 20 includes a plurality of constant current sources CS (constant current sources CS[0], CS[1], CS[2], CS[3], ...), a plurality of AD converters ADC (AD converters ADC[0], ADC[1], ADC[2], ADC[3], ...), and a transmission scanning unit 29.

[0078] Multiple constant current sources CS are arranged corresponding to multiple signal lines VSL. Specifically, the 0th constant current source CS[0] is arranged corresponding to the 0th signal line VSL[0], the first constant current source CS[1] is arranged corresponding to the first signal line VSL[1], the second constant current source CS[2] is arranged corresponding to the second signal line VSL[2], and the third constant current source CS[3] is arranged corresponding to the third signal line VSL[3]. The same applies to the fourth and subsequent constant current sources CS. One end of each constant current source CS is connected to the corresponding signal line VSL, and the other end is grounded. Each of the multiple constant current sources CS is configured to apply a predetermined current to the corresponding signal line VSL.

[0079] A plurality of AD converters ADC are provided corresponding to a plurality of signal lines VSL. Specifically, the 0th AD converter ADC[0] is provided corresponding to the 0th signal line VSL[0], the first AD converter ADC[1] is provided corresponding to the first signal line VSL[1], the second AD converter ADC[2] is provided corresponding to the second signal line VSL[2], and the third AD converter ADC[3] is provided corresponding to the third signal line VSL[3]. The same applies to the fourth and subsequent AD converters ADC. Each of the plurality of AD converters ADC is configured to convert the voltage of the signal SIG into a digital code CODE by performing AD conversion based on the signal SIG provided from the pixel array 11. Each AD converter ADC includes a comparing unit 21, a counter 24, and a latch 25.

[0080] The comparison unit 21 is configured to generate a signal CMPO by performing a comparison operation based on a reference signal RAMP supplied from the reference signal generation unit 13 and a signal SIG supplied from the pixel P via the signal line VSL. The comparison unit 21 sets an operating point based on control signals AZSW and AXN supplied from the imaging control unit 15 and then performs a comparison operation. The comparison unit 21 includes a power supply circuit 22 and a comparison circuit 23.

[0081] Figure 4A An example configuration of the comparison unit 21 is shown. The comparison unit 21 is supplied with a power supply voltage VDD0, a ground voltage VSS0, and bias voltages VB1 and VB2. The power supply voltage VDD0 is supplied from the imaging control unit 15 via a power supply line VDDL. The power supply circuit 22 of the comparison unit 21 includes a transistor MN10. The comparison circuit 23 of the comparison unit 21 includes capacitors C1 and C2, transistors MP11, MN11, MP12, and MN12, switches SW1 and SW2, and a capacitor C3. Transistors MP11 and MP12 are P-type MOS transistors, and transistors MN10 to MN12 are N-type MOS transistors. In this example, although not shown, the back gates of transistors MP11 and MP12 are supplied with the power supply voltage VDD0, and the back gates of transistors MN10 to MN12 are supplied with the ground voltage VSS0.

[0082] The transistor MN10 has a gate supplied with a bias voltage VB1, a drain connected to a power supply line VDDL, and a source connected to sources of the transistors MP11 and MP12. The transistor MN10 operates as a so-called source follower, outputting the power supply voltage VDD1 from the source.

[0083] Capacitors C1 and C2 each have one end (terminal T1) and the other end (terminal T2). One end of capacitor C1 is connected to the reference signal generator 13, and the other end is connected to the other end of capacitor C2, the gate of transistor MP11, and one end of switch SW1. One end of capacitor C1 is supplied with a reference signal RAMP generated by reference signal generator 13. One end of capacitor C2 is connected to signal line VSL, and the other end is connected to the other end of capacitor C1, the gate of transistor MP11, and one end of switch SW1. One end of capacitor C2 is supplied with a signal SIG generated by pixel P.

[0084] The gate of transistor MP11 is connected to the other end of capacitors C1 and C2 and one end of switch SW1. Its drain is connected to the drain of transistor MN11, the gate of transistor MP12, and the other end of switch SW1. Its source is connected to the sources of transistors MN10 and MP12. Bias voltage VB2 is applied to the gate of transistor MN11, its drain is connected to the drain of transistor MP11, the gate of transistor MP12, and the other end of switch SW1. Ground voltage VSS0 is applied to the source of transistor MN11. Transistor MN11 serves as a load for transistor MP11 and operates as a constant current source. Switch SW1 is configured to be turned on and off based on control signal AZSW. One end of switch SW1 is connected to the other end of capacitors C1 and C2 and the gate of transistor MP11, and the other end is connected to the drains of transistors MP11 and MN11, as well as the gate of transistor MP12. Transistors MP11 and MN11, as well as switch SW1, are included in primary circuit 101 of comparison circuit 23.

[0085] The gate of transistor MP12 is connected to the drains of transistors MP11 and MN11 and the other end of switch SW1. Its drain is connected to the drain of transistor MN12 and one end of switch SW2. Its source is connected to the sources of transistors MN10 and MP11. The gate of transistor MN12 is connected to one end of capacitor C3 and the other end of switch SW2. Its drain is connected to the drain of transistor MP12 and one end of switch SW2. Its source is supplied with ground voltage VSS0. Switch SW2 is configured to be turned on and off based on control signal AZN. One end of switch SW2 is connected to the drains of transistors MP12 and MN12, and the other end is connected to the gate of transistor MN12 and one end of capacitor C3. One end of capacitor C3 is connected to the gate of transistor MN12 and the other end of switch SW2, and the other end is supplied with ground voltage VSS0. It should be noted that capacitor C3 can be formed using a MOS capacitor or the like, or can be formed using, for example, parasitic capacitance at the gate of transistor MN12, parasitic capacitance at switch SW2, or parasitic capacitance in wiring. The transistors MP12 and MN12 , the switch SW2 , and the capacitor C3 are included in the subsequent-stage circuit 102 of the comparison circuit 23 .

[0086] With this configuration, in the comparison section 21, the power supply circuit 22 generates the power supply voltage VDD1, and the comparison circuit 23 operates based on the power supply voltage VDD1, thereby performing a comparison operation based on the signal SIG and the reference signal RAMP. Specifically, the current generated by the transistor MN11 operating as a constant current source flows through the transistor MN10, and the transistor MN10 operates as a so-called source follower. Therefore, the power supply circuit 22 generates the power supply voltage VDD1. In the comparison circuit 23, as described later, the operating point is set by turning on the switches SW1 and SW2. Then, the comparison circuit 23 performs a comparison operation based on the reference signal RAMP and the reset voltage Vreset included in the signal SIG in the P-phase period TP, and performs a comparison operation based on the reference signal RAMP and the pixel voltage Vpix included in the signal SIG in the D-phase period TD.

[0087] It should be noted that in this example, the comparison section 21 is as follows Figure 4A The comparison unit 21 may be configured as shown, but is not limited thereto. Figure 4B Comparator 21A is configured similarly to the comparison unit 21A shown in FIG. In this example, ground voltage VSS0 is supplied from imaging control unit 15 via ground line VSSL. Comparator 21A includes power supply circuit 22A and comparison circuit 23A. Power supply circuit 22A includes transistor MP20. Comparator circuit 23A includes capacitors C11 and C12, transistors MN21, MP21, MN22, and MP22, switches SW11 and SW12, and capacitor C13. Transistors MP20 and MP22 are P-type MOS transistors, while transistors MN21 and MN22 are N-type MOS transistors.

[0088] The transistor MP20 has a gate supplied with a bias voltage VB1, a drain connected to the ground line VSSL, and a source connected to the sources of the transistors MN21 and MN22. The transistor MP20 operates as a so-called source follower, outputting the ground voltage VSS1 from the source.

[0089] Capacitors C11 and C12 each have one end and another end. One end of capacitor C11 is connected to the reference signal generator 13, and the other end is connected to the other end of capacitor C12, the gate of transistor MN21, and one end of switch SW11. One end of capacitor C11 is supplied with a reference signal RAMP generated by reference signal generator 13. One end of capacitor C12 is connected to signal line VSL, and the other end is connected to the other end of capacitor C11, the gate of transistor MN21, and one end of switch SW11. One end of capacitor C12 is supplied with a signal SIG generated by pixel P.

[0090] Transistor MN21 has a gate connected to the other end of capacitors C11 and C12 and one end of switch SW11. Its drain is connected to the drain of transistor MP21, the gate of transistor MN22, and the other end of switch SW11. Its source is connected to the sources of transistors MP20 and MN22. Bias voltage VB2 is applied to the gate of transistor MP21, its drain is connected to the drain of transistor MN21, the gate of transistor MN22, and the other end of switch SW11. Power supply voltage VDD0 is applied to the source of transistor MP21. Transistor MP21 serves as a load for transistor MN21 and operates as a constant current source. Switch SW11 is configured to be turned on and off based on control signal AZSW. One end of switch SW11 is connected to the other end of capacitors C11 and C12 and the gate of transistor MN21, and the other end is connected to the drains of transistors MN21 and MP21, as well as the gate of transistor MN22. Transistors MN21 and MP21, as well as switch SW11, are included in primary circuit 101 of comparison circuit 23A.

[0091] Transistor MN22 has a gate connected to the drains of transistors MN21 and MP21 and the other end of switch SW11. Its drain is connected to the drain of transistor MP22 and one end of switch SW12. Its source is connected to the sources of transistors MP20 and MN21. Transistor MP22 has a gate connected to one end of capacitor C13 and the other end of switch SW12. Its drain is connected to the drain of transistor MN22 and one end of switch SW12. Its source is supplied with power supply voltage VDD0. Switch SW12 is configured to be turned on and off based on control signal AZN. One end of switch SW12 is connected to the drains of transistors MN22 and MP22, and the other end is connected to the gate of transistor MP22 and one end of capacitor C13. One end of capacitor C13 is connected to the gate of transistor MP22 and the other end of switch SW12, and the other end is supplied with power supply voltage VDD0. Transistors MN22 and MP22, switch SW12, and capacitor C13 are included in the subsequent-stage circuit 102 of comparison circuit 23A.

[0092] Figure 5 1 shows an example of connection between the power supply line VDDL and the plurality of comparison units 21. Note that in this figure, the transistor MN11 of the comparison circuit 23 is represented by the symbol of a constant current source, and the subsequent circuit 102 of the comparison circuit 23 (transistors MP12 and MN12, switch SW2, and capacitor C3) is represented by the symbol of an amplifier circuit.

[0093] like Figure 3 and Figure 5As shown, the imaging control section 15 supplies the power supply voltage VDD0 to the plurality of comparison sections 21 via the power supply line VDDL. In each of the plurality of comparison sections 21, the power supply circuit 22 (transistor MN10) generates a power supply voltage VDD1 based on the power supply voltage VDD0 and supplies the generated power supply voltage VDD1 to the comparison circuit 23. The comparison circuit 23 then performs a comparison operation based on the reference signal RAMP and the signal SIG, and generates a signal CMPO.

[0094] Counter 24( Figure 3 ) is configured to perform a counting operation based on the signal CMPO supplied from the comparison section 21 and the control signal CTL supplied from the imaging control section 15. In the counting operation, pulses of the clock signal CLK supplied from the imaging control section 15 are counted.

[0095] The latch 25 is configured to generate a digital code CODE based on the count value obtained by the counter 24 and to hold the digital code CODE. Specifically, the latch 25 generates a digital code CODE corresponding to the difference (CNTD-CNTP) between the count value CNTP obtained by the counter 24 in the P-phase period TP and the count value CNTD obtained by the counter 24 in the D-phase period TD. The latch 25 then outputs the digital code CODE to the bus wiring BUS based on a control signal supplied from the transmission scanning section 29.

[0096] The transmission scanning unit 29 is configured to control the latches 25 of the plurality of AD converters ADC to sequentially output the digital codes CODE to the bus wiring BUS based on a control signal CTL2 supplied from the imaging control unit 15. The readout unit 20 sequentially transmits the plurality of digital codes CODE supplied from the plurality of AD converters ADC to the signal processing unit 14 as image signals DATA0 using the bus wiring BUS.

[0097] Signal processing unit 14 ( Figure 1 ) is configured to generate an image signal DATA by performing predetermined signal processing on the image signal DATA0 based on an instruction from the imaging control section 15, and output the image signal DATA.

[0098] The imaging control section 15 is configured to supply control signals to the driver 12, the reference signal generator 13, the readout section 20, and the signal processing section 14, and to control the operation of these circuits, thereby controlling the operation of the imaging device 1. Specifically, the imaging control section 15 supplies control signals to the driver 12, thereby controlling the driver 12 to sequentially drive the plurality of pixels P in the pixel array 11 in units of pixel lines L. Furthermore, the imaging control section 15 supplies control signals to the reference signal generator 13, thereby controlling the reference signal generator 13 to generate a reference signal RAMP. Furthermore, the imaging control section 15 supplies the power supply voltage VDD0 and bias voltages VB1 and VB2 to the readout section 20, and supplies control signals AZSW, AZN, CTL, and CTL2, as well as a clock signal CLK, to the readout section 20, thereby controlling the readout section 20 to generate the image signal DATA0 by performing A / D conversion based on the signal SIG. Furthermore, the imaging control section 15 supplies control signals to the signal processing section 14, thereby controlling the operation of the signal processing section 14.

[0099] Next, the implementation of the imaging device 1 will be described. In the imaging device 1, for example, Figure 1 Each of the blocks shown may be formed in one semiconductor substrate, or may be formed in a plurality of semiconductor substrates.

[0100] Figure 6 This embodiment of an imaging device 1 is shown in which each block is formed on a single semiconductor substrate 200. A pixel array 11 is provided on the semiconductor substrate 200, and a driver 12 is provided to the left of the pixel array 11. Furthermore, a readout section 20 is provided below the pixel array 11. Within the readout section 20, a constant current source section 201 including multiple constant current sources CS, a comparison circuit section 202 including multiple comparison sections 21, a counter section 203 including multiple counters 24, a latch section 204 including multiple latches 25, and a transfer scanning section 29 are arranged in this order from the top. A reference signal generator 13 and an imaging control section 15 are provided to the left of the readout section 20. Furthermore, a signal processor 14 is provided to the right of the pixel array 11 and the readout section 20.

[0101] Figure 7An embodiment of an imaging device 1 is shown in which each block is formed in two semiconductor substrates 211 and 212. For example, the pixel array 11 is provided in the semiconductor substrate 211, while the readout unit 20, the drive unit 12, the reference signal generation unit 13, the signal processing unit 14, and the imaging control unit 15 are provided in the semiconductor substrate 212. The semiconductor substrates 211 and 212 are stacked one on top of the other. The plurality of signal lines VSL arranged in the semiconductor substrate 211 are electrically connected to the readout unit 20 arranged in the semiconductor substrate 212 via, for example, TSVs (Through Silicon Vias), and the plurality of control lines TGL, RSTL, and SELL arranged in the semiconductor substrate 211 are electrically connected to the drive unit 12 arranged in the semiconductor substrate 212 via, for example, TSVs. The readout section 20 is provided in the semiconductor substrate 212, and the drive section 12, the reference signal generation section 13, and the imaging control section 15 are provided on the left side of the readout section 20, and the signal processing section 14 is provided on the right side of the readout section 20. In the readout section 20, a constant current source section 201 including a plurality of constant current sources CS, a comparison circuit section 202 including a plurality of comparison sections 21, a counter section 203 including a plurality of counters 24, a latch section 204 including a plurality of latches 25, and a transmission scanning section 29 are arranged in this order from the top.

[0102] In each block, the above method ( Figure 7 ) are formed in two semiconductor substrates 211 and 212, by providing the pixel array 11 primarily in the semiconductor substrate 211, the semiconductor substrate 211 can be manufactured using a semiconductor manufacturing process specific to pixels. That is, the semiconductor substrate 211 does not include any circuits other than the pixel array 11. Therefore, for example, even when a specific manufacturing process is used to form pixels, that manufacturing process does not affect circuits other than the pixel array 11. Therefore, in the imaging device 1, a semiconductor manufacturing process specific to pixel formation can be used, thereby improving the imaging characteristics of the imaging device 1.

[0103] Here, pixel P corresponds to a specific example of a "first pixel" in the present disclosure. Comparator 21 corresponds to a specific example of a "first comparing unit" in the present disclosure. Power supply circuit 22 corresponds to a specific example of a "first power supply circuit" in the present disclosure. Comparator 23 corresponds to a specific example of a "first comparing circuit" in the present disclosure. Transistor MN10 corresponds to a specific example of a "first power supply transistor" in the present disclosure. Capacitor C1 corresponds to a specific example of a "first capacitor" in the present disclosure. Capacitor C2 corresponds to a specific example of a "second capacitor" in the present disclosure. Transistor MP11 corresponds to a specific example of a "first transistor" in the present disclosure. Switch SW1 corresponds to a specific example of a "first switch" in the present disclosure. Transistor MN11 corresponds to a specific example of a "first current source" in the present disclosure. Transistor MP12 corresponds to a specific example of a "second transistor" in the present disclosure. Transistor MN12 corresponds to a specific example of a "third transistor" in the present disclosure. Switch SW2 corresponds to a specific example of a "second switch" in the present disclosure.

[0104] [Operation and function]

[0105] Next, the operation and effects of the image pickup apparatus 1 according to the present embodiment will be described.

[0106] (Overview of overall operation)

[0107] First, refer to Figure 1 The overall operation of the imaging device 1 is briefly described. The drive unit 12 sequentially drives the plurality of pixels P in the pixel array 11 in units of pixel lines L based on instructions from the imaging control unit 15. Each pixel P outputs a reset voltage Vrest as a signal SIG during the P-phase period TP, and outputs a pixel voltage Vpix corresponding to the amount of received light as a signal SIG during the D-phase period TD. The reference signal generation unit 13 generates a reference signal RAMP based on instructions from the imaging control unit 15. The readout unit 20 generates an image signal DATA0 by performing A / D conversion based on the signal SIG supplied from the pixel array 11 via the signal line VSL based on instructions from the imaging control unit 15. The signal processing unit 14 generates an image signal DATA by performing predetermined signal processing on the image signal DATA0 based on instructions from the imaging control unit 15. The imaging control unit 15 provides control signals to the drive unit 12, the reference signal generation unit 13, the readout unit 20, and the signal processing unit 14, and controls the operation of these circuits, thereby controlling the operation of the imaging device 1.

[0108] (Detailed operation)

[0109] In the imaging device 1, each of the plurality of pixels P accumulates charges corresponding to the amount of light received and outputs a pixel voltage Vpix corresponding to the amount of light received as a signal SIG. The readout unit 20 then performs AD conversion based on the signal SIG. This operation will be described in detail below.

[0110] Figure 8 An example of an operation of scanning a plurality of pixels P in the pixel array 11 is shown.

[0111] During the period from time t0 to time t1, the imaging device 1 sequentially exposes the pixel array 11 vertically, starting from the top, and starts driving D1. Specifically, the driver 12 generates control signals STG and SRST, for example, to sequentially select pixel lines L and sequentially turn on transistors TG and RST in each pixel P for a predetermined period of time. Consequently, in each pixel P, the voltage across the floating diffusion FD and the cathode of the photodiode PD are set to the power supply voltage VDD. Then, transistors TG and RST are turned off, causing the photodiode PD to begin accumulating charge corresponding to the amount of light received. Thus, the exposure period T begins sequentially in each of the pixels P.

[0112] During the period from time t2 to time t3, the imaging device 1 sequentially performs readout drive D2 on the pixel array 11 in the vertical direction, starting from the top. Specifically, as described later, the drive unit 12 sequentially selects pixel lines L by generating control signals STG and SRST. Consequently, the pixels P output a reset voltage Vreset as a signal SIG during the P-phase period TP and a pixel voltage Vpix as a signal SIG during the D-phase period TD. The readout unit 20 generates a digital code CODE by performing A / D conversion based on the signal SIG.

[0113] The image pickup device 1 repeats the exposure start drive D1 and the readout drive D2, thereby obtaining a captured image.

[0114] Next, the readout drive D2 will be described in detail. Next, focusing on a certain pixel P (pixel P1) among the plurality of pixels P, the operations of the pixel P1 and the AD converter ADC (AD converter ADC1) connected to the pixel P1 will be described in detail.

[0115] Figure 9FIG1 shows an example of the operation of the readout driver D2 in the pixel of interest P1, wherein (A) shows the waveform of the control signal SSEL, (B) shows the waveform of the control signal SRST, (C) shows the waveform of the control signal STG, (D) shows the waveform of the signal SIG, (E) shows the waveform of the control signal AZSW, (F) shows the waveform of the reference signal RAMP, (G) shows the waveform of the gate voltage Vg of the transistor MP11 in the comparison unit 21 of the AD converter ADC1, and (H) shows the waveform of the signal CMPO in the AD converter ADC1. The waveform of the control signal AZN is the same as that of the control signal AZSW.

[0116] In the imaging device 1, within a certain horizontal period (H), pixel P1 first performs a reset operation to output a reset voltage Vrest, and the AD converter ADC1 performs AD conversion based on the reset voltage Vreset during the P-phase period TP. Then, pixel P1 performs a charge transfer operation to output a pixel voltage Vpix, and the AD converter ADC1 performs AD conversion based on the pixel voltage Vpix during the D-phase period TD. This operation is described in detail below.

[0117] First, at time t11, when the horizontal period H starts, the driving section 12 changes the voltage of the control signal SSEL from the low level to the high level ( Figure 9 (A)). Therefore, in the pixel P1, the transistor SEL is turned on, and the pixel P1 is electrically connected to the signal line VSL. In addition, at time t11, the driving unit 12 changes the voltage of the control signal SRST from a low level to a high level ( Figure 9 (B)). Therefore, in the pixel P1, the transistor RST is turned on, and the voltage of the floating diffusion portion FD is set to the power supply voltage VDD (reset operation). Then, the pixel P1 outputs a voltage corresponding to the voltage of the floating diffusion portion FD at this time (reset voltage Vreset). Therefore, the voltage of the signal SIG becomes the reset voltage Vreset ( Figure 9 (D)).

[0118] Furthermore, at time t11, the reference signal generating unit 13 changes the reference signal RAMP to the voltage V1 ( Figure 9 (F)). In addition, at time t11, the imaging control unit 15 changes the voltages of the control signals AZSW and AZN from low level to high level ( Figure 9 (E)). Therefore, the two switches SW1 and SW2 in the comparison unit 21 of the AD conversion unit ADC1 are turned on. By turning on the switch SW1, the gate voltage Vg of the transistor MP11 becomes the same voltage (voltage V2) as the drain voltage of the transistor MP11 ( Figure 9(G)) to set the voltages of the capacitors C1 and C2. In addition, by turning on the switch SW2, the gate voltage of the transistor MN12 becomes the same voltage as the drain voltage of the transistor MN12 to set the voltage of the capacitor C3. Therefore, the voltage of the signal CMPO becomes the voltage V3 ( Figure 9 Therefore, the comparison section 21 performs the operation point setting operation.

[0119] Next, at time t12, the driving unit 12 changes the voltage of the control signal SRST from high level to low level ( Figure 9 (B)). Therefore, in pixel P1, transistor RST is turned off.

[0120] Next, at time t13, the imaging control unit 15 changes the voltages of the control signals AZSW and AZN from high level to low level ( Figure 9 (E)). Therefore, in the comparison section 21 of the AD conversion section ADC1, the two switches SW1 and SW2 are turned off, and the operating point setting operation ends. Thereafter, the comparison section 21 operates to compare the gate voltage Vg with the voltage V2.

[0121] Next, at time t14, the reference signal generating unit 13 reduces the voltage of the reference signal RAMP from the voltage V1 to the voltage V4 ( Figure 9 Therefore, in the comparison unit 21 of the AD conversion unit ADC1, the gate voltage Vg of the transistor MP11 becomes a voltage lower than the voltage V2 ( Figure 9 (G)), thereby reducing the voltage of the signal CMPO ( Figure 9 In other words, the comparison section 21 compares the gate voltage Vg with the voltage V2, and the gate voltage Vg is lower than the voltage V2, thereby changing the voltage of the signal CMPO to a low level.

[0122] Next, in the period from time t15 to time t17 (P-phase period TP), the AD conversion unit ADC1 performs AD conversion based on the reset voltage Vreset. Specifically, first, at time t15, the reference signal generation unit 13 starts to increase the voltage of the reference signal RAMP from the voltage V4 at a predetermined rate of change ( Figure 9 Therefore, in the comparison unit 21 of the AD conversion unit ADC1, the gate voltage Vg of the transistor MP11 starts to increase ( Figure 9 (G)). In addition, at time t15, the imaging control section 15 starts generating the clock signal CLK. The counter 24 of the AD conversion section ADC1 performs a counting operation to count the pulses of the clock signal CLK.

[0123] Then, at time t16, the gate voltage Vg exceeds the voltage V2 ( Figure 9Therefore, the comparison unit 21 of the AD conversion unit ADC1 changes the voltage of the signal CMPO from the low level to the high level ( Figure 9 (H)). That is, comparator 21 compares gate voltage Vg with voltage V2, and gate voltage Vg exceeds voltage V2, thereby changing the voltage of signal CMPO from a low level to a high level. Counter 24 of analog-to-digital converter ADC1 stops counting based on this transition in signal CMPO. At this point, the count value of counter 24 is CNTP. Latch 25 of analog-to-digital converter ADC1 latches this count value CNTP as the count value during P-phase period TP. Counter 24 is then reset.

[0124] Next, at time t17, the reference signal generating section 13 sets the voltage of the reference signal RAMP to the voltage V1 at the end of the P-phase period TP. In addition, at time t17, the imaging control section 15 stops generating the clock signal CLK.

[0125] Then, at time t17, the driving unit 12 changes the voltage of the control signal STG from the low level to the high level ( Figure 9 (C)). Therefore, in the pixel P1, the transistor TG is turned on, and the charge generated in the photodiode PD is transferred to the floating diffusion FD (charge transfer operation). Then, the pixel P1 outputs a voltage (pixel voltage Vpix) corresponding to the voltage of the floating diffusion FD at this time. Therefore, the voltage of the signal SIG becomes the pixel voltage Vpix ( Figure 9 (D)). Figure 9 Two pixel voltages Vpix (pixel voltages Vpix1 and Vpix2) different from each other are shown as an example. The voltage of the signal SIG is reduced in the above manner, so that in the comparison section 21 of the AD conversion section ADC1, the gate voltage Vg of the transistor MP11 is reduced ( Figure 9 (G)). The gate voltage Vg changes to a voltage corresponding to the pixel voltage Vpix. By reducing the gate voltage Vg in this way, the voltage of the signal CMPO is reduced ( Figure 9 That is, the comparison section 21 compares the gate voltage Vg with the voltage V2, and the gate voltage Vg is lower than the voltage V2, thereby changing the voltage of the signal CMPO to a low level.

[0126] Next, at time t18, the driving unit 12 changes the voltage of the control signal STG from the high level to the low level ( Figure 9 (C)). Therefore, in pixel P1, transistor TG is turned off.

[0127] Next, at time t19, the reference signal generating unit 13 reduces the voltage of the reference signal RAMP from the voltage V1 to the voltage V4 ( Figure 9Therefore, in the comparison unit 21 of the AD conversion unit ADC1, the gate voltage Vg of the transistor MP11 decreases ( Figure 9 (G)).

[0128] Next, in the period from time t20 to time t23 (D phase period TD), the AD conversion section ADC1 performs AD conversion based on the pixel voltage Vpix. Specifically, first, at time t20, the reference signal generation section 13 starts to increase the voltage of the reference signal RAMP from the voltage V4 at a predetermined rate of change ( Figure 9 Therefore, in the comparison unit 21 of the AD conversion unit ADC1, the gate voltage Vg of the transistor MP11 starts to increase ( Figure 9 (G)). In addition, at time t20, the imaging control section 15 stops generating the clock signal CLK. The counter 24 of the AD conversion section ADC1 performs a counting operation to count the pulses of the clock signal CLK.

[0129] When the pixel voltage Vpix is ​​the voltage Vpix1, at time t21, the gate voltage Vg exceeds the voltage V2 ( Figure 9 Therefore, the comparison unit 21 of the AD conversion unit ADC1 changes the voltage of the signal CMPO from the low level to the high level ( Figure 9 That is, the comparison unit 21 compares the gate voltage Vg with the voltage V2, and the gate voltage Vg exceeds the voltage V2, thereby changing the voltage of the signal CMPO from the low level to the high level.

[0130] When the pixel voltage Vpix is ​​Vpix2, the gate voltage Vg exceeds the voltage V2 ( Figure 9 Therefore, the comparison unit 21 of the AD conversion unit ADC1 changes the voltage of the signal CMPO from the low level to the high level ( Figure 9 (H)).

[0131] The counter 24 of the AD converter ADC1 stops the counting operation based on this transition of the signal CMPO. At this time, the count value of the counter 24 is CNTD. The latch 25 of the AD converter ADC1 latches the count value CNTD as the count value in the D-phase period TD. Then, the counter 24 is reset.

[0132] Next, at time t23, the reference signal generating section 13 sets the voltage of the reference signal RAMP to the voltage V1 ( Figure 9 (F)). In addition, at time t23, the imaging control unit 15 stops generating the clock signal CLK. Then, at time t23, the driving unit 12 changes the voltage of the control signal SSEL from high level to low level ( Figure 9(A)). Therefore, in the pixel P1, the transistor SEL is turned off, thereby electrically isolating the pixel P1 from the signal line SGL.

[0133] Then, the latch 25 of the AD conversion section ADC1 generates a digital code CODE corresponding to a difference (CNTD−CNTP) between the count value CNTP obtained by the counter 24 in the P-phase period TP and the count value CNTD obtained by the counter 24 in the D-phase period TD.

[0134] As described above, in the imaging device 1, a count value CNTP is obtained by performing a counting operation based on the reset voltage Vreset during the P-phase period TP, and a count value CNTD is obtained by performing a counting operation based on the pixel voltage Vpix during the D-phase period TD. Then, in the imaging device 1, a digital code CODE corresponding to the difference (CNTD-CNTP) between the count values ​​CNTP and CNTD is generated. By performing such correlated double sampling in the imaging device 1, noise components contained in the pixel voltage Vpix can be removed. Consequently, the image quality of the captured image can be improved.

[0135] As described above, in the imaging device 1, each of the multiple comparing units 21 includes a power supply circuit 22. This reduces interference between the multiple AD converters ADC. For example, if none of the multiple comparing units 21 were provided with a power supply circuit 22, when a comparing unit 21 in a particular AD converter ADC causes a transition in signal CMPO, transient current could generate noise in the power supply voltage VDD0. In this case, this noise could potentially affect the operation of other AD converters via the power supply line VDDL. In the imaging device 1, since each of the multiple comparing units 21 includes a power supply circuit 22, the likelihood of noise in the power supply voltage VDD0 caused by transient current when a comparing unit 21 in a particular AD converter ADC causes a transition in signal CMPO is reduced. Therefore, in the imaging device 1, the likelihood of stripes appearing in captured images, for example, can be reduced. As a result, the image quality of captured images can be improved.

[0136] [Effect]

[0137] As described above, in this embodiment, since each of the plurality of comparing sections includes a power supply circuit, the image quality of the captured image can be improved.

[0138] [Variation 1]

[0139] In the above-described embodiment, for example, although Figure 4AThe comparison circuit 23 of the comparison unit 21 shown in FIG. 1 is provided with four transistors MP11, MN11, MP12 and MN12, but is not limited thereto. Figure 10A Like the comparison circuit 23B of the comparison unit 21B shown in FIG. , a transistor MN13 may also be provided. Transistor MN13 is an N-type MOS transistor, and its gate is supplied with signal CMPO, its drain is connected to the sources of transistors MN10, MP11, and MP12, and its source is connected to the drains of transistors MP11 and MN11, the gate of transistor MP12, and the other end of switch SW1. Here, transistor MN13 corresponds to a specific example of a "fourth transistor" in this disclosure. Transistor MN13 performs control based on the voltage of signal CMPO to prevent the drain voltage of transistor MN11, which operates as a constant current source, from becoming too low. Therefore, for example, the constant current characteristic of transistor MN11 can be maintained, and interference between multiple AD conversion units ADC can be suppressed.

[0140] In this example, although this modification is applied to the comparison section 21 ( Figure 4A ), but this modification can also be applied to, for example, the comparison unit 21A ( Figure 4B ). Specifically, for example, Figure 10B As shown in FIG1 , a transistor MP23 can be provided, similar to the comparison circuit 23C of the comparison unit 21C. Transistor MP23 is a P-type MOS transistor. Signal CMPO is supplied to its gate, its drain is connected to the sources of transistors MP20, MN21, and MN22, and its source is connected to the drains of transistors MN21 and MP21, the gate of transistor MN22, and the other end of switch SW11. Transistor MP23 is controlled based on the voltage of signal CMPO to prevent the drain voltage of transistor MP21, which operates as a constant current source, from becoming excessively high. This, for example, maintains the constant current characteristics of transistor MP21 and suppresses interference between the multiple analog-to-digital converters (ADCs).

[0141] [Variation 2]

[0142] In the above embodiment, for example, Figure 4A In the power supply circuit 22 of the comparison unit 21 shown in FIG. 1 , the bias voltage VB1 is constantly supplied to the gate of the transistor MN10, but the present invention is not limited thereto. Alternatively, for example, a sample-and-hold circuit may be provided, and the bias voltage VB1 may be supplied to the gate of the transistor MN10 only during a predetermined period. Figure 10A An example of the case of the comparison unit 21B is shown.

[0143] Figure 11AThe diagram shows an example configuration of a comparison unit 21D according to this variation. Comparison unit 21D includes a power supply circuit 22D and a comparison circuit 23B. Power supply circuit 22D includes a capacitor C4 and a switch SW3. One end of capacitor C4 is connected to the gate of transistor MN10 and one end of switch SW3, while the other end is supplied with a DC voltage VREF. Voltage VREF is generated by the imaging control unit 15. Note that capacitor C4 can be constructed using, for example, a MOS capacitor, or can be constructed using parasitic capacitance at the gate of transistor MN10, parasitic capacitance at switch SW3, or parasitic capacitance in wiring. Switch SW3 is configured to be turned on and off based on a control signal SHSW. One end of switch SW3 is connected to the gate of transistor MN10 and one end of capacitor C4, while the other end is supplied with a bias voltage VB1. Control signal SHSW is generated by the imaging control unit 15. The sample-and-hold circuit includes capacitor C4 and switch SW3. Capacitor C4 corresponds to a specific example of a "fourth capacitor" in this disclosure. The switch SW3 corresponds to a specific example of a “fourth switch” in the present disclosure.

[0144] For example, the switch SW3 is turned on during the period when the switches SW1 and SW2 are turned on, and is turned off during the period when the switches SW1 and SW2 are turned off. Figure 9 In the readout driver D2 shown, switch SW3 is turned on during the period from time t11 to time t13. Therefore, the gate voltage of transistor MN10 is set to bias voltage VB1. Then, switch SW3 is turned on during the period from time t13 to time t23. Therefore, the gate voltage of transistor MN10 is maintained at bias voltage VB1. In comparison unit 21D, switch SW3 is turned off during the P-phase period TP and the D-phase period TD. Therefore, when comparison unit 21D causes signal CMPO to transition in a particular AD converter ADC, generating noise in the gate of transistor MN10, the likelihood of this noise affecting the operation of other AD converters ADC can be reduced. As a result, interference between multiple AD converters ADC can be suppressed.

[0145] Likewise, for example, this modification can be applied to the comparison section 21A ( Figure 4B ), or this modification example can be applied to the comparison unit 21C ( Figure 10B ). Figure 11B The present modification example is applied to the comparison unit 21C ( Figure 10B) is an example of the configuration of the comparison unit 21E in the case of a CMOS circuit. The comparison unit 21E includes a power supply circuit 22E and a comparison circuit 23C. The power supply circuit 22E includes a capacitor C14 and a switch SW13. One end of the capacitor C14 is connected to the gate of the transistor MP20 and one end of the switch SW13, and the other end is supplied with a voltage VREF. The switch SW13 is configured to be turned on and off based on a control signal SHSW. One end of the switch SW13 is connected to the gate of the transistor MP20 and one end of the capacitor C14, and the other end is supplied with a bias voltage VB1. Therefore, as with the comparison unit 21D, the comparison unit 21E can also suppress interference between the multiple analog-to-digital converters ADC.

[0146] [Variation 3]

[0147] In the above embodiment, for example, Figure 4A In the comparison circuit 23 of the comparison section 21 shown in FIG. 1 , the bias voltage VB2 is constantly supplied to the gate of the transistor MN11 operating as a current source, but the present invention is not limited thereto. Alternatively, for example, a sample-and-hold circuit may be provided, and the bias voltage VB2 may be supplied to the gate of the transistor MN11 only during a predetermined period. Figure 11A An example of the case of the comparison unit 21D is shown.

[0148] Figure 12A The following diagram illustrates an example configuration of a comparison unit 21F according to this modified example. The comparison unit 21F includes a power supply circuit 22D and a comparison circuit 23F. The comparison circuit 23F includes a capacitor C5 and a switch SW4. One end of the capacitor C5 is connected to the gate of the transistor MN11 and one end of the switch SW4, while the other end is supplied with a DC voltage VREF. Voltage VREF is generated by the imaging control unit 15. Note that, for example, the capacitor C5 can be constructed using a MOS capacitor, or can be constructed using parasitic capacitance at the gate of the transistor MN11, parasitic capacitance at the switch SW4, or parasitic capacitance in wiring. The switch SW4 is configured to be turned on and off based on a control signal SHSW2. One end of the switch SW4 is connected to the gate of the transistor MN11 and one end of the capacitor C5, while the other end is supplied with a bias voltage VB2. The control signal SHSW2 is generated by the imaging control unit 15. The sample-and-hold circuit includes the capacitor C5 and the switch SW4. Here, the switch SW4 corresponds to a specific example of the "sixth switch" in this disclosure.

[0149] For example, the switch SW4 is turned on during the period when the switches SW1 and SW2 are turned on, and is turned off during the period when the switches SW1 and SW2 are turned off. Figure 9In the readout driver D2 shown, switch SW4 is turned on during the period from time t11 to time t13. Therefore, the gate voltage of transistor MN11 is set to bias voltage VB2. Then, switch SW4 is turned on during the period from time t13 to time t23. Therefore, the gate voltage of transistor MN11 is maintained at bias voltage VB2. In comparison unit 21F, switch SW4 is turned off during the P-phase period TP and the D-phase period TD. Therefore, when comparison unit 21F causes signal CMPO to transition in a particular AD converter ADC, generating noise in the gate of transistor MN11, the likelihood of this noise affecting the operation of other AD converters ADC can be reduced. As a result, interference between multiple AD converters ADC can be suppressed.

[0150] Likewise, for example, this modification can be applied to the comparison section 21A ( Figure 4B ), this modification can be applied to the comparison unit 21C ( Figure 10B ), or this modification example can be applied to the comparison unit 21E ( Figure 11B ). Figure 12B The present modification example is applied to the comparison unit 21E ( Figure 11B ). Comparison unit 21G includes a power supply circuit 22E and a comparison circuit 23G. Comparison circuit 23G includes a capacitor C15 and a switch SW14. One end of capacitor C15 is connected to the gate of transistor MP21 and one end of switch SW14, while the other end is supplied with voltage VREF. Switch SW14 is configured to be turned on and off based on control signal SHSW2. One end of switch SW14 is connected to the gate of transistor MP21 and one end of capacitor C15, while the other end is supplied with bias voltage VB2. Therefore, as with comparison unit 21F, comparison unit 21G can also suppress interference between multiple analog-to-digital converters (ADCs).

[0151] [Variation 4]

[0152] In the above embodiment, for example, Figure 4A As shown in FIG. 21 , the primary circuit 101 of the comparison circuit 23 is constituted by using two transistors MP11 and NM11, but is not limited thereto. Alternatively, for example, Figure 13 The primary circuit 101 can be configured by using a plurality of transistors, as in the comparison unit 21H shown in FIG. The primary circuit 101 of the comparison unit 21H includes transistors MN11, MP11, MP13, and MN14.

[0153] Transistor MP13 is a P-type MOS transistor. Bias voltage VB3 is applied to its gate. Its drain is connected to the drain of transistor MN14, the input terminal of the subsequent circuit 102, and the other end of switch SW1. Its source is connected to the drain of transistor MP11. Bias voltage VB3 is generated by the imaging control unit 15. The source of transistor MP11 is grounded, and the gate of transistor MP13 is grounded. Thus, transistors MP11 and MP13 form a cascade circuit.

[0154] The transistor MN14 is an N-type MOS transistor. A bias voltage VB4 is applied to the gate of the transistor MN14. The drain of the transistor MN14 is connected to the drain of the transistor MP13, the input terminal of the subsequent circuit 102, and the other end of the switch SW1. The source of the transistor MN14 is connected to the drain of the transistor MN11. The bias voltage VB4 is generated by the imaging control unit 15. The transistors MN11 and MN14 are included in a cascade circuit.

[0155] With this configuration, in the comparison circuit 23H, the small signal gain can be increased, thereby achieving a more stable comparison operation. In addition, by providing the transistors MP13 and MN14, the kickback noise from the subsequent stage circuit 102 can be reduced.

[0156] [Variation 5]

[0157] In the above embodiment, for example, Figure 4A As shown in the comparison unit 21, in the power supply circuit 22, the transistor MN10 operates as a source follower, but the present invention is not limited to this. Alternatively, for example, multiple transistors may be provided, and the multiple transistors may operate as a multi-stage source follower. This modification will be described in detail with reference to some examples.

[0158] Figure 14 1 and 2. The comparison section 21J according to the present modification is shown as an example of a configuration. The comparison section 21J includes a power supply circuit 22J and a comparison circuit 23. The power supply circuit 22J includes transistors MN10 and MN15, a capacitor C6, and a switch SW5.

[0159] Transistor MN10 has a gate supplied with bias voltage VB1, a drain connected to power supply line VDDL, and a source connected to the drain of transistor MN15. Transistor MN15 is an N-type MOS transistor. Its gate is connected to one end of capacitor C6 and one end of switch SW5, its drain is connected to the source of transistor MN10, and its source is connected to the source of transistor MP11 and the power supply terminal of the subsequent-stage circuit 102. Capacitor C6 has one end connected to the gate of transistor MN15 and one end of switch SW5, and its other end supplied with DC voltage VREF. Voltage VREF is generated by the camera control unit 15. Switch SW5 is configured to be turned on and off based on a control signal SHSW. One end of switch SW5 is connected to the gate of transistor MN15 and one end of capacitor C6, and its other end supplied with bias voltage VB5. Control signal SHSW and bias voltage VB5 are generated by the camera control unit 15. Capacitor C6 and switch SW5 are included in a sample-and-hold circuit. For example, the switch SW5 is turned on during the period when the switch SW1 is turned on, and is turned off during the period when the switch SW1 is turned off. Here, the transistor MN15 corresponds to a specific example of the "second power supply transistor" in the present disclosure. The switch SW5 corresponds to a specific example of the "fifth switch" in the present disclosure.

[0160] With this configuration, in the comparison unit 21J, the current generated by the transistor MN11, which operates as a constant current source, is applied to the transistors MN10 and MN15, and the transistors MN10 and MN15 operate as a two-stage source follower circuit. Consequently, the power supply circuit 22J generates the power supply voltage VDD1. Therefore, by providing a two-stage source follower circuit in the comparison unit 21J, the possibility of noise from the power supply voltage VDD0 generated by the transient current when the comparison unit 21J transitions the signal CMPO in one AD converter ADC being affected by the operation of other AD converters ADC can be reduced. As a result, interference between the multiple AD converters ADC can be suppressed.

[0161] Figure 15 1 and 2. The comparison section 21K according to the present modification is shown as an example of a configuration. The comparison section 21K includes a power supply circuit 22K and a comparison circuit 23. The power supply circuit 22K includes transistors MN10 and MN15, an operational amplifier OPA, a capacitor C6, and a switch SW5.

[0162] Transistor MN10 has a gate connected to the output terminal of operational amplifier OPA, a drain connected to power supply line VDDL, and a source connected to the drain of transistor MN15 and the inverting input terminal of operational amplifier OPA. Operational amplifier OPA has a non-inverting input terminal supplied with bias voltage VB1, an inverting input terminal connected to the source of transistor MN10 and the drain of transistor MN15, and an output terminal connected to the gate of transistor MN10.

[0163] The gate of transistor MN15 is connected to one end of capacitor C6 and one end of switch SW5. The drain is connected to the source of transistor MN10 and the inverting input terminal of operational amplifier OPA. The source is connected to the source of transistor MP11 and the power supply terminal of subsequent circuit 102. One end of capacitor C6 is connected to the gate of transistor MN15 and one end of switch SW5, and the other end is supplied with a DC voltage VREF. Voltage VREF is generated by the camera control unit 15. Switch SW5 is configured to be turned on and off based on a control signal SHSW. One end of switch SW5 is connected to the gate of transistor MN15 and one end of capacitor C6, and the other end is supplied with a bias voltage VB5. Control signal SHSW and bias voltage VB5 are generated by the camera control unit 15. Capacitor C6 and switch SW5 are included in a sample-and-hold circuit. For example, switch SW5 is turned on when switch SW1 is on and is turned off when switch SW1 is off.

[0164] With this configuration, in comparison unit 21K, negative feedback is performed to equalize the source voltage of transistor MN10 to bias voltage VB1. The current generated by transistor MN1, operating as a constant current source, is then applied to transistors MN10 and MN15, and transistors MN10 and MN15 operate as a two-stage source follower circuit. Power supply circuit 22K then generates power supply voltage VDD1. Therefore, as with comparison unit 21J, in comparison unit 21K, interference between multiple analog-to-digital converters (ADCs) can also be suppressed.

[0165] Figure 16 1 and 2. The configuration example of another comparison section 21L according to the present modification is shown. The comparison section 21L includes a power supply circuit 22L and a comparison circuit 23. The power supply circuit 22L includes transistors MN10 and MN15, capacitors C4 and C6, and switches SW3 and SW5.

[0166] The gate of transistor MN10 is connected to one end of capacitor C4 and one end of switch SW3, the drain is connected to power supply line VDDL, and the source is connected to the drain of transistor MN15. One end of capacitor C4 is connected to the gate of transistor MN10 and one end of switch SW3, and the other end is supplied with a DC voltage VREF1. Voltage VREF1 is generated by the imaging control unit 15. Switch SW3 is configured to be turned on and off based on a control signal SHSW1. One end of switch SW3 is connected to the gate of transistor MN10 and one end of capacitor C4, and the other end is supplied with a bias voltage VB1. Control signal SHSW1 and bias voltage VB1 are generated by the imaging control unit 15. For example, switch SW3 is turned on when switch SW1 is on and is turned off when switch SW1 is off.

[0167] The gate of transistor MN15 is connected to one end of capacitor C6 and one end of switch SW5. The drain is connected to the source of transistor MN10. The source is connected to the source of transistor MP11 and the power supply terminal of the subsequent-stage circuit 102. One end of capacitor C6 is connected to the gate of transistor MN15 and one end of switch SW5, and the other end is supplied with a DC voltage VREF2. Voltage VREF2 is generated by the imaging control unit 15. Switch SW5 is configured to be turned on and off based on a control signal SHSW2. One end of switch SW5 is connected to the gate of transistor MN15 and one end of capacitor C6, and the other end is supplied with a bias voltage VB5. The control signal SHSW2 and the bias voltage VB5 are generated by the imaging control unit 15. For example, switch SW5 is turned on when switch SW1 is on and is turned off when switch SW1 is off.

[0168] With this configuration, in comparison section 21L, the current generated by transistor MN11, operating as a constant current source, is applied to transistors MN10 and MN15, and transistors MN10 and MN15 operate as a two-stage source follower circuit. Power supply circuit 22L then generates power supply voltage VDD1. Therefore, as with comparison section 21J, in comparison section 21L, interference between the multiple AD converters ADC can also be suppressed.

[0169] [Variation 6]

[0170] In the above embodiment, if Figure 17 As shown, the back gates of the transistors MN10 and MN11 are supplied with the ground voltage VSS0, and the back gate of the transistor MP11 is supplied with the power supply voltage VDD0, but the present invention is not limited thereto. This modification will be described in detail below with reference to some examples.

[0171] Figure 18 FIG2 shows an example configuration of a comparison unit 21M according to this modification. Comparison unit 21M includes a power supply circuit 22M. In power supply circuit 22M, the back gate of transistor MN10 is connected to the source of transistor MN10. Transistor MN10 is formed in a P-well electrically isolated from a P-type semiconductor substrate by a deep N-well. Therefore, for example, the gate-source voltage Vgs of transistor MN10 can be reduced, thereby further lowering the power supply voltage VDD0 and reducing power consumption.

[0172] Figure 19FIG2 shows another configuration example of a comparison unit 21N according to this modification. Comparison unit 21N includes a comparison circuit 23N. In comparison circuit 23N, the back gate of transistor MP11 is connected to the source of transistor MP11. Therefore, for example, the absolute value of the gate-source voltage Vgs of transistor MP11 can be reduced, thereby further reducing the power supply voltage VDD0 and reducing power consumption. Comparison unit 21N is effective when using a manufacturing process that cannot form a deep N-well.

[0173] Figure 20 FIG2 shows another configuration example of a comparison unit 21P according to this variation. Comparison unit 21P includes a power supply circuit 22M and a comparison circuit 23N. Specifically, the back gate of transistor MN10 is connected to the source of transistor MN10, and the back gate of transistor MP11 is connected to the source of transistor MP11. Therefore, for example, the absolute value of the gate-source voltage Vgs of transistors MN10 and MP11 can be reduced, thereby further reducing the power supply voltage VDD0 and reducing power consumption. Furthermore, in comparison unit 21P, the back gates of transistors MP11 and MN10 are connected to the sources of these transistors, respectively, so that these back gates are driven separately for each AD converter ADC. Consequently, interference between multiple AD converters ADC can be suppressed.

[0174] [Variation 7]

[0175] In addition, the back gates of the transistors MN10 in the power supply circuits of the plurality of AD converters ADC may be connected to each other. Figure 21 The following illustrates an example configuration of a readout unit 20Q in an imaging device 1Q according to this modified example. The readout unit 20Q includes multiple comparison units 21Q and a voltage generator 16Q. Each of the multiple comparison units 21Q includes a power supply circuit 22Q. The back gates of the transistors MN10 in the multiple power supply circuits 22Q are connected to one another. A DC voltage VDC is applied to the back gates of these transistors MN10. The multiple transistors MN10 are formed in a single P-well. The voltage generator 16Q is configured to generate a voltage VDC. The voltage VDC is set to a voltage that causes the PN junction formed by the source of the transistor MN10 and the P-well to become reverse biased.

[0176] Therefore, in the imaging device 1Q, the voltage VDC is supplied to the back gates of the multiple transistors MN10. For example, by appropriately setting the voltage VDC, the absolute value of the gate-source voltage Vgs of the transistor MN10 can be reduced, thereby further lowering the power supply voltage VDD0 and reducing power consumption. Furthermore, in the imaging device 1Q, the multiple transistors MN10 are provided in a single P-well. Therefore, compared to a case where the multiple transistors MN10 are provided in multiple P-wells, for example, the well contact area can be reduced. Consequently, the layout area can be reduced.

[0177] [Variation 8]

[0178] In the above embodiment, the output terminal of the power supply circuit 22 is connected to the comparison circuit 23 in each comparison unit 21 of the multiple AD converters ADC, but this is not limiting. Alternatively, for example, the output terminals of the power supply circuits 22 of two or more AD converters ADC may be connected to each other, and these output terminals may be connected to the comparison circuits 23 of two or more AD converters ADC. This modified example will be described in detail below.

[0179] Figure 22 and Figure 23 An example of the configuration of the readout section 20R in the image pickup device 1R according to this modification is shown. The readout section 20R includes a plurality of AD converters ADC. In this example, the output terminals of the power supply circuits 22 in the two AD converters ADC are connected to each other. Specifically, the output terminal of the power supply circuit 22 of the 0th AD converter ADC[0] and the output terminal of the power supply circuit 22 of the first AD converter ADC[1] are connected to each other. Therefore, the two power supply circuits 22 generate the power supply voltage VDD1. The comparison circuit 23 of the 0th AD converter ADC[0] and the comparison circuit 23 of the first AD converter ADC[1] operate based on the power supply voltage VDD1. In addition, the output terminal of the power supply circuit 22 of the second AD converter ADC[2] and the output terminal of the power supply circuit 22 of the third AD converter ADC[3] are connected to each other. Therefore, the two power supply circuits 22 generate the power supply voltage VDD1. The comparison circuit 23 of the second AD converter ADC[2] and the comparison circuit 23 of the third AD converter ADC[3] operate based on the power supply voltage VDD1. The same applies to the fourth and subsequent AD converters. Therefore, the two power supply circuits 22 generate the power supply voltage VDD1 , and the output impedance of the circuit generating the power supply voltage VDD1 can be reduced compared to the above embodiment, and the circuit noise included in the power supply voltage VDD1 can be reduced to 1 / √2.

[0180] Note that in this example, the output terminals of the power supply circuits 22 in two AD converters ADC are connected to each other, but the present invention is not limited to this. Alternatively, the output terminals of the power supply circuits 22 in three or more AD converters ADC may be connected to each other. For example, if the output terminals of the power supply circuits 22 in N AD converters ADC are connected to each other, the circuit noise contained in the power supply voltage VDD1 can be reduced to 1 / √N.

[0181] In addition, in this example, Figure 23 As shown, the subsequent circuit 102 operates based on the power supply voltage VDD1, but is not limited thereto. Figure 24Like the readout section 20S shown in FIG. 1 , the subsequent circuit 102 can operate based on the power supply voltage VDD0. The readout section 20S includes multiple comparison sections 21S. Each of the comparison sections 21S includes a comparison circuit 23S. The subsequent circuit 102 of the comparison circuit 23S operates based on the power supply voltage VDD0. Therefore, in this modification, the influence of the operation of the subsequent circuit 102 on the power supply voltage VDD1 can be suppressed.

[0182] [Variation 9]

[0183] In the above embodiment, the comparison unit 21 of each of the plurality of AD conversion units ADC includes the power supply circuit 22. However, another power supply circuit may be provided in addition to the power supply circuit 22. This modification will be described in detail below.

[0184] Figure 25 and Figure 26 The following illustrates an example configuration of a readout unit 20T in an imaging device 1T according to this modified example. The readout unit 20T includes multiple A / D converters ADC and multiple power supply circuits 28T. Each of the multiple power supply circuits 28T is configured to generate a power supply voltage VDD0 based on a power supply voltage VDDA supplied via a power supply line VDDL. In this example, the power supply circuit 28T then supplies the generated power supply voltage VDD0 to a comparison unit 21T in two A / D converters ADC. The power supply circuit 28T includes a transistor MN0. Transistor MN0 is an N-type MOS transistor with a gate supplied with a bias voltage VB0, a drain connected to the power supply line VDDL, and a source connected to the two comparison units 21T. The power supply voltage VDDA and the bias voltage VB0 are generated by the imaging control unit 15. The comparison unit 21T includes a power supply circuit 22D and a comparison circuit 23S. The drain of the transistor MN10 in the power supply circuit 22D is connected to the source of the transistor MN0 in the power supply circuit 28T. The power supply circuit 28T and the power supply circuit 22D operate as a two-stage source follower.

[0185] Therefore, by providing two source-follower stages in the readout section 20T, the possibility of noise from the power supply voltage VDD0 generated by the transient current when the comparison section 21T in one AD converter section ADC causes the signal CMPO to transition can be reduced, thereby reducing the possibility of noise from the power supply voltage VDD0 affecting the operation of other AD converter sections ADC. Consequently, interference between multiple AD converter sections ADC can be suppressed. Furthermore, in the readout section 20T, in this example, the power supply circuit 28T supplies the generated power supply voltage VDD0 to the two comparison sections 21T, thereby reducing the number of power supply circuits 28T. Consequently, the circuit area can be reduced.

[0186] Note that in this example, the power supply circuit 28T supplies the generated power supply voltage VDD0 to two comparison sections 21T, but is not limited thereto. Alternatively, the power supply circuit 28T may supply the power supply voltage VDD0 to three or more comparison sections 21T.

[0187] In addition, in this example, Figure 26 As shown, the power supply circuit 28T is constituted by using a transistor MN0, but is not limited thereto. Alternatively, for example, Figure 27 Like the readout unit 20U shown in FIG. , the power supply circuit 28U can be constructed using a transistor MN0 and an operational amplifier OPAO. The non-inverting input terminal of the operational amplifier OPAO is supplied with a bias voltage VB0, the inverting input terminal is connected to the source of the transistor MN0, and the output terminal is connected to the gate of the transistor MN0. Therefore, the power supply circuit 28U can generate a stable power supply voltage VDD0. As a result, in this variation, interference between the multiple analog-to-digital converters (ADCs) can be suppressed.

[0188] [Variation 10]

[0189] Furthermore, a variable resistor may be provided between the output terminals of the power supply circuits of two adjacent AD converters ADC among the plurality of AD converters ADC. This modification will be described in detail below.

[0190] Figure 28 An example of the construction of a readout unit 20V in an image pickup device 1V according to this modification is shown. The readout unit 20V includes a plurality of comparison units 21T, a plurality of transistors 18V, and a voltage generating unit 17V. The transistor 18V is an N-type MOS transistor, and the transistor 18V is provided between the output terminals of the power supply circuit 22D of each two adjacent AD conversion units ADC in a plurality of AD conversion units ADC. The source of the transistor 18V is connected to the output terminal of a certain power supply circuit 22D, the drain is connected to the output terminal of the power supply circuit 22D adjacent to the certain power supply circuit 22D, and the gate is provided with a control voltage Vctrl. The drain-source resistance value in the transistor 18V is changed according to the control voltage Vctrl. That is, the transistor 18V functions as a variable resistor. The voltage generating unit 17V is configured to generate the control voltage Vctrl.

[0191] With this configuration, for example, when the resistance value of the transistor 18V increases, the resistance value between the output terminals of the plurality of power supply circuits 22D increases, and therefore, the readout section 20 ( Figure 5), for example, the possibility of streaks in the captured image can be reduced. As a result, the image quality of the captured image can be improved. In addition, when the resistance value of the transistor 18V is reduced, the resistance value between the output terminals of the plurality of power supply circuits 22D is reduced, and thus, compared with the readout unit 20S ( Figure 24 ), the output impedance can be reduced, and the circuit noise included in the power supply voltage VDD1 can be reduced.

[0192] It should be noted that in this example, the variable resistor is configured by using an N-type MOS transistor, but the present invention is not limited thereto. Alternatively, for example, the variable resistor may be configured by using a P-type MOS transistor.

[0193] In addition, in this example, all of the multiple AD conversion units ADC are connected to each other via transistor 18V, but are not limited to this. As an alternative, for example, the multiple AD conversion units ADC can be divided into multiple groups each including two or more AD conversion units ADC, and the AD conversion units ADC belonging to the same group can be connected to each other via transistor 18V. In addition, multiple AD conversion units ADC of even number can be connected to each other via transistor 18V, and multiple AD conversion units ADC of odd number can be connected to each other via transistor 18V. Specifically, for example, the 0th AD conversion unit ADC[0] and the second AD conversion unit ADC[2] can be connected to each other via transistor 18V (transistor 18V1), and the second AD conversion unit ADC[2] and the fourth AD conversion unit ADC[4] can be connected to each other via transistor 18V (transistor 18V2). Similarly, the first AD conversion unit ADC[1] and the third AD conversion unit ADC[3] can be connected to each other via transistor 18V (transistor 18V3), and the third AD conversion unit ADC[3] and the fifth AD conversion unit ADC[5] can be connected to each other via transistor 18V (transistor 18V4).

[0194] In this example, one voltage generating section 17V is provided and controls the resistance values ​​of all transistors 18V, but the present invention is not limited thereto. Alternatively, for example, a plurality of voltage generating sections may be provided and may control the resistance values ​​of different transistors 18V.

[0195] [Variation 11]

[0196] In addition, if Figure 29As shown in the readout unit 20W, the output terminals of the power supply circuits 22 of two non-adjacent AD converters ADC can be connected to each other. In this example, the nth AD converter ADC[n], the (n+2)th AD converter ADC[n+2], the (n+3)th AD converter ADC[n+3], and the (n+5)th AD converter ADC[n+5] constitute a group (a first group), and the output terminals of the power supply circuits 22 of the multiple AD converters ADC belonging to this first group are connected to each other. In addition, the (n+4)th AD converter ADC[n+4], the (n+6)th AD converter ADC[n+6], the (n+7)th AD converter ADC[n+7], and the (n+9)th AD converter ADC[n+9] constitute another group (a second group), and the output terminals of the power supply circuits 22 of the multiple AD converters ADC belonging to this second group are connected to each other. That is, the power supply circuit 22 of the AD converter ADC[n+4] provided between the AD converter ADC[n+3] and the AD converter ADC[n+5] (their power supply circuits 22 are connected to each other) is not connected to the power supply circuits 22 of the AD converter ADC[n+3] and the AD converter ADC[n+5]. Therefore, for example, even in the case where stripes appear in the captured image, the boundaries of the image can be blurred, so that the stripes can be made less noticeable. Interference is generated between the multiple AD converters ADC belonging to the first group, and similarly, interference is generated between the multiple AD converters ADC belonging to the second group. The degree of interference between the multiple AD converters ADC belonging to the first group is different from the degree of interference between the multiple AD converters ADC belonging to the second group. Therefore, by providing the AD converter ADC belonging to the second group between the multiple AD converters ADC belonging to the first group, the boundaries of the image can be blurred based on the difference in the degree of interference.

[0197] [Variation 12]

[0198] In the above embodiment, if Figure 4A As shown, the comparison circuit 23 includes a single-ended circuit, but is not limited thereto. Alternatively, for example, the comparison circuit may include a differential circuit. The comparison units 31A and 31B according to this modification will be described in detail below.

[0199] Figure 30A FIG2 shows an example configuration of a comparison unit 31A. The comparison unit 31A includes a power supply circuit 22 and a comparison circuit 33A. The comparison circuit 33A includes capacitors C31 to C33, transistors MN31 to MN33, switches SW31 and SW32, and transistors MP31 and MP32. The transistors MN31 to MN33 are N-type MOS transistors, and the transistors MP31 and MP32 are P-type MOS transistors.

[0200] Capacitors C31 and C32 each have one end and another end. Capacitor C31 has one end supplied with a reference signal RAMP, and its other end connected to the other end of capacitor C32, the gate of transistor MN31, and one end of switch SW31. Capacitor C32 has one end supplied with a signal SIG, and its other end connected to the other end of capacitor C31, the gate of transistor MN31, and one end of switch SW31. Capacitor C33 has one end supplied with a DC voltage VREF, and its other end connected to the gate of transistor MN32 and one end of switch SW32.

[0201] The gate of transistor MN31 is connected to the other end of capacitors C31 and C32 and one end of switch SW31. Its drain is connected to the drain of transistor MP31, the gates of transistors MP31 and MP32, and the other end of switch SW31. Its source is connected to the source of transistor MN32 and the drain of transistor MN33. Transistor MN32 has a gate connected to the other end of capacitor C33 and one end of switch SW32. Its drain is connected to the drain of transistor MP32, the other end of switch SW32, and the input terminal of the subsequent-stage circuit 102. Its source is connected to the source of transistor MN31 and the drain of transistor MN33. Transistor MN33 has a gate supplied with bias voltage VB2, a drain connected to the sources of transistors MN31 and MN32, and a source supplied with ground voltage VSS0. Transistor MN33 operates as a current source, and transistors MN31 and MN32 operate as a differential pair.

[0202] Switch SW31 is configured to be turned on and off based on a control signal AZSW. One end of switch SW31 is connected to the other end of capacitors C31 and C32 and the gate of transistor MN31, while the other end is connected to the drains of transistors MN31 and MP31 and the gates of transistors MP31 and MP32. Switch SW32 is configured to be turned on and off based on a control signal AZSW. One end of switch SW32 is connected to the other end of capacitor C33 and the gate of transistor MN32, while the other end is connected to the drains of transistors MN32 and MP32 and the input terminal of the subsequent-stage circuit 102.

[0203] The gate of transistor MP31 is connected to the gate of transistor MP32, the drains of transistors MP31 and MN31, and the other end of switch SW31; the drain is connected to the gates of transistors MP31 and MP32, the drain of transistor MN31, and the other end of switch SW31; the source is connected to the sources of transistors MN10 and MP32, and the power supply terminal of subsequent-stage circuit 102. The gate of transistor MP32 is connected to the gate of transistor MP31, the drains of transistors MP31 and MN31, and the other end of switch SW31; the drain is connected to the input terminal of subsequent-stage circuit 102, the drain of transistor MN32, and the other end of switch SW32; the source is connected to the sources of transistors MN10 and MP31, and the power supply terminal of subsequent-stage circuit 102. Transistors MP31 and MP32 operate as loads for transistors MN31 and MN32, which form a differential pair.

[0204] Here, transistor MN31 corresponds to a specific example of a "first transistor" in the present disclosure. Transistor MN32 corresponds to a specific example of a "fifth transistor" in the present disclosure. Capacitor C33 corresponds to a specific example of a "third capacitor" in the present disclosure. Switch SW32 corresponds to a specific example of a "third switch" in the present disclosure. Transistors MP31 and MP32 correspond to specific examples of a "load circuit" in the present disclosure. Transistor MN33 corresponds to a specific example of a "first current source" in the present disclosure.

[0205] Figure 30B FIG3 shows an example configuration of a comparison unit 31B. Comparison unit 31B includes power supply circuit 22A and comparison circuit 33B. Comparison circuit 33B includes capacitors C41 to C43, transistors MP1 to MP43, switches SW41 and SW42, and transistors MN41 and MN42. Transistors MP41 to MP43 are P-type MOS transistors, while transistors MN41 and MN42 are N-type MOS transistors. Capacitors C41 to C43 of comparison unit 31B correspond to capacitors C31 to C33 of comparison unit 31A, respectively. Transistors MP41 to MP43 of comparison unit 31B correspond to transistors MN31 to MN33 of comparison unit 31A, respectively. Switches SW41 and SW42 of comparison unit 31B correspond to switches SW31 and SW32 of comparison unit 31A, respectively. Transistors MN41 and MN42 of comparison unit 31B correspond to transistors MP31 and MP32 of comparison unit 31A, respectively.

[0206] [Variation 13]

[0207] In the above embodiment, for example, Figure 4AAs shown, the comparison circuit 23 combines the voltage of the signal SIG and the voltage of the reference signal RAMP using capacitors C1 and C2 and performs a comparison operation based on the combined voltage, but is not limited thereto.

[0208] Figure 31A FIG2 shows an example configuration of a comparison unit 51A. Comparison unit 51A includes power supply circuit 22 and comparison circuit 53A. Comparison circuit 53A includes capacitors C51 and C52. One end of capacitor C51 is supplied with reference signal RAMP, and the other end is connected to the gate of transistor MN31 and one end of switch SW31. One end of capacitor C52 is supplied with signal SIG, and the other end is connected to the gate of transistor MN32 and one end of switch SW32. Capacitor C51 corresponds to a specific example of a "first capacitor" in this disclosure. Capacitor C52 corresponds to a specific example of a "second capacitor" in this disclosure.

[0209] Figure 31B FIG2 shows an example configuration of a comparison unit 51B. Comparison unit 51B includes power supply circuit 22A and comparison circuit 53B. Comparison circuit 53B includes capacitors C61 and C62. One end of capacitor C61 is supplied with reference signal RAMP, and the other end is connected to the gate of transistor MP41 and one end of switch SW41. One end of capacitor C62 is supplied with signal SIG, and the other end is connected to the gate of transistor MP42 and one end of switch SW42.

[0210] [Other modifications]

[0211] In addition, two or more of the above-described modifications may be combined.

[0212] <2. Example of use of the imaging device>

[0213] Figure 32 The use example of the imaging device 1 according to the above embodiment is shown. For example, as described below, the imaging device 1 can be used in various situations such as sensing visible light, infrared light, ultraviolet light, and X-rays.

[0214] - Devices that capture images for viewing, such as digital cameras and mobile devices with camera functions

[0215] - Equipment for transportation use, for safe driving such as automatic stopping and recognizing the driver's status, for example, on-board sensors for capturing images of the front, rear, surroundings, and interior of a car; surveillance cameras for monitoring moving vehicles and roads; and distance sensors for measuring the distance between vehicles, etc.

[0216] - Devices used in home appliances such as televisions, refrigerators, and air conditioners to capture images of user gestures and operate the appliances based on the gestures

[0217] - Equipment for healthcare purposes, such as endoscopes and devices that capture images of blood vessels by receiving infrared light

[0218] - Equipment for security purposes, such as surveillance cameras for crime prevention and cameras for personal authentication

[0219] - Equipment for beauty purposes, such as skin measurement equipment that takes images of the skin and microscopes that take images of the scalp

[0220] - Equipment for sports use, such as action cameras and wearable cameras for sports applications, etc.

[0221] - Equipment for agricultural use, such as cameras used to monitor fields and crops

[0222] <3. Application Examples of Mobile Objects>

[0223] The technology according to the present disclosure (the present technology) is applicable to various products. For example, the technology according to the present disclosure can be implemented as a device installed on any of the following types of mobile objects, such as automobiles, electric vehicles, hybrid vehicles, motorcycles, bicycles, personal mobile devices, airplanes, drones, ships, and robots.

[0224] Figure 33 : is a block diagram showing an example of a schematic configuration of a vehicle control system as an example of a mobile body control system to which the technology according to the embodiment of the present disclosure can be applied.

[0225] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. Figure 33 In the illustrated example, a vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an exterior information detection unit 12030, an interior information detection unit 12040, and an integrated control unit 12050. Furthermore, the functional configuration of the integrated control unit 12050 includes a microcomputer 12051, a sound / image output unit 12052, and an in-vehicle network interface (I / F) 12053.

[0226] Drive system control unit 12010 controls the operation of devices related to the vehicle's drive system according to various programs. For example, drive system control unit 12010 functions as a control device for various devices, including a drive force generating device such as an internal combustion engine or a drive motor, which generates the vehicle's drive force; a drive force transmission mechanism for transmitting the drive force to the wheels; a steering mechanism for adjusting the vehicle's steering angle; and a braking device for generating the vehicle's braking force.

[0227] The body system control unit 12020 controls the operation of various devices installed on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for the following devices: a keyless entry system; a smart key system; power windows; or various lights such as headlights, taillights, brake lights, turn signals, and fog lights. In this case, radio waves transmitted from a mobile device that replaces a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals and controls the vehicle's door locks, power windows, lights, and so on.

[0228] The vehicle exterior information detection unit 12030 detects information about the exterior of the vehicle, including the vehicle control system 12000. For example, the vehicle exterior information detection unit 12030 is connected to the camera unit 12031. The vehicle exterior information detection unit 12030 causes the camera unit 12031 to capture an image of the exterior of the vehicle and receives the captured image. Based on the received image, the vehicle exterior information detection unit 12030 can perform object detection or distance detection on objects such as pedestrians, vehicles, obstacles, signs, or letters on the road surface.

[0229] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output this electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 can be visible light or non-visible light such as infrared light.

[0230] The in-vehicle information detection unit 12040 detects information about the interior of the vehicle. For example, the in-vehicle information detection unit 12040 is connected to a driver status detection unit 12041 for detecting the driver's condition. For example, the driver status detection unit 12041 includes a camera for capturing the driver's image. Based on the detection information input from the driver status detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's level of fatigue or concentration, or determine whether the driver is dozing off.

[0231] Based on the information outside or inside the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, the microcomputer 12051 can calculate a control target value for the driving force generating device, the steering mechanism, or the braking device, and can output a control command to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control to implement advanced driver assistance system (ADAS) functions, such as collision avoidance or impact mitigation, following travel based on following distance, speed maintenance travel, vehicle collision warning, or lane departure warning.

[0232] In addition, the microcomputer 12051 is capable of controlling the driving force generating device, steering mechanism, or braking device, etc. based on the information outside or inside the vehicle obtained by the outside information detection unit 12030 or the inside information detection unit 12040, thereby performing collaborative control aimed at achieving autonomous driving that enables the vehicle to drive independently without relying on the driver's operation.

[0233] Furthermore, based on information outside the vehicle acquired by the vehicle exterior information detection unit 12030, the microcomputer 12051 can output a control command to the body system control unit 12020. For example, the microcomputer 12051 can control the headlights and switch the high beam to the low beam based on the position of the preceding vehicle or oncoming vehicle detected by the vehicle exterior information detection unit 12030, thereby performing cooperative control to prevent glare.

[0234] The sound / image output unit 12052 transmits an output signal of at least one of sound and image to an output device, which can visually or auditorily notify information to passengers on the vehicle or outside the vehicle. Figure 33 In the example of FIG, as output devices, an audio speaker 12061, a display portion 12062, and an instrument panel 12063 are shown. The display portion 12062 may include, for example, at least one of an on-board display and a head-up display.

[0235] Figure 34 This is a diagram showing an example of the installation position of the camera unit 12031.

[0236] exist Figure 34 , the camera unit 12031 includes camera units 12101 , 12102 , 12103 , 12104 and 12105 .

[0237] Camera units 12101, 12102, 12103, 12104, and 12105 are, for example, located at the front nose, rearview mirror, rear bumper, and rear door of vehicle 12100, as well as at the upper portion of the windshield inside the vehicle. Camera unit 12101 located at the front nose and camera unit 12105 located at the upper portion of the windshield inside the vehicle primarily capture images in front of vehicle 12100. Camera units 12102 and 12103 located at the rearview mirror primarily capture images from the side of vehicle 12100. Camera unit 12104 located at the rear bumper or rear door primarily captures images from the rear of vehicle 12100. Camera unit 12105 located at the upper portion of the windshield inside the vehicle primarily detects vehicles ahead, pedestrians, obstacles, traffic lights, traffic signs, lanes, and the like.

[0238] By the way, Figure 34 Examples of the imaging ranges of imaging units 12101 to 12104 are shown. Imaging range 12111 represents the imaging range of imaging unit 12101, located on the front nose. Imaging ranges 12112 and 12113 represent the imaging ranges of imaging units 12102 and 12103, respectively, located on the rearview mirrors. Imaging range 12114 represents the imaging range of imaging unit 12104, located on the rear bumper or rear door. For example, by superimposing the image data captured by imaging units 12101 to 12104, a bird's-eye view of vehicle 12100 as seen from above is obtained.

[0239] At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0240] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can determine the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby identifying the following three-dimensional object as the preceding vehicle: specifically, the object that is closest to the vehicle 12100 on the road and is traveling in substantially the same direction as the vehicle 12100 at a predetermined speed (e.g., greater than or equal to 0 km / h). Furthermore, the microcomputer 12051 can pre-set a following distance to be maintained ahead of the preceding vehicle and can execute automatic braking control (including follow-up stop control) or automatic acceleration control (including follow-up start control). This allows for cooperative control, such as automated driving, that enables the vehicle to travel autonomously without relying on driver input.

[0241] For example, based on the distance information obtained from the imaging units 12101-12104, the microcomputer 12051 can classify 3D object data regarding three-dimensional objects into 3D object data for two-wheeled vehicles, standard vehicles, large vehicles, pedestrians, utility poles, and other 3D objects, extract the classified 3D object data, and use the extracted 3D object data to automatically avoid obstacles. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as those visible to the driver of the vehicle 12100 and those difficult to see. The microcomputer 12051 then determines a collision risk, indicating the risk of collision with each obstacle. If the collision risk is equal to or higher than a set value, indicating a potential collision, the microcomputer 12051 outputs a warning to the driver via the audio speaker 12061 or display unit 12062, and the drive system control unit 12010 executes forced deceleration or evasive steering. Thus, the microcomputer 12051 can assist in driving to avoid collisions.

[0242] At least one of the imaging units 12101-12104 may be an infrared camera for detecting infrared rays. For example, the microcomputer 12051 can identify a pedestrian by determining whether the pedestrian exists in the images captured by the imaging units 12101-12104. For example, this pedestrian identification is performed by extracting feature points from the images captured by the imaging units 12101-12104, which are infrared cameras; and performing pattern matching on a series of feature points representing the object's outline to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian exists in the images captured by the imaging units 12101-12104 and identifies the pedestrian, the audio / video output unit 12052 controls the display unit 12062 to superimpose and display a rectangular outline on the identified pedestrian for emphasis. The audio / video output unit 12052 may also control the display unit 12062 to display an icon representing the pedestrian at a desired location.

[0243] An example of a vehicle control system to which the technology of the present disclosure can be applied has been described above. The technology of the present disclosure can be applied to the camera unit 12031 of the aforementioned components. Consequently, the image quality of images captured by the vehicle control system 12000 can be improved. This enables the vehicle control system 12000 to improve the accuracy of collision avoidance or impact mitigation, following driving based on following distance, speed maintenance driving, vehicle collision warnings, and lane departure warnings.

[0244] <4. Application Examples of Distance Measuring Devices>

[0245] Next, an example in which the present technology is applied to a distance measuring device will be described in detail.

[0246] Figure 35 The present invention shows an example of a distance measuring device 900 according to this application example. The distance measuring device 900 is configured to measure the distance to the measurement object OBJ by an indirect method. The distance measuring device 900 includes a light emitting unit 901, an optical system 902, a light detecting unit 910, and a control unit 903.

[0247] Light emitting unit 901 is configured to emit light pulses L0 toward object OBJ. Based on instructions from control unit 903, light emitting unit 901 emits light pulses L0 by performing a light-emitting operation that alternately repeats emitting light and not emitting light. Light emitting unit 901 includes, for example, a light source that emits infrared light. The light source is configured using, for example, a laser light source or an LED (light emitting diode).

[0248] The optical system 902 includes a lens that forms an image on the light receiving surface S of the light detecting section 910. A light pulse (reflected light pulse L1) emitted from the light emitting section 901 and reflected on the measuring object OBJ enters the optical system 902.

[0249] The light detection unit 910 is configured to generate a distance image PIC by detecting light based on an instruction from the control unit 903. The multiple pixel values ​​included in the distance image PIC each represent a value related to the distance D to the measurement object OBJ. The light detection unit 910 then outputs the generated distance image PIC as an image signal DATA.

[0250] The control section 903 is configured to supply control signals to the light emitting section 901 and the light detecting section 910 , and control operations of the light emitting section 901 and the light detecting section 910 , thereby controlling operations of the distance measuring device 900 .

[0251] Figure 36 : An example of the structure of the light detection unit 910 is shown. The light detection unit 910 includes a pixel array 911, a driving unit 912, a reference signal generating unit 913, a readout unit 919, a signal processing unit 914, and an imaging control unit 915. For example, the pixel array 911, the driving unit 912, the reference signal generating unit 913, the readout unit 919, the signal processing unit 914, and the imaging control unit 915 can be formed in one semiconductor substrate. Alternatively, the pixel array 911 can be formed in one semiconductor substrate, and the driving unit 912, the reference signal generating unit 913, the readout unit 919, the signal processing unit 914, and the imaging control unit 915 can be formed in another semiconductor substrate. The two semiconductor substrates can be stacked on top of each other.

[0252] The pixel array 911 includes a plurality of pixels 920 arranged in a matrix. Each of the pixels 920 is configured to generate a pixel voltage Vpix corresponding to the amount of light received.

[0253] Figure 37 1 shows a configuration example of the pixel 920. The pixel array 911 includes a plurality of control lines 931A, a plurality of control lines 931B, a plurality of control lines 932A, a plurality of control lines 932B, a plurality of control lines 933, a plurality of signal lines 939A, and a plurality of signal lines 939B.

[0254] Pixel 920 includes a photodiode 921, floating diffusions 923A and 923B, and transistors 922A, 922B, 924A, 924B, 925A, 925B, 926A, and 926B. The circuit including the photodiode 921, floating diffusion 923A, and transistors 922A, 924A, 925A, and 926A is also referred to as a tap A. Furthermore, the circuit including the photodiode 921, floating diffusion 923B, and transistors 922B, 924B, 925B, and 926B is also referred to as a tap B.

[0255] In tap A, transistor 922A has a gate connected to control line 931A, a source connected to photodiode 921, and a drain connected to floating diffusion 923A. Floating diffusion 923A is configured to accumulate charge supplied from photodiode 921 via transistor 922A. Transistor 924A has a gate connected to control line 932A, a drain supplied with power supply voltage VDD, and a source connected to floating diffusion 923A. Transistor 925A has a gate connected to floating diffusion 923A, a drain supplied with power supply voltage VDD, and a source connected to the drain of transistor 926A. Transistor 926A has a gate connected to control line 933, a drain connected to the source of transistor 925A, and a source connected to signal line 939A. While the above description uses tap A as an example, the same applies to tap B.

[0256] With this configuration, in each pixel 920, transistor 924A turns on to reset floating diffusion 923A, and transistor 924B turns on to reset floating diffusion 923B. Then, one of transistors 922A and 922B turns on alternately to selectively accumulate charge generated by photodiode 921 in floating diffusion 923A and floating diffusion 923B. Then, transistors 926A and 926B turn on to cause pixel 920 to output a pixel signal corresponding to the amount of charge accumulated in floating diffusion 923A to signal line 939A, and to output a pixel signal corresponding to the amount of charge accumulated in floating diffusion 923B to signal line 939B.

[0257] Drive unit 912 ( Figure 36) is configured to sequentially drive the plurality of pixels 920 in the pixel array 911 in units of pixel lines L based on an instruction from the imaging control section 915. The reference signal generating section 913 is configured to generate a reference signal RAMP based on an instruction from the imaging control section 915. The readout section 919 is configured to generate an image signal DATA0 by performing AD conversion based on pixel signals supplied from the pixel array 911 via signal lines 939A and 939B based on an instruction from the imaging control section 915. The signal processing section 914 is configured to generate a distance image PIC by performing predetermined signal processing on the image signal DATA0 based on an instruction from the imaging control section 915, and output an image signal DATA including the distance image PIC. The imaging control section 915 is configured to supply control signals to the driving section 912, the reference signal generating section 913, the readout section 919, and the signal processing section 914, and to control the operations of these circuits, thereby controlling the operation of the light detection section 910.

[0258] Figure 38 An operation example of the distance measuring device 900 is shown. Figure 38 (A) shows the waveform of the light pulse L0 emitted from the light emitting unit 901. Figure 38 (B) shows the waveform of the reflected light pulse L1 detected by the light detection unit 910 .

[0259] The light emitting unit 901 emits a light pulse L0 ( Figure 38 (A)). The light pulse L0 travels toward the object OBJ. Then, the light pulse L0 is reflected on the object OBJ, and the reflected light pulse L1 travels toward the light detection unit 910. Then, the pixel 920 of the light detection unit 910 detects the reflected light pulse L1 ( Figure 38 (B)). The waveform of the reflected light pulse L1 detected by pixel 920 is relative to Figure 38 The waveform of light pulse L0 shown in (A) is delayed by delay time DL. Delay time DL is the time it takes for light to travel through light emitting unit 901, object OBJ, and light detecting unit 910 in this order, and corresponds to the light's flight time. The light's flight time corresponds to the distance between distance measuring device 900 and object OBJ.

[0260] In the indirect method, the floating diffusion 923A of the pixel 920 accumulates signal charge Q1 corresponding to the amount of light received by the photodiode 921 during period 941 when the light-emitting unit 901 emits light. The floating diffusion 923B of the pixel 920 accumulates signal charge Q2 corresponding to the amount of light received by the photodiode 921 during period 942 when the light-emitting unit 901 does not emit light. The signal processing unit 914 then determines the charge ratio between signal charge Q1 and signal charge Q2. The photodiode 921 detects light during periods 951 and 952. Therefore, the charge amount of signal charge Q1 is proportional to the length of period 951, and the charge amount of signal charge Q2 is proportional to the length of period 952. When the delay time DL is short, the signal charge Q1 increases and the signal charge Q2 decreases. When the delay time DL is long, the signal charge Q1 decreases and the signal charge Q2 increases. Therefore, the charge ratio between signal charge Q1 and signal charge Q2 changes depending on the delay time DL. In the indirect method, for example, by determining the charge ratio, the delay time DL can be determined with high accuracy. As a result, the distance to the measurement object OBJ can be measured with high accuracy. This technology is applied to the readout unit 919. Therefore, the image quality of the distance image can be improved.

[0261] An example of the distance measuring device 900 to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to the above-described distance measuring device 900. Therefore, in the distance measuring device 900, the image quality of the distance image can be improved.

[0262] Although the present technology has been described above with reference to some embodiments, modifications, and specific application examples, the present technology is not limited to these embodiments and the like, and the present technology can be modified in various ways.

[0263] For example, in the above embodiment, the pixel P is as follows Figure 2 The configuration shown is, but not limited to, this. Pixels having various configurations can be used.

[0264] It should be noted that the effects described herein are merely illustrative and not restrictive, and other effects may be provided.

[0265] It should be noted that the present technology can have the following configurations. According to the present technology having the following configurations, image quality can be improved. (1)

[0267] A light detection device, comprising:

[0268] a first pixel configured to generate a first pixel signal;

[0269] a reference signal generating section configured to generate a reference signal; and

[0270] A first comparing unit includes a first power supply circuit and a first comparing circuit, wherein the first power supply circuit is configured to generate a first power supply voltage based on a power supply voltage and a bias voltage provided from a first power supply node and output the first power supply voltage from an output terminal, and the first comparing circuit is configured to operate based on the first power supply voltage and perform a comparing operation based on the first pixel signal and the reference signal. (2)

[0272] The light detection device according to (1), wherein the first comparison circuit includes a first current source connected to the second power supply node. (3)

[0274] The light detection device according to (2), wherein

[0275] The first pixel is configured to output the first pixel signal from an output terminal,

[0276] The reference signal generating section is configured to output the reference signal from an output terminal, and

[0277] The first comparison circuit includes:

[0278] a first transistor having a gate, a drain, and a source;

[0279] a first capacitor having a first terminal connected to the output terminal of the reference signal generating section and a second terminal connected to the gate of the first transistor,

[0280] a second capacitor having a first terminal connected to the output terminal of the first pixel and a second terminal connected to the gate of the first transistor; and

[0281] A first switch connects the gate of the first transistor and the drain of the first transistor to each other by turning on the first switch. (4)

[0283] The light detection device according to (3), wherein

[0284] The source of the first transistor is connected to the output terminal of the first power supply circuit, and

[0285] The drain of the first transistor is connected to the first current source. (5)

[0287] The light detection device according to (4), wherein

[0288] The first comparison circuit further includes:

[0289] a second transistor having a gate connected to the drain of the first transistor, a drain, and a source;

[0290] a third transistor having a gate, a drain connected to the drain of the second transistor, and a source connected to the second power supply node; and

[0291] a second switch that connects the gate of the third transistor and the drain of the third transistor to each other by turning on the second switch. (6)

[0293] The light detection device according to (5), wherein the first comparison unit further includes a fourth transistor having a gate connected to the drain of the second transistor, a drain connected to the output terminal of the first power supply circuit, and a source connected to the drain of the first transistor. (7)

[0295] The light detection device according to (3), wherein

[0296] The source of the first transistor is connected to the first current source, and

[0297] The first comparison circuit includes:

[0298] a fifth transistor having a gate, a drain, and a source connected to the first current source;

[0299] a third capacitor connected to the gate of the fifth transistor;

[0300] a third switch to connect the gate of the fifth transistor and the drain of the fifth transistor to each other by turning on the third switch; and

[0301] A load circuit is connected to the output terminal of the first power supply circuit, the drain of the first transistor, and the drain of the fifth transistor. (8)

[0303] The light detection device according to (2), wherein

[0304] The first pixel is configured to output the first pixel signal from an output terminal,

[0305] The reference signal generating section is configured to output the reference signal from an output terminal, and

[0306] The first comparison circuit includes:

[0307] a first transistor having a gate, a drain, and a source connected to the first current source;

[0308] a fifth transistor having a gate, a drain, and a source connected to the first current source;

[0309] a first capacitor having a first terminal connected to the output terminal of the reference signal generating section and a second terminal connected to the gate of the first transistor,

[0310] a second capacitor having a first terminal connected to the output terminal of the first pixel and a second terminal connected to the gate of the fifth transistor;

[0311] a first switch, connecting the gate of the first transistor and the drain of the first transistor to each other by turning on the first switch;

[0312] a third switch to connect the gate of the fifth transistor and the drain of the fifth transistor to each other by turning on the third switch; and

[0313] A load circuit is connected to the output terminal of the first power supply circuit, the drain of the first transistor, and the drain of the fifth transistor. (9)

[0315] The light detection device according to (7) or (8), wherein the load circuit includes:

[0316] a first load transistor having a gate, a drain connected to the drain of the first transistor, and a source connected to the output terminal of the first power supply circuit; and

[0317] a second load transistor having a gate connected to the gate of the first load transistor, a drain connected to the drain of the fifth transistor, and a source connected to the output terminal of the first power supply circuit. (10)

[0319] The light detection device according to (2), wherein

[0320] The first pixel is configured to output the first pixel signal from an output terminal,

[0321] The reference signal generating section is configured to output the reference signal from an output terminal, and

[0322] The first comparison circuit includes:

[0323] a first transistor having a gate, a drain, and a source connected to the output terminal of the first power supply circuit;

[0324] a sixth transistor having a gate, a drain connected to the first current source, and a source connected to the drain of the first transistor;

[0325] a first capacitor having a first terminal connected to the output terminal of the reference signal generating section and a second terminal connected to the gate of the first transistor;

[0326] a second capacitor having a first terminal connected to the output terminal of the first pixel and a second terminal connected to the gate of the first transistor; and

[0327] A first switch is configured to connect the gate of the first transistor and the drain of the sixth transistor to each other by turning on the first switch. (11)

[0329] The light detection device according to any one of (3) to (10), wherein

[0330] The bias voltage includes a first bias voltage, and

[0331] The first power supply circuit includes a first power supply transistor having a gate supplied with the first bias voltage, a drain connected to the first power supply node, and a source connected to the source of the first transistor. (12)

[0333] The light detection device according to any one of (3) to (10), wherein

[0334] The bias voltage includes a first bias voltage and a second bias voltage, and

[0335] The first power supply circuit includes:

[0336] a first power supply transistor having a gate supplied with the first bias voltage, a drain connected to the first power supply node, and a source; and

[0337] A second power supply transistor has a gate supplied with the second bias voltage, a drain connected to the source of the first power supply transistor, and a source connected to the source of the first transistor. (13)

[0339] The light detection device according to (11) or (12), wherein the first power supply circuit further includes a fourth switch, and the first bias voltage is supplied to the gate of the first power supply transistor by turning on the fourth switch. (14)

[0341] The light detection device according to (13), wherein the first power supply circuit further includes a fourth capacitor connected to the gate of the first power supply transistor. (15)

[0343] A light detection device according to (11) or (12), wherein the first power supply circuit further includes an operational amplifier, a non-inverting input terminal of the operational amplifier is provided with the first bias voltage, an inverting input terminal is connected to the source of the first power supply transistor, and an output terminal is connected to the gate of the first power supply transistor. (16)

[0345] The light detection device according to (11) or (12), wherein the first power supply transistor further has a back gate connected to the source of the first power supply transistor. (17)

[0347] The light detection device according to (11) or (12), further including a voltage generating section configured to output a predetermined voltage from the output terminal, wherein

[0348] The first power supply transistor further has a back gate connected to the output terminal of the voltage generating section. (18)

[0350] The light detection device according to (12), wherein the first power supply circuit further includes a fifth switch, and the second bias voltage is supplied to the gate of the second power supply transistor by turning on the fifth switch. (19)

[0352] The light detection device according to any one of (3) to (6), wherein the first transistor further has a back gate connected to the source of the first transistor. (20)

[0354] The light detection device according to any one of (2) to (19), wherein the first current source includes a first current source transistor having a gate, a drain, and a source connected to the second power supply node. (twenty one)

[0356] The light detection device according to any one of (2) to (19), wherein

[0357] The first current source comprises:

[0358] a first current source transistor having a gate, a drain, and a source connected to the second power supply node; and

[0359] A second current source transistor has a gate, a drain, and a source connected to the drain of the first current source transistor. (twenty two)

[0361] The light detection device according to (20), wherein the first current source further includes a sixth switch, and a third bias voltage is supplied to the gate of the first current source transistor by turning on the sixth switch. (twenty three)

[0363] The light detection device according to any one of (1) to (22), further comprising:

[0364] a second pixel configured to generate a second pixel signal; and

[0365] a second comparing section including a second power supply circuit and a second comparing circuit, the second power supply circuit being configured to generate a second power supply voltage based on the power supply voltage supplied from the first power supply node and the bias voltage, and output the second power supply voltage from an output terminal, the second comparing circuit being configured to operate based on the second power supply voltage and perform the comparing operation based on the second pixel signal and the reference signal. (twenty four)

[0367] The light detection device according to (23), wherein the output terminal of the second power supply circuit is connected to the output terminal of the first power supply circuit. (25)

[0369] The light detection device according to (24), further comprising:

[0370] a third pixel configured to generate a third pixel signal; and

[0371] a third comparing section including a third power supply circuit and a third comparing circuit, wherein the third power supply circuit is configured to generate a third power supply voltage based on the power supply voltage supplied from the first power supply node and the bias voltage and output the third power supply voltage from an output terminal, and the third comparing circuit is configured to operate based on the third power supply voltage and perform the comparing operation based on the third pixel signal and the reference signal, wherein:

[0372] The output terminal of the third power supply circuit is electrically insulated from the output terminal of the first power supply circuit and is electrically insulated from the output terminal of the second power supply circuit, and

[0373] The third comparing section is provided between the first comparing section and the second comparing section. (26)

[0375] The light detection device according to (23) further includes a variable resistor having a first terminal connected to the output terminal of the first power supply circuit and a second terminal connected to the output terminal of the second power supply circuit. (27)

[0377] The light detection device according to (23) further includes a fourth power supply circuit configured to generate the power supply voltage based on another power supply voltage supplied from a third power supply node and output the power supply voltage to the first power supply node. (28)

[0379] An electronic device, comprising:

[0380] a light detection device; and

[0381] a processing unit that controls the operation of the light detection device,

[0382] The light detection device comprises:

[0383] a first pixel configured to generate a first pixel signal;

[0384] a reference signal generating section configured to generate a reference signal; and

[0385] A first comparing unit includes a first power supply circuit and a first comparing circuit, wherein the first power supply circuit is configured to generate a first power supply voltage based on a power supply voltage and a bias voltage provided from a first power supply node and output the first power supply voltage from an output terminal, and the first comparing circuit is configured to operate based on the first power supply voltage and perform a comparing operation based on the first pixel signal and the reference signal.

[0386] This application claims the benefit of Japanese Priority Patent Application JP 2019-068359 filed in the Japan Patent Office on March 29, 2019, the entire contents of which are incorporated herein by reference.

[0387] Those skilled in the art should understand that various modifications, combinations, sub-combinations and alterations may occur depending on design requirements and other factors, as long as these modifications, combinations, sub-combinations and alterations are within the scope of the appended claims or the equivalents thereof.

Claims

1. A light detection device, comprising: A comparison unit includes a power supply circuit and a comparison circuit, wherein the power supply circuit is configured to generate a first power supply voltage based on a power supply voltage and a bias voltage supplied from a first power supply node and output the first power supply voltage from an output terminal, and the comparison circuit is configured to operate based on the first power supply voltage and perform a comparison operation based on a pixel signal and a reference signal.

2. The light detection device according to claim 1, wherein The comparison circuit includes a first current source connected to a second power supply node.

3. The light detection device according to claim 2, wherein The first current source includes a first current source transistor having a gate, a drain, and a source connected to the second power supply node.

4. The light detection device according to claim 2, wherein The first current source comprises: a first current source transistor having a gate, a drain, and a source connected to the second power supply node; and A second current source transistor has a gate, a drain, and a source connected to the drain of the first current source transistor.

5. The light detection device according to claim 2, wherein The light detection device further includes: a pixel configured to output the pixel signal from an output terminal, a reference signal generating section configured to output the reference signal from an output terminal, Wherein, the comparison circuit includes: a first transistor having a gate, a drain, and a source; a first capacitor having a first terminal connected to the output terminal of the reference signal generating section and a second terminal connected to the gate of the first transistor, a second capacitor having a first terminal connected to the output terminal of the pixel and a second terminal connected to the gate of the first transistor; and A first switch connects the gate of the first transistor and the drain of the first transistor to each other by turning on the first switch. The light detection device according to claim 5 , wherein: The source of the first transistor is connected to the output terminal of the first power supply circuit, and The drain of the first transistor is connected to the first current source.

7. The light detection device according to claim 6, wherein The first comparison circuit further includes: a second transistor having a drain, a source, and a gate connected to the drain of the first transistor; a third transistor having a gate, a drain connected to the drain of the second transistor, and a source connected to the second power supply node; and a second switch that connects the gate of the third transistor and the drain of the third transistor to each other by turning on the second switch.

8. The light detection device according to claim 7, wherein The first comparing section further includes a fourth transistor having a gate connected to the drain of the second transistor, a drain connected to the output terminal of the first power supply circuit, and a source connected to the drain of the first transistor.

9. The light detection device according to claim 5, wherein The source of the first transistor is connected to the first current source, and The first comparison circuit includes: a fifth transistor having a gate, a drain, and a source connected to the first current source; a third capacitor connected to the gate of the fifth transistor; a third switch to connect the gate of the fifth transistor and the drain of the fifth transistor to each other by turning on the third switch; and A load circuit is connected to the output terminal of the first power supply circuit, the drain of the first transistor, and the drain of the fifth transistor.

10. An electronic device comprising: light detection device; and a processing unit that controls the operation of the light detection device, The light detection device is the light detection device according to any one of claims 1 to 9.

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