Three-dimensional memory, manufacturing method of three-dimensional memory and storage system

Abstract

The invention relates to a three-dimensional memory, a manufacturing method of the three-dimensional memory and a memory system.The manufacturing method of the three-dimensional memory comprises the steps that a stacking structure is formed on a substrate, and the stacking structure comprises a plurality of stacking areas and grid line gap areas located between the adjacent stacking areas in the first direction; forming a plurality of channel holes penetrating through the stacking structure in the stacking region and a plurality of virtual channel holes penetrating through the stacking structure in the grid line gap region; and forming a gate line slit penetrating through the stack structure in the gate line slit region to remove the plurality of virtual channel holes and separate the stack structures in the adjacent stack regions, thereby forming a plurality of gate line slits in the gate line slit region in the process of etching to form the channel holes in the stack regions, according to the invention, the problem of insufficient etching of the channel hole close to the grid line gap region caused by the fact that the etching material formed in the grid line gap region is easy to accumulate in the channel hole close to the grid line gap region can be avoided, so that the performance of the finally formed three-dimensional memory is improved.

Description

[0001] This application is for the application date of January 19, 2022, application number

[0002] 202210061913.9, a divisional application of the patent with the invention name of “Three-dimensional memory, manufacturing method of three-dimensional memory and storage system”.

Technical field

[0003] The present invention relates to the field of memory technology, and in particular to a three-dimensional memory, a method for manufacturing a three-dimensional memory, and a storage system. [Background Technology]

[0004] As technology advances, the semiconductor industry continues to explore new production methods to increase the number of memory cells per memory die in memory devices. Among these, 3D NAND memory, with its high storage density and low cost, has become a cutting-edge 3D memory technology with great potential.

[0005] Existing three-dimensional memories typically include multiple memory block regions, with adjacent memory block regions separated by gate line gaps. Multiple channel structures are distributed within each memory block region. However, during the channel hole formation process, the channel holes near the gate line gap regions can be underetched, which in turn affects the performance of the resulting three-dimensional memory. [Summary of the invention]

[0006] The embodiments of the present invention provide a three-dimensional memory and a manufacturing method thereof, and a storage system to improve the problem of insufficient etching of channel holes near gate line gap regions, thereby improving the performance of the ultimately formed three-dimensional memory.

[0007] To solve the above problems, an embodiment of the present invention provides a method for manufacturing a three-dimensional memory, which includes: a method for manufacturing a three-dimensional memory, characterized in that it includes: forming a stacking structure on a substrate, the stacking structure including multiple stacking areas and a gate line gap area located between adjacent stacking areas in a first direction; forming multiple channel holes penetrating the stacking structure in the stacking areas, and multiple virtual channel holes penetrating the stacking structure in the gate line gap area; forming a gate line slit penetrating the stacking structure in the gate line gap area to remove the multiple virtual channel holes and separate the stacking structures in adjacent stacking areas.

[0008] The plurality of channel holes are arranged in a plurality of rows in the first direction, and the plurality of dummy channel holes are arranged in at least one row in the first direction.

[0009] The spacing distance between a row of virtual channel holes and a row of channel holes adjacent thereto in the first direction is equal to the spacing distance between two adjacent rows of channel holes.

[0010] The plurality of channel holes have the same aperture.

[0011] The virtual channel holes and the channel holes have the same aperture, and the spacing distance between any two adjacent channel holes, the spacing distance between any two adjacent virtual channel holes, and the spacing distance between any adjacent channel hole and a virtual channel hole are equal.

[0012] Among them, forming a plurality of channel holes of the stacking structure penetrating the stacking area and a plurality of virtual channel holes of the stacking structure penetrating the gate line gap area specifically includes: providing a mask plate, the mask plate including a first area and a second area distributed along a first direction, the mask plate in the first area having a plurality of first openings, and the mask plate in the second area having a plurality of second openings; etching the stacking structure according to the plurality of first openings to form a plurality of channel holes of the stacking structure penetrating the stacking area, and etching the stacking structure according to the plurality of second openings to form a plurality of virtual channel holes of the stacking structure penetrating the gate line gap area.

[0013] Before forming the gate line slits that penetrate the stacked structure in the gate line gap region, the method further includes: forming a dummy channel structure in the dummy channel hole; and forming a channel structure in the channel hole.

[0014] Among them, forming a virtual channel structure in the virtual channel hole specifically includes: forming a mask layer covering the channel hole and the virtual channel hole on the stacked structure; etching the mask layer located on the gate line gap area to form a third opening, the third opening exposing the virtual channel hole; and forming a virtual channel structure in the virtual channel hole according to the third opening.

[0015] Before forming a mask layer covering the channel hole and the dummy channel hole on the stack structure, the method further includes: forming a protective layer on the inner walls of the channel hole and the dummy channel hole.

[0016] Before forming the channel structure in the channel hole, the method further includes: removing the mask layer on the stacking area to expose the channel hole.

[0017] The gate line slits are formed to penetrate the stacked structure in the gate line slit region, and specifically include: removing the stacked structure and the dummy channel structure in the gate line slit region to form the gate line slits.

[0018] The material of the virtual channel structure is insulating material.

[0019] In order to solve the above problems, an embodiment of the present invention further provides a three-dimensional memory, which includes: a substrate; a stacking structure located on the substrate, the stacking structure including multiple stacking areas and a gate line gap area located between adjacent stacking areas in a first direction; a gate line slit running through the stacking structure in the gate line gap area, the gate line slit separating the stacking structures in adjacent stacking areas, and a plurality of concave-convex structures formed in the bottom surface of the gate line slit; and a plurality of channel structures running through the stacking structure in the stacking area.

[0020] The bottom surface of the gate line slit is partially raised in a direction away from the substrate to form a plurality of concave-convex structures, and the concave-convex structures are bosses.

[0021] Part of the bottom surface of the gate line slit protrudes into the substrate toward the substrate to form a plurality of concave-convex structures on the substrate, and the concave-convex structures are grooves.

[0022] The plurality of channel structures are arranged in multiple rows in the first direction, and the plurality of concave-convex structures are arranged in at least one row in the first direction.

[0023] The spacing distance in the first direction between a row of concave-convex structures adjacent to the stacking area in at least one row of concave-convex structures and a row of channel structures adjacent to the gate line gap area in the multiple rows of channel structures is equal to the spacing distance in the first direction between two adjacent rows of channel structures.

[0024] Wherein, the plurality of channel structures have the same outer diameter.

[0025] The spacing distance between any two adjacent channel structures in the first direction, the spacing distance between any two adjacent platform structures in the first direction, and the spacing distance between any adjacent channel structure and platform structure in the first direction are equal.

[0026] In order to solve the above problems, the present invention further provides a storage system, which includes a controller and any one of the above three-dimensional memories, wherein the controller is coupled to the three-dimensional memory and is used to control the three-dimensional memory to store data.

[0027] The beneficial effects of the present invention are as follows: different from the prior art, the three-dimensional memory and the manufacturing method thereof provided by the present invention form a stacking structure on a substrate, the stacking structure including multiple stacking areas and a gate line gap area located between adjacent stacking areas in a first direction, and form multiple channel holes penetrating the stacking structure in the stacking area, and multiple virtual channel holes penetrating the stacking structure in the gate line gap area, and then form a gate line slit penetrating the stacking structure in the gate line gap area to remove the multiple virtual channel holes and separate the stacking structures in adjacent stacking areas, so that in the process of etching to form channel holes in the stacking area, the etching material (for example, polymer) formed in the gate line gap area can be distributed more evenly, rather than concentrated in the channel holes near the gate line gap area, so as to effectively improve the problem of insufficient etching of the channel holes near the gate line gap area, thereby improving the performance of the finally formed three-dimensional memory.

Brief Description of the Drawings

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0029] Figure 1 is a flow chart of a method for manufacturing a three-dimensional memory provided by an embodiment of the present invention;

[0030] Figure 2 is a schematic diagram of a top view of the structure after step S11 is completed according to an embodiment of the present invention;

[0031] Figure 3 It is along Figure 2 A schematic diagram of a cross-sectional structure taken along line O-O';

[0032] Figure 4 is a schematic diagram of a top view of the structure after step S12 is completed according to an embodiment of the present invention;

[0033] Figure 5 It is along Figure 4 A schematic diagram of a cross-sectional structure taken along line O-O';

[0034] Figure 6 This is a schematic top view of a semiconductor structure obtained after forming a channel hole provided by the prior art;

[0035] Figure 7 This is another schematic top view of a semiconductor structure obtained after forming a channel hole provided by the prior art;

[0036] Figure 8This is another schematic diagram of a top view of the structure after step S12 is completed according to an embodiment of the present invention;

[0037] Figure 9 This is another schematic diagram of a top view of the structure after step S12 is completed according to an embodiment of the present invention;

[0038] Figure 10 1 is a schematic diagram of a top view of the structure of a mask provided by an embodiment of the present invention;

[0039] Figure 11 is another schematic top view of the structure of the mask provided by an embodiment of the present invention;

[0040] Figure 12 is a schematic diagram of the cross-sectional structure after step S12 is completed according to an embodiment of the present invention;

[0041] Figure 13 is a schematic cross-sectional structural diagram after step S141 is completed according to an embodiment of the present invention;

[0042] Figure 14 is a schematic diagram of a cross-sectional structure after step S142 is completed according to an embodiment of the present invention;

[0043] Figure 15 is a schematic cross-sectional structural diagram after step S1431 is completed according to an embodiment of the present invention;

[0044] Figure 16 is a schematic diagram of a cross-sectional structure after step S1432 is completed according to an embodiment of the present invention;

[0045] Figure 17 is a schematic cross-sectional structural diagram after step S15 is completed according to an embodiment of the present invention;

[0046] Figure 18 This is another schematic cross-sectional structure diagram after step S15 is completed according to an embodiment of the present invention;

[0047] Figure 19 is a schematic diagram of the cross-sectional structure after step S13 is completed according to an embodiment of the present invention;

[0048] Figure 20 is a schematic diagram of the cross-sectional structure after step S13 is completed according to an embodiment of the present invention;

[0049] Figure 21 is a schematic diagram of a top view of the structure after step S16 is completed according to an embodiment of the present invention;

[0050] Figure 22 It is along Figure 21 A schematic diagram of a cross-sectional structure taken along line O-O';

[0051] Figure 23It is along Figure 21 Another schematic cross-sectional view of the structure taken along line O-O';

[0052] Figure 24 It is a schematic structural diagram of a memory system provided by an embodiment of the present invention. [Specific implementation method]

[0053] The present invention will be further described in detail below with reference to the accompanying drawings and examples. It is particularly noted that the following examples are intended only to illustrate the present invention and are not intended to limit the scope of the present invention. Similarly, the following examples are only some embodiments of the present invention and are not intended to be exhaustive. All other embodiments obtained by those of ordinary skill in the art without creative effort are intended to fall within the scope of protection of the present invention.

[0054] In addition, directional terms used herein, such as [upper], [lower], [front], [back], [left], [right], [inner], [outer], and [side], refer only to directions in the accompanying drawings. Therefore, the directional terms used are intended to illustrate and facilitate understanding of the present invention and are not intended to limit the present invention. In the various figures, similar structural elements are denoted by the same reference numerals. For clarity, parts in the figures are not drawn to scale. Furthermore, some well-known parts may not be shown in the figures.

[0055] The present invention may be embodied in various forms, some examples of which are described below.

[0056] See also Figure 1 , Figure 1 FIG. 1 is a flow chart of a method for manufacturing a three-dimensional memory provided by an embodiment of the present invention. The specific flow of the method for manufacturing the three-dimensional memory may be as follows:

[0057] Step S11: forming a stack structure on a substrate, the stack structure comprising a plurality of stack regions and a gate line gap region located between adjacent stack regions in a first direction.

[0058] The schematic diagram of the top view structure after step S11 is completed is as follows: Figure 2 As shown, the cross-sectional structure diagram after step S11 is completed is as follows Figure 3 As shown, and Figure 3 Specifically along Figure 2 Schematic diagram of the cross-sectional structure taken along line O-O'.

[0059] The substrate 11 may be made of semiconductor materials such as silicon, germanium, or silicon-on-insulator (SOI). The stacked structure 12 may include multiple layers of gate sacrificial layers 121 and insulating layers 122 alternately stacked in a direction away from the substrate 11 .

[0060] Specifically, the stacked structure 12 may include a first stacking region K1, a gate line gap region GLS, and a second stacking region K2, which are sequentially connected in a first direction Y parallel to the substrate 11. The gate line gap region GLS may be used to form a gate line gap in subsequent process steps, and the gate line gap may be used to separate the stacked structures 12 in two adjacent stacking regions (e.g., the first stacking region K1 and the second stacking region K2). The stacking regions K1 / K2 may be used to form a channel structure in subsequent process steps.

[0061] In some embodiments, the stacked structure 12 may include multiple block regions, each of which may include multiple finger regions. Furthermore, the stacked regions K1 / K2 may refer to block regions or finger regions. That is, the gate line gap regions GLS may refer to gate line gap regions GLS located between adjacent block regions in the first direction Y, or may refer to gate line gap regions GLS located between adjacent finger regions in the first direction Y, or may refer to gate line gap regions GLS located between adjacent finger regions and block regions in the first direction Y.

[0062] In the above-mentioned stacked structure 12, a gate sacrificial layer 121 can be formed between adjacent insulating layers 122. The material of the gate sacrificial layer 121 can be but not limited to silicon nitride, and the material of the insulating layer 122 can be but not limited to silicon oxide, thereby forming a stacked structure of silicon nitride layer / silicon oxide layer. In addition, in subsequent steps, the above-mentioned gate sacrificial layer 121 will be replaced through a replacement process and a conductive material (for example, tungsten) will be filled in the same position to form a gate layer.

[0063] In a three-dimensional memory, the number of layers of the stacking structure 12 determines the number of storage units it contains in the vertical direction (the direction perpendicular to the substrate 21). For example, the number of layers of the stacking structure 12 can be 32 layers, 64 layers, 96 layers, 128 layers, etc., and the more layers the stacking structure 12 has, the higher the integration of the corresponding three-dimensional memory.

[0064] Step S12: forming a plurality of channel holes penetrating the stack structure in the stack region and a plurality of dummy channel holes penetrating the stack structure in the gate line gap region.

[0065] The schematic diagram of the top view structure after step S12 is completed is as follows: Figure 4 As shown, the cross-sectional structure diagram after step S12 is completed is as follows Figure 5 As shown, and Figure 5 Specifically along Figure 4 Schematic diagram of the cross-sectional structure taken along line O-O'.

[0066] Specifically, an anisotropic etching process may be used, for example, a dry etching process (e.g., a plasma etching process, a reactive ion etching process, etc.) to etch the stacked structure 12 in the stacked region K1 / K2 from top to bottom to form a channel hole 13 that penetrates the stacked structure 12 in the stacked region K1 / K2 from top to bottom, and simultaneously etch the stacked structure 12 in the gate line gap region GLS from top to bottom to form a virtual channel hole 14 that penetrates the stacked structure 12 in the gate line gap region GLS from top to bottom. In a specific embodiment, as Figure 5 As shown, the above-mentioned channel hole 13 and the virtual channel hole 14 can penetrate the above-mentioned stacking structure 12 in the direction Z perpendicular to the substrate 11, and extend into the substrate 11 to form openings 11A and openings 11B on the substrate 11 respectively, thereby achieving sufficient etching to ensure that the substrate 11 can be exposed through the channel hole 13 and the virtual channel hole 14, and it is also beneficial to increase the supporting effect of the channel structure formed in the channel hole 13 on the stacking structure 12 in subsequent processes.

[0067] In this embodiment, each channel hole 13 can be completely located within the stacking region K1 / K2, that is, it does not exceed the boundary of the stacking region K1 / K2. Each dummy channel hole 14 can be completely located within the gate line gap region GLS, that is, it does not exceed the boundary of the gate line gap region GLS.

[0068] It is worth noting that the inventors have found that according to a method for manufacturing a three-dimensional memory according to an embodiment, Figure 6 As shown, in the process of etching the stack structure 22 in the stack area K1' / K2' to form the channel hole 23, because the stack structure 22 located in the gate line gap area GLS' for forming the gate line gap in the subsequent process steps will be reserved and will not be etched and patterned, the etching material (for example, polymer) formed in the gate line gap area GLS' during the etching process will mostly enter the channel hole 23 near the gate line gap area GLS', thereby causing the channel hole 23 near the gate line gap area GLS' to be unable to be etched to the corresponding depth, resulting in insufficient etching, which affects the performance of the finally formed three-dimensional memory.

[0069] And, in some embodiments, as Figure 7 As shown, in order to solve the problem of insufficient etching of the channel hole 23 close to the gate line gap region GLS', when designing the channel hole pattern, the size of the channel hole pattern corresponding to the channel hole 23 close to the gate line gap region GLS' can be designed to be larger, that is, the top size of the channel hole 23 close to the gate line gap region GLS' is larger than the top size of the channel hole 23 away from the gate line gap region GLS'.

[0070] However, the inventors have discovered that, although the above-mentioned scheme of designing the size of the channel hole pattern corresponding to the channel hole 23 near the gate line gap region GLS' to be larger can improve the problem of insufficient etching of the channel hole 23 near the gate line gap region GLS', designing the channel hole pattern in this way will result in a large difference in the top size of the channel hole 23 near the gate line gap region GLS' and the top size of the channel hole 23 far from the gate line gap region GLS', which will cause the morphological consistency of the channel hole 23 near the gate line gap region GLS' and the channel hole 23 far from the gate line gap region GLS' to deteriorate, thereby affecting the uniformity of the electrical parameters of the storage cells in the ultimately formed three-dimensional memory.

[0071] It is understandable that if Figure 4 As shown, in the present embodiment, during the process of etching the channel hole 13 in the stacking area K1 / K2, a virtual channel hole 14 is simultaneously etched in the gate line gap area GLS. This not only allows the etching material (e.g., polymer) formed in the gate line gap area GLS during the etching process to be more evenly distributed, rather than being concentrated in the channel hole 13 near the gate line gap area GLS, thereby effectively improving the problem of insufficient etching of the channel hole 13 near the gate line gap area GLS, but also allows the channel hole 13 near the gate line gap area GLS and the channel hole 13 away from the gate line gap area GLS to have the same size, thereby also improving the morphology consistency of the channel hole 13 near the gate line gap area GLS and the channel hole 13 away from the gate line gap area GLS, thereby improving the uniformity of electrical parameters of storage cells in the three-dimensional memory.

[0072] Specifically, if Figure 4 As shown, the plurality of channel holes 13 may have the same aperture, and the plurality of dummy channel holes 14 may have the same aperture. For example, the plurality of channel holes 13 may have the same shape and size, and the plurality of dummy channel holes 14 may have the same shape and size.

[0073] In this embodiment, the same aperture, the same shape and the same size may respectively refer to at least the same surface aperture, the same surface shape and the same surface size, for example, the surface aperture at one end away from the substrate 11 is the same, the surface shape at one end away from the substrate 11 is the same and the surface size at one end away from the substrate 11 is the same.

[0074] In some embodiments, the diameter, shape, and / or size of the channel hole 13 may not vary from top to bottom, that is, the diameter, shape, and / or size of the channel hole 13 may be the same from top to bottom. In other embodiments, the diameter, shape, and / or size of the virtual channel hole 14 may not vary from top to bottom.

[0075] In some other embodiments, the aperture, shape, and / or size of the channel hole 13 and the virtual channel hole 14 may change from top to bottom. For example, the aperture, shape, and / or size of the channel hole 13 and the virtual channel hole 14 may gradually decrease from top to bottom. Furthermore, the aperture, shape, and size of the plurality of channel holes 13 being the same may specifically refer to the aperture, shape, and size of the tops of the plurality of channel holes 13 being the same, and the aperture, shape, and size of the plurality of virtual channel holes 14 being the same may specifically refer to the aperture, shape, and size of the tops of the plurality of virtual channel holes 14 being the same.

[0076] Furthermore, the aperture, shape and size of the top of the channel hole 13 and the aperture, shape and size of the top of the dummy channel hole 14 can be adjusted by changing the mask used in the etching process for forming the channel hole 13 and the dummy channel hole 14 .

[0077] In a specific embodiment, Figure 8 As shown, the channel hole 13 and the virtual channel hole 14 may have the same aperture. Specifically, the channel hole 13 and the virtual channel hole 14 may have the same shape and size. For example, the cross-sectional shape of the channel hole 13 and the virtual channel hole 14 may be a circle with the same diameter.

[0078] In a specific embodiment, the plurality of channel holes 13 and the plurality of dummy channel holes 14 may be evenly distributed in the stacking region K1 / K2 and the gate line gap region GLS of the stack structure 12. Specifically, the spacing distance between any two adjacent channel holes 13, the spacing distance between any two adjacent dummy channel holes 14, and the spacing distance between any adjacent channel hole 13 and a dummy channel hole 14 may all be equal.

[0079] In this embodiment, the spacing distance may refer to the center spacing distance or the closest edge spacing distance. The center spacing distance and the closest edge spacing distance may respectively refer to the center spacing distance of the end portion and the closest edge spacing distance of the end portion, and the end portion may be away from the top of the substrate 11.

[0080] Moreover, in a possible embodiment, the above-mentioned channel hole 13 and the virtual channel hole 14 can have the same shape and size, and the distance between the center points of any two adjacent channel holes 13, the distance between the center points of any two adjacent virtual channel holes 14, and the distance between the center points of any adjacent channel hole 13 and a virtual channel hole 14 can all be equal.

[0081] Correspondingly, the channel holes 13 located in the above-mentioned stacking area K1 / K2 and the virtual channel holes 14 located in the above-mentioned gate line gap area GLS can be arranged in a manner that shares a common arrangement pattern, so that the channel holes 13 located in the stacking area K1 / K2 and the virtual channel holes 14 located in the gate line gap area GLS have the same characteristics (for example, shape, size and spacing distance between the center points of adjacent virtual channel holes 14 and / or channel holes 13) except for their different distribution positions.

[0082] In this way, in the process of etching to form the channel hole 13 in the stacking area K1 / K2, it is ensured that the etching material formed in the stacking area K1 / K2 and the gate line gap area GLS can be evenly distributed, thereby completely eliminating the difference in the etching material entering each channel hole 13, and can completely solve the problem of insufficient etching of the channel hole 13 close to the gate line gap area GLS, and make the channel hole 13 close to the gate line gap area GLS and the channel hole 13 away from the gate line gap area GLS completely consistent in morphology, thereby improving the consistency of the electrical parameters of each storage unit in the three-dimensional memory.

[0083] In other embodiments, Figure 4 As shown, the plurality of channel holes 13 may be arranged in multiple rows in a first direction Y parallel to the substrate 11, that is, the plurality of channel holes 13 may include multiple rows of channel holes. The plurality of dummy channel holes 14 may be arranged in at least one row in the first direction Y, that is, the plurality of dummy channel holes 14 may include at least one row of dummy channel holes.

[0084] The spacing distance between a row of dummy channel holes and a row of channel holes adjacent thereto in the first direction Y may be equal to the spacing distance between two adjacent rows of channel holes. For example, the spacing distance between a row of dummy channel holes in the at least one row of dummy channel holes closest to the stacking region K1 / K2 and a row of channel holes in the adjacent multiple rows of channel holes closest to the gate line gap region GLS is equal to the spacing distance between two adjacent rows of channel holes.

[0085] In this embodiment, the spacing distance between two adjacent rows of channel holes can be specifically the spacing distance between the tops of the two adjacent rows of channel holes. The spacing distance between an adjacent row of virtual channel holes and a row of channel holes can be specifically the spacing distance between the tops of an adjacent row of virtual channel holes and a row of channel holes. The spacing distance between two adjacent rows of virtual channel holes can be specifically the spacing distance between the tops of the two adjacent rows of virtual channel holes.

[0086] In some specific embodiments, the plurality of channel holes 13 may have the same shape and size, and the plurality of rows of channel holes and the at least one row of dummy channel holes may be distributed in the first direction Y at equal intervals.

[0087] In a specific application scenario, such as Figure 8 As shown, the channel holes 13 and the dummy channel holes 14 may have the same shape and size, and the multiple rows of channel holes and the at least one row of dummy channel holes may be equally spaced in the first direction Y. That is, the channel holes 13 and the dummy channel holes 14 have the same shape and size, and the spacing distance between any two adjacent rows of channel holes in the first direction Y, the spacing distance between any two adjacent rows of dummy channel holes in the first direction Y, and the spacing distance between any adjacent row of channel holes and row of dummy channel holes in the first direction Y may all be equal.

[0088] Specifically, the width W1 of the gate line gap region GLS in the first direction Y can satisfy the condition that the multiple rows of channel holes and the at least one row of virtual channel holes are evenly spaced in the first direction Y, that is, not less than (m1*D1+(m1-1)*D2) and not greater than (m1*D1+(m1+1)*D2), wherein m1 is a positive integer greater than 0, D1 is the width of a row of channel holes in the first direction Y, and D2 is the spacing distance between two adjacent rows of channel holes 13.

[0089] It can be understood that in the application scenario where the above-mentioned multiple rows of channel holes and the above-mentioned at least one row of virtual channel holes are equally spaced in the first direction Y, when the width W1 of a gate line gap area GLS in the first direction Y satisfies not less than (m1*D1+(m1-1)*D2) and not greater than (m1*D 1+(m1+1)*D2), m1 rows of virtual channel holes can be set on the corresponding gate line gap area GLS.

[0090] Taking m1 equal to 2, that is, the width of the gate line gap area GLS in the first direction Y is not less than (2*D1+D2) and not greater than (2*D1+3*D2) as an example, in the application scenario where the above-mentioned multiple rows of channel holes and at least one row of virtual channel holes are equally spaced in the first direction Y, exactly two rows of virtual channel holes can be set on the gate line gap area GLS.

[0091] In another specific application scenario, such as Figure 4As shown, the plurality of channel holes 13 may have the same shape and size, and the plurality of rows of channel holes may be evenly spaced in the first direction Y. The plurality of virtual channel holes 14 may have the same shape and size, and the at least one row of virtual channel holes may be evenly spaced in the first direction Y. That is, the plurality of channel holes 13 may have the same shape and size, the plurality of virtual channel holes 14 may have the same shape and size, and the spacing distance between any two adjacent rows of channel holes in the first direction Y may be equal. Furthermore, when the plurality of virtual channel holes 14 include at least two rows of virtual channel holes, the spacing distance between any two adjacent rows of virtual channel holes in the first direction Y may also be equal.

[0092] Moreover, the width W2 of the gate line gap region GLS in the first direction Y may not satisfy the condition that the multiple rows of channel holes and the at least one row of dummy channel holes are evenly spaced in the first direction Y, that is, it may be less than ((m1+1)*D1+m1*D2) and greater than (m1*D 1+(m1+1)*D2), and the corresponding channel holes 13 located on the stacking area K1 / K2 and the dummy channel holes 14 located on the gate line gap region GLS may be arranged in different arrangement patterns.

[0093] It can be understood that in the application scenario where the above-mentioned multiple rows of channel holes and the above-mentioned at least one row of virtual channel holes are unequally spaced in the first direction Y, when the width W1 of a gate line gap area GLS in the first direction Y satisfies the requirement of being less than ((m1+1)*D 1+m1*D2) and greater than (m1*D 1+(m1+1)*D2), m1 rows of virtual channel holes can be set on the corresponding gate line gap area GLS, that is, the above-mentioned multiple virtual channel holes 14 can include m1 rows of virtual channel holes to ensure that the boundaries of the above-mentioned multiple virtual channel holes 14 do not exceed the boundaries of the gate line slit area GLS.

[0094] Taking m1 equal to 1, that is, the width of the gate line gap area GLS in the first direction Y is less than (2*D1+D2) and greater than (D1+2*D2) as an example, in an application scenario where the above-mentioned multiple channel holes 13 and the above-mentioned multiple virtual channel holes 14 are unevenly distributed on the stacking area K1 / K2 of the substrate 11 and the gate line gap area GLS, a row of virtual channel holes can be set on the gate line gap area GLS.

[0095] In some specific embodiments, in order to minimize the difference in etching material entering the channel holes 13 close to the gate line gap region GLS and the channel holes 13 far away from the gate line gap region GLS during the process of etching the channel holes 13 in the stacking area K1 / K2 when the width of the gate line gap region GLS in the first direction Y does not satisfy the condition for making the multiple rows of channel holes and the at least one row of virtual channel holes equally spaced in the first direction Y, so as to improve the problem of insufficient etching of the channel holes 13 close to the gate line gap region GLS, it can be arranged that: the spacing distance between a row of virtual channel holes among the at least one row of virtual channel holes closest to the stacking area K1 / K2 and a row of channel holes among the multiple rows of channel holes adjacent thereto that is closest to the gate line gap region GLS is equal to the spacing distance between two adjacent rows of channel holes.

[0096] Furthermore, when the plurality of virtual channel holes 14 include multiple rows of virtual channel holes, the spacing distance between any two adjacent rows of virtual channel holes in the first direction Y and the spacing distance between any two adjacent rows of channel holes in the first direction Y may be equal. Thus, the multiple rows of channel holes and the at least one row of virtual channel holes can be evenly spaced in the first direction Y, and further, the plurality of channel holes 13 and the plurality of virtual channel holes 14 can be distributed as close to uniformly as possible. Therefore, in the process of etching to form the channel hole 13 in the stacking area K1 / K2, the etched materials formed in the stacking area K1 / K2 and the gate line gap area GLS can be distributed as close to uniformly as possible, thereby eliminating the difference in the etched materials entering each channel hole 13 as much as possible, so as to effectively improve the problem of insufficient etching of the channel hole 13 close to the gate line gap area GLS, and make the channel hole 13 close to the gate line gap area GLS and the channel hole 13 away from the gate line gap area GLS as completely consistent in morphology as possible, so as to improve the consistency of the electrical parameters of each storage unit in the three-dimensional memory.

[0097] In some embodiments, as Figure 9As shown, the cross-sectional area of ​​the virtual channel holes 14 may be greater than the cross-sectional area of ​​the channel holes 13. Specifically, in an application scenario where the multiple rows of channel holes and the at least one row of virtual channel holes are unequally spaced in the first direction Y, when the width W1 of a gate line gap region GLS in the first direction Y satisfies the condition of being less than ((m1+1)*D1+m1*D2) and greater than (m1*D1+(m1+1)*D2), if m1 rows of virtual channel holes are evenly spaced in the gate line gap region GLS, and the shape and size of the virtual channel holes 14 are the same as those of the channel holes 13, then the spacing distance between the row of virtual channel holes in the m1 row that is closest to the stacking area K1 / K2 and the row of channel holes in the adjacent multiple rows of channel holes that is closest to the stacking area K1 / K2 will inevitably be greater than the spacing distance between two adjacent rows of channel holes. Therefore, the size of the virtual channel holes 14 in the first direction Y can be adaptively increased relative to the channel holes 13, so that the spacing distance between any two adjacent rows of channel holes in the first direction Y, the spacing distance between any two adjacent rows of virtual channel holes in the first direction Y, and the spacing distance between any adjacent row of channel holes and row of virtual channel holes in the first direction Y can be equal, thereby enabling the above-mentioned multiple channel holes 13 and the above-mentioned multiple virtual channel holes 14 to be as close to uniformly distributed as possible on the stacking area K1 / K2 and the gate line gap area GLS of the substrate 11.

[0098] Furthermore, in a specific implementation, it can be configured that the maximum width of the virtual channel hole 14 in the first direction Y is greater than the maximum width in the second direction X perpendicular to the first direction Y. Accordingly, the cross-sectional shape of the virtual channel hole 14 can be a geometric shape with major and minor axes, such as an ellipse. Specifically, the maximum width of the virtual channel hole 14 in the second direction X can also be equal to the maximum width of the channel hole 13 in the second direction X.

[0099] In the above embodiment, the above step S12 may specifically include:

[0100] Step S121 : providing a mask, wherein the mask includes a first region and a second region distributed along a first direction, the mask in the first region has a plurality of first openings, and the mask in the second region has a plurality of second openings.

[0101] Step S122 : etching the stack structure according to the plurality of first openings to form a plurality of channel holes penetrating the stack structure in the stack region, and etching the stack structure according to the plurality of second openings to form a plurality of dummy channel holes penetrating the stack structure in the gate line gap region.

[0102] In this embodiment, if Figure 10As shown, the first region 30A of the mask 30 may correspond one-to-one with the stacking region K1 / K1 of the substrate 11, and the second region 30B may correspond one-to-one with the gate line slit region GLS of the substrate 11. The first opening 301 in the first region 30A may correspond one-to-one with the channel hole 13, and the second opening 302 in the second region 30B may correspond one-to-one with the dummy channel hole 14.

[0103] Specifically, if Figure 10 As shown, the plurality of first openings 301 may be arranged in multiple rows in the first direction Y, and the plurality of second openings 302 may be arranged in at least one row in the first direction Y. Thus, the plurality of channel holes 13 formed by etching the stack structure 12 through the plurality of first openings 301 may be arranged in multiple rows in the first direction Y, and the plurality of dummy channel holes 14 formed by etching the stack structure 12 through the plurality of second openings 302 may be arranged in at least one row in the first direction Y.

[0104] In some embodiments, as Figure 10 As shown, the multiple first openings 301 may have the same shape and size to ensure that the channel holes 13 formed by etching the stacked structure 12 through the first openings 301 have the same shape and size, thereby ensuring uniformity of electrical parameters of the memory cells in the three-dimensional memory.

[0105] In a specific embodiment, Figure 11 As shown, the spacing distance between the row of second openings closest to the first region 30A in the at least one row of second openings and the row of channel holes closest to the second region 30B in the adjacent multiple rows of first openings can be equal to the spacing distance between two adjacent rows of first openings. Specifically, the spacing distance between any two adjacent rows of first openings in the first direction Y, the spacing distance between any two adjacent rows of second openings in the first direction Y, and the spacing distance between any adjacent rows of first openings and rows of second openings in the first direction Y can all be equal, so that the multiple rows of channel holes formed by etching the stack structure 12 through the first openings 301 and the at least one row of dummy channel holes formed by etching the stack structure 12 through the second openings 302 can be evenly spaced along the first direction Y on the stack region K1 / K2 and the gate line gap region GLS. As a result, the multiple channel holes 13 and the multiple dummy channel holes 14 can be distributed as close to uniformly as possible on the stack region K1 / K2 and the gate line gap region GLS of the substrate 11.

[0106] In some embodiments, as Figure 11As shown, the cross-sectional area of ​​the second opening 302 can be larger than the cross-sectional area of ​​the first opening 301, so that the cross-sectional area of ​​the virtual channel hole 14 formed by etching the stack structure 12 through the second opening 302 can be larger than the cross-sectional area of ​​the channel hole 13 formed by etching the stack structure 12 through the first opening 301.

[0107] Specifically, the maximum width of the second openings 302 in the first direction Y may be greater than the maximum width in the direction X perpendicular to the first direction Y. Furthermore, the spacing distance between any two adjacent rows of first openings in the first direction Y, the spacing distance between any two adjacent rows of second openings in the first direction Y, and the spacing distance between any adjacent rows of first openings and second openings in the first direction Y may all be equal.

[0108] Furthermore, in a specific implementation, the maximum width of the second opening 302 in the first direction Y may be greater than the maximum width in the direction X perpendicular to the first direction Y. Accordingly, the second opening 302 may be a geometric shape with major and minor axes, such as an ellipse. Specifically, the maximum width of the second opening 302 in the direction X may be equal to the maximum width of the first opening 301 in the direction X.

[0109] It can be understood that the number, shape, size and arrangement of the first area 30A, the second area 30B, the first opening 301 and the second opening 302 on the above-mentioned mask 30 can be the same as the number, shape, size and arrangement of the corresponding stacking areas K1 / K1, the gate line gap area GLS, the channel hole 13 and the virtual channel hole 14, so they are not repeated here.

[0110] In the above embodiment, in order to increase the number of layers of the stacking structure 12 to increase the storage density of the three-dimensional memory without increasing the difficulty of the etching process for forming the above-mentioned channel holes 13 and virtual channel holes 14, the above-mentioned stacking structure 12 may include a plurality of stacking structures stacked in a direction Z away from the substrate 11, and correspondingly, the channel holes 13 and virtual channel holes 14 passing through the above-mentioned stacking structure 12 can be formed by multiple etchings.

[0111] And, for ease of understanding and explanation, as Figure 12As shown, this embodiment is described by taking the stacking structure 12 as an example, in which the stacking structure 12 includes a first stacking structure 12A and a second stacking structure 12B stacked in a direction Z away from the substrate 11. Accordingly, the above-mentioned step S12 may specifically include: forming a first channel hole 13A located on the stacking area K1 / K2 and passing through the first stacking structure 12A, and a first virtual channel hole 14A located on the gate line gap area GLS and passing through the first stacking structure 12A; forming a sacrificial material layer in the first channel hole 13A and the first virtual channel hole 14A; forming a second stacking structure 12B on the first stacking structure 12A and the sacrificial material layer; forming a first channel hole 13A located on the stacking area K1 / K2 and passing through the first stacking structure 12A; forming a first channel hole 14A located on the gate line gap area GLS and passing through the first stacking structure 12A; forming a first channel hole 13A and a first virtual channel hole 14A; forming a second channel hole 12B on the first stacking structure 12A and the sacrificial material layer; forming a first channel hole 13A located on the stacking area K1 / K2 and a second channel hole 13B that passes through the second stack structure 12B, and a second virtual channel hole 14B that is located on the gate line gap area GLS and passes through the second stack structure 12B, wherein the second channel hole 13B exposes the sacrificial material layer located in the first channel hole 13A, and the second virtual channel hole 14B exposes the sacrificial material layer located in the first virtual channel hole 14A; the sacrificial material layer is removed through the second channel hole 13B and the second virtual channel hole 14B to obtain a channel hole 13 composed of the connected first channel hole 13A and the second channel hole 13B, and a virtual channel hole 14 composed of the connected first virtual channel hole 14A and the second virtual channel hole 14B.

[0112] Specifically, the first stack structure 12A and the second stack structure 12B in the stack structure 12 may each include multiple layers of the gate sacrificial layer 121 and the gate insulating layer 122 alternately stacked in the longitudinal direction Z away from the substrate 11. Furthermore, the number of layers in the second stack structure 12A may be the same as or different from the number of layers in the first stack structure 12A.

[0113] The first channel hole 13A and the first dummy channel hole 14A can be formed by etching the first stack structure 12A from top to bottom in the stacking region K1 / K2 and the gate line gap region GLS, respectively. The first channel hole 13A and the first dummy channel hole 14A penetrate the first stack structure 12A and can extend into the interior of the substrate 11 in a longitudinal direction Z perpendicular to the substrate 11. The second channel hole 13B and the second dummy channel hole 14B can be formed by etching the second stack structure 12B from top to bottom in the stacking region K1 / K2 and the gate line gap region GLS, respectively. The second channel hole 13B and the second virtual channel hole 14B penetrate the second stack structure 12B in the longitudinal direction Z perpendicular to the substrate 11 and reach the upper surface of the first stack structure 12A, and the bottom of the second channel hole 13B can expose the top surface of the sacrificial material layer in the first channel hole 13A, and the bottom of the second virtual channel hole 14B can expose the top surface of the sacrificial material layer in the first virtual channel hole 14A.

[0114] The sacrificial material layer can be formed by depositing a sacrificial material in the first channel hole 13A and the first dummy channel hole 14A using a chemical vapor deposition process, and removing the sacrificial material outside the first channel hole 13A and the first dummy channel hole 14A using chemical mechanical planarization. The sacrificial material can be any one of polysilicon, carbon, and tungsten.

[0115] Accordingly, the above-mentioned channel hole 13 may include a first channel hole 13A and a second channel hole 13B that are connected to each other, and the above-mentioned virtual channel hole 14 may include a first virtual channel hole 14A and a second virtual channel hole 14B that are connected to each other, and after forming the above-mentioned second channel hole 13B and the second virtual channel hole 14B, a selective etchant may be used to selectively remove the above-mentioned sacrificial material layer through the second channel hole 13B and the second virtual channel hole 14B.

[0116] Step S13 : forming a gate line slit penetrating the stack structure in the gate line gap region to remove a plurality of dummy channel holes and separate the stack structures in adjacent stack regions.

[0117] Before the above step S13, the following steps may also be included:

[0118] Step S14: forming a dummy channel structure in the dummy channel hole.

[0119] Specifically, the above step S14 may include:

[0120] Step S141 : forming a mask layer covering the channel holes and the dummy channel holes on the stacked structure.

[0121] The cross-sectional structure diagram after step S141 is completed is as follows: Figure 13 shown.

[0122] The material of the mask layer 15 may include insulating materials such as silicon oxide.

[0123] Step S142 : etching the mask layer on the gate line gap region to form a third opening, wherein the third opening exposes the dummy channel hole.

[0124] The cross-sectional structure diagram after step S142 is completed is as follows: Figure 14 shown.

[0125] Specifically, the third opening 152 may be formed by etching away the mask layer 15 located on the gate line gap region GLS.

[0126] Step S143: forming a dummy channel structure in the dummy channel hole according to the third opening.

[0127] The above step S143 may specifically include:

[0128] Step S1431 : forming a dummy channel structure in the third opening and the dummy channel hole.

[0129] The cross-sectional structure diagram after step S1431 is completed is as follows: Figure 15 shown.

[0130] The dummy channel structure 16 may include insulating materials such as silicon oxide.

[0131] Step S1432: aligning the dummy channel structure with the stacked structure.

[0132] The cross-sectional structure diagram after step S1432 is completed is as follows: Figure 16 shown.

[0133] Specifically, chemical mechanical polishing or wet etching can be performed to align the dummy channel structure 16 with the stacked structure 12. Figure 16 As shown, the uppermost gate sacrificial layer 121 in the stack structure 12 can be used as a grinding stop layer to grind the surface of the stack structure 12 facing away from the substrate 11 (i.e., the top surface of the stack structure 12) to expose the top surface of the uppermost gate sacrificial layer 121 in the stack structure 12, and to re-expose the surface of the substrate 13 at the bottom of the channel hole 13.

[0134] It can be understood that in the process of aligning the virtual channel structure 16 with the stack structure 13, the mask layer 15 located on the stack area K1 / K2 will be removed, so that the channel hole 13 covered by the mask layer 15 in the previous process step is exposed again, thereby facilitating the formation of a channel structure in the channel hole 13 in the subsequent process step.

[0135] Step S15: forming a channel structure in the channel hole.

[0136] The cross-sectional structure diagram after step S15 is completed is as follows: Figure 17 shown.

[0137] The channel structure 17 may include a storage function layer and a channel layer sequentially disposed on the sidewalls of the channel hole 13. Specifically, the storage function layer may include a first oxide layer as a charge blocking layer, a nitride layer as a charge trapping layer, and a second oxide layer as a tunneling layer sequentially disposed on the sidewalls of the channel hole 13. The first oxide layer, the nitride layer, the second oxide layer, and the channel layer may be made of silicon oxide, silicon nitride, silicon oxide, and polysilicon, respectively.

[0138] In some specific embodiments, Figure 18As shown, before forming the dummy channel structure 16 in the dummy channel hole 14, a protective layer 20 may be formed on the inner walls of the channel hole 13 and the dummy channel hole 14. Specifically, the inner walls of the channel hole 13 and the dummy channel hole 14 may be oxidized to form an oxide serving as the protective layer 20. The protective layer 20 can protect the inner walls of the channel hole 13 and the dummy channel hole 14 from being damaged in subsequent process steps.

[0139] In other specific embodiments, Figure 18 As shown, before forming the dummy channel structure 16 in the dummy channel hole 14, an epitaxial layer 21 may be further formed at the bottom of the channel hole 13 and the dummy channel hole 14. Accordingly, the dummy channel structure 16 may be located on the epitaxial layer 21 at the bottom of the dummy channel hole 14, and the channel structure 17 may be located on the epitaxial layer 21 at the bottom of the channel hole 13.

[0140] Moreover, in a specific embodiment, after the above-mentioned channel hole 13 and the virtual channel hole 14 are formed, the above-mentioned epitaxial layer 21 can be formed at the bottom of the channel hole 13 and the virtual channel hole 14, and then the above-mentioned protective layer 20 is formed on the inner wall of the channel hole 13 and the virtual channel hole 14 with the epitaxial layer 21 formed at the bottom, and then the above-mentioned channel structure 17 and the virtual channel structure 16 are formed in the remaining space of the channel hole 13 and the virtual channel hole 14 respectively.

[0141] In a possible embodiment, when the epitaxial layer 21 is not formed at the bottom of the dummy channel hole 14 in the previous process step, the cross-sectional structural diagram after the completion of the step S13 may be as follows: Figure 19 As shown, the above step S13 may specifically include: removing the stacked structure 12 , the dummy channel structure 16 and the protection layer 20 (if any) located on the gate line gap region GLS to form a gate line slit 18 .

[0142] Specifically, the bottom surface of the gate line slit 18 may partially protrude into the substrate 11 toward the substrate 11, so as to form a plurality of grooves 18A on the substrate 11. Furthermore, it is understood that the grooves 18A may correspond one-to-one to the dummy channel holes 14 located in the gate line gap region GLS, and the grooves 18A may specifically be the bottom ends of the corresponding dummy channel holes 14, or may be formed by further extending into the interior of the substrate 11 along the direction toward the substrate 11 during the etching process of the corresponding dummy channel holes 14 to form the gate line slits 18.

[0143] In another possible embodiment, when the epitaxial layer 21 is formed at the bottom of the dummy channel hole 14 in the preceding process step, the cross-sectional structural diagram after the completion of the step S13 may be as follows: Figure 20As shown, the above step S13 may specifically include: removing the stacked structure 12 , the dummy channel structure 16 , the protection layer 20 (if any) and at least a portion of the epitaxial layer 21 in the gate line gap region GLS to form a gate line slit 18 .

[0144] Specifically, the bottom surface of the gate line slit 18 may partially protrude in a direction away from the substrate 11 to form a plurality of bosses 18B. Furthermore, it is understood that the bosses 18B may correspond one-to-one to the dummy channel holes 14 located in the gate line slit region GLS, and the bosses 18B may be formed during the etching process to form the gate line slit 18 because the reaction rate between the epitaxial layer 21 directly below the dummy channel structure 16 in the gate line slit region GLS and the etchant is lower than the reaction rate between the stacked structure 12 and the dummy channel structure 16 and the etchant, resulting in the substrate 11 directly below the dummy channel structure 16 reacting with the etchant later and being less consumed by the etchant.

[0145] In the above embodiment, after the above step S13, the following steps may also be included:

[0146] Step S16: forming a gate line gap structure in the gate line slit.

[0147] The schematic diagram of the top view structure after step S16 is completed is as follows: Figure 21 As shown, the cross-sectional structure diagram after step S16 is completed is as follows Figure 22 or Figure 23 As shown, and Figure 22 and Figure 23 Can be specifically along Figure 21 Schematic diagram of the cross-sectional structure taken along line O-O'.

[0148] Specifically, the gate line gap structure 19 can be formed by filling the gate line gap 18 with an insulating material (e.g., an insulating material with a high dielectric constant, such as silicon oxide, silicon nitride, or silicon oxynitride). In some alternative embodiments, the gate line gap 18 can be filled with a spacer layer (e.g., an oxide layer) serving as an insulating layer and a conductive material (e.g., titanium or titanium nitride, polysilicon, and / or metal tungsten) serving as a common source to obtain a gate line gap structure 19 having a common source.

[0149] In some embodiments, before forming the gate line slit structure 19 in the gate line slit 18 , the process may further include replacing the gate sacrificial layer 121 in the stacked structure 12 with a gate layer through the gate line slit 18 .

[0150] Specifically, the gate sacrificial layer 121 of the stacked structure 12 may be replaced by a replacement process, and a conductive material (eg, tungsten) may be filled in the same position to form the gate layer of the stacked structure 12 .

[0151] Different from the prior art, the manufacturing method of the three-dimensional memory in this embodiment forms a stacking structure on a substrate, where the stacking structure includes multiple stacking regions and a gate line gap region located between adjacent stacking regions in a first direction. Then, multiple channel holes are formed through the stacking structure in the stacking region, and multiple virtual channel holes are formed through the stacking structure in the gate line gap region. Then, a gate line slit is formed through the stacking structure in the gate line gap region to remove the multiple virtual channel holes and separate the stacking structures in adjacent stacking regions. In this way, during the process of etching to form channel holes in the stacking region, the etching material (for example, a polymer) formed in the gate line gap region can be distributed more evenly, rather than being concentrated in the channel holes near the gate line gap region, so as to effectively improve the problem of insufficient etching of the channel holes near the gate line gap region, thereby improving the performance of the finally formed three-dimensional memory.

[0152] The three-dimensional memory manufactured according to the above method embodiment of the present invention is as follows Figure 21 、 Figure 22 and Figure 23 As shown, the three-dimensional memory may include: a substrate 11; a stacking structure 12 located on the substrate 11, the stacking structure 12 including a plurality of stacking regions K1 / K2 and a gate line gap region GLS located between adjacent stacking regions K1 / K2 (for example, the first stacking region K1 and the second stacking region K2) in a first direction Y; a gate line slit 18 passing through the stacking structure 12 in the gate line gap region GLS, the gate line slit 18 separating the stacking structures 12 in adjacent stacking regions K1 / K2, and a plurality of concave-convex structures formed in the bottom surface of the gate line slit GLS; and a plurality of channel structures 17 passing through the stacking structure 12 in the stacking region K1 / K2.

[0153] In one embodiment, Figure 22 As shown, the bottom surface of the gate line slit 18 may partially protrude into the substrate 11 toward the substrate 11 to form a plurality of grooves 18A on the substrate 11 , thereby obtaining a plurality of concave-convex structures of the grooves 18A.

[0154] In another embodiment, Figure 23 As shown, the bottom surface of the gate line slit 18 may be partially raised in a direction away from the substrate 11 to form a plurality of bosses 18B, thereby obtaining a plurality of concave-convex structures of the bosses 18B.

[0155] In one embodiment, the plurality of channel structures 17 may be arranged in a plurality of rows in the first direction Y, and the plurality of concave-convex structures may be arranged in at least one row in the first direction Y.

[0156] Specifically, the spacing distance in the first direction Y between a row of concave-convex structures adjacent to the stacking area K1 / K2 in the at least one row of concave-convex structures and a row of channel structures adjacent to the gate line gap area GLS in the multiple rows of channel structures 17 can be equal to the spacing distance in the first direction Y between two adjacent rows of channel structures.

[0157] The spacing distance between adjacent rows of concave-convex structures and a row of channel structures in the first direction Y may specifically be the spacing distance between the bottoms of adjacent rows of concave-convex structures and a row of channel structures in the first direction Y.

[0158] In this embodiment, the spacing distance may refer to the center spacing distance or the closest edge spacing distance. The center spacing distance and the closest edge spacing distance may respectively refer to the center spacing distance of the end portion and the closest edge spacing distance of the end portion, and the end portion may be away from the top of the substrate 11.

[0159] In some embodiments, the cross-sectional area of ​​the concavo-convex structure may be greater than the cross-sectional area of ​​the channel structure 17. The cross-sectional area of ​​the concavo-convex structure and the cross-sectional area of ​​the channel structure 17 may be specifically the cross-sectional area of ​​the top of the concavo-convex structure and the cross-sectional area of ​​the top of the channel structure 17, respectively.

[0160] Specifically, the maximum width of the concave-convex structure in the first direction Y may be greater than the maximum width of the concave-convex structure in the direction X perpendicular to the first direction Y.

[0161] In some embodiments, the plurality of channel structures 17 may have the same outer diameter. Specifically, the cross-sections of the plurality of channel structures 17 may have the same shape and size. The outer diameter and cross-section of the channel structure 17 may specifically be the outer diameter and cross-section of the top of the channel structure 17.

[0162] In this embodiment, the same outer diameter, the same cross-sectional shape and the same cross-sectional size may respectively refer to at least the same surface outer diameter, the same surface shape and the same surface size, for example, the surface outer diameter at the end away from the above-mentioned substrate 11 is the same, the surface shape at the end away from the above-mentioned substrate 11 is the same and the surface size at the end away from the above-mentioned substrate 11 is the same.

[0163] In some embodiments, the outer diameter, cross-sectional shape, and / or cross-sectional size of the channel structure 17 may not vary from top to bottom, that is, the outer diameter, cross-sectional shape, and / or cross-sectional size of the channel structure 17 may be the same from top to bottom. In other embodiments, the outer diameter (or inner diameter), cross-sectional shape, and / or cross-sectional size of the concave-convex structure may not vary from top to bottom.

[0164] In some embodiments, the spacing distance between any two adjacent channel structures 17 in the first direction Y, the spacing distance between any two adjacent platform structures in the first direction Y, and the spacing distance between any adjacent channel structure 17 and a platform structure in the first direction Y can all be equal. The spacing distance can specifically refer to the center spacing distance of the top portion or the nearest edge spacing distance of the top portion.

[0165] Furthermore, the cross section of the channel structure 17 and the cross section of the boss structure may have the same shape and size.

[0166] In a specific embodiment, the distance between the center points of the orthographic projections of any two adjacent channel structures 17 on the substrate 11, the distance between the center points of the orthographic projections of any two adjacent platform structures on the substrate 11, and the distance between the center points of the orthographic projections of any adjacent channel structure 17 and a platform structure on the substrate 11 can all be equal.

[0167] In some embodiments, the three-dimensional memory may further include a gate line gap structure 19 located in the gate line slit 18 .

[0168] It should be noted that the various structures of the three-dimensional memory in this embodiment can refer to the specific implementation methods described in the above method embodiments, so they will not be described again here.

[0169] The three-dimensional memory provided in this embodiment forms virtual channel holes in the gate line gap region while etching the channel holes in the stacked region. This allows the etched material (e.g., polymer) formed in the gate line gap region during the etching process to be more evenly distributed rather than concentrated in the channel holes near the gate line gap region. This effectively alleviates the problem of insufficient etching of the channel holes near the gate line gap region, thereby improving the performance of the ultimately formed three-dimensional memory.

[0170] Accordingly, if Figure 24 As shown, an embodiment of the present invention further provides a storage system 40 , which includes a controller 41 and a three-dimensional memory 42 . The controller 41 is coupled to the three-dimensional memory 42 and is used to control the three-dimensional memory 42 to store data.

[0171] The three-dimensional memory 42 can be the same as the three-dimensional memory described in any of the above embodiments, and therefore will not be described in detail here. The controller 41 can control the three-dimensional memory 42 via a channel CH, and the three-dimensional memory 42 can perform operations under the control of the controller 41 in response to requests from the host 50. The three-dimensional memory 42 can receive a command CMD and an address ADDR from the controller 41 via the channel CH and access an area selected from the memory cell array in response to the address. In other words, the three-dimensional memory 42 can perform internal operations corresponding to the command on the area selected by the address.

[0172] In some embodiments, the storage system 40 may be implemented as a storage device such as a universal flash storage (UFS) device, a solid state drive (SSD), a multimedia card in the form of MMC, eMMC, RS-MMC and micro MMC, a secure digital card in the form of SD, mini SD and micro SD, a Personal Computer Memory Card International Association (PCMCIA) card type storage device, a peripheral component interconnect (PCI) type storage device, a PCI-Express (PCI-E) type storage device, a compact flash (CF) card, a smart media card or a memory stick, etc.

[0173] The storage system provided in this embodiment forms virtual channel holes in the gate line gap region while etching the channel holes in the stacked region. This allows the etching material (e.g., polymer) formed in the gate line gap region during the etching process to be more evenly distributed rather than concentrated in the channel holes near the gate line gap region, thereby effectively alleviating the problem of insufficient etching of the channel holes near the gate line gap region and thereby improving the performance of the ultimately formed three-dimensional memory.

[0174] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention shall be included within the scope of protection of the present invention. The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention shall be included within the scope of protection of the present invention.

Claims

1. A three-dimensional memory, characterized in that: include: substrate; A plurality of stacked structures are located on the substrate, and the plurality of stacked structures are arranged along a first direction; a gate line gap structure, located between two adjacent stacked structures in the first direction, wherein a bottom surface of the gate line gap structure partially protrudes into the substrate toward the substrate to form a plurality of grooves on the substrate; as well as a plurality of channel structures, wherein the plurality of channel structures penetrate the stack structure; The dimension of the end portion of the groove away from the bottom surface of the gate line gap structure along the first direction is substantially the same as the dimension of the end portion of the channel structure close to the substrate along the first direction.

2. The three-dimensional memory according to claim 1, wherein: A plurality of the channel structures are arranged along a second direction to form a row of channel structures, and a plurality of the grooves are arranged along the second direction to form a row of grooves, and the second direction intersects with the first direction.

3. The three-dimensional memory according to claim 2, wherein: In the first direction, the plurality of channel structures are arranged in multiple rows, and the plurality of grooves include at least one row of grooves.

4. The three-dimensional memory according to claim 3, wherein: A spacing distance in the first direction between a row of grooves in the at least one row of grooves adjacent to the plurality of channel structures and a row of channel structures in the multiple rows of channel structures adjacent to the row of grooves is equal to a spacing distance in the first direction between two adjacent rows of channel structures.

5. The three-dimensional memory according to claim 1, wherein: The plurality of channel structures have the same outer diameter.

6. The three-dimensional memory according to claim 3, wherein: The spacing distance between two adjacent channel structures in two adjacent rows of channel structures in the first direction is equal to the spacing distance between any adjacent channel structure and one groove in the first direction.

7. The three-dimensional memory according to claim 3, wherein: In the first direction, the multiple grooves are arranged in multiple rows, and the spacing distance in the first direction between two adjacent channel structures in two adjacent rows of channel structures, the spacing distance in the first direction between two adjacent grooves in two adjacent rows of grooves, and the spacing distance in the first direction between any adjacent channel structure and one groove are equal.

8. The three-dimensional memory according to claim 1, wherein: The gate line gap structure includes a spacer layer, the spacer layer includes an insulating material, and the spacer layer is located between two adjacent stack structures in the first direction.

9. The three-dimensional memory according to claim 8, characterized in that The gate line gap structure further includes a conductive material. In the first direction, the spacer layer is located between the conductive material and the stacked structure.

10. A three-dimensional memory, characterized in that: include: substrate; A plurality of stacked structures are located on the substrate, and the plurality of stacked structures are arranged along a first direction; a gate line gap structure, located between two adjacent stacked structures in the first direction, wherein a bottom surface of the gate line gap structure is partially raised in a direction away from the substrate to form a plurality of bosses; as well as a plurality of channel structures, wherein the plurality of channel structures penetrate the stack structure; The dimension of the end of the boss away from the bottom surface of the gate line gap structure along the first direction is substantially the same as the dimension of the end of the channel structure close to the substrate along the first direction.

11. The three-dimensional memory according to claim 10, wherein: The plurality of channel structures are arranged along a second direction to form a row of channel structures, and the plurality of bosses are arranged along the second direction to form a row of bosses, and the second direction intersects with the first direction.

12. The three-dimensional memory according to claim 11, wherein: In the first direction, the plurality of channel structures are arranged in multiple rows, and the plurality of bosses include at least one row of bosses.

13. The three-dimensional memory according to claim 12, wherein: The spacing distance in the first direction between a row of bosses in the at least one row of bosses adjacent to the multiple channel structures and a row of channel structures in the multiple rows of channel structures adjacent to the row of bosses is equal to the spacing distance between two adjacent rows of channel structures in the first direction.

14. The three-dimensional memory according to claim 10, wherein: The plurality of channel structures have the same outer diameter.

15. The three-dimensional memory according to claim 12, wherein: The spacing distance between two adjacent channel structures in two adjacent rows of channel structures in the first direction is equal to the spacing distance between any adjacent channel structure and one boss in the first direction.

16. The three-dimensional memory according to claim 12, wherein: In the first direction, the multiple bosses are arranged in multiple rows, and the spacing distance in the first direction between two adjacent channel structures in two adjacent rows of channel structures, the spacing distance in the first direction between two adjacent bosses in two adjacent rows of bosses, and the spacing distance in the first direction between any adjacent channel structure and a boss are equal.

17. The three-dimensional memory according to claim 10, wherein: The gate line gap structure includes a spacer layer, the spacer layer includes an insulating material, and the spacer layer is located between two adjacent stack structures in the first direction.

18. The three-dimensional memory according to claim 17, wherein: The gate line gap structure further includes a conductive material. In the first direction, the spacer layer is located between the conductive material and the stacked structure.

19. A method for manufacturing a three-dimensional memory, characterized in that: include: forming gate sacrificial layers and insulating layers alternately stacked in a plurality of stacking regions and gate line gap regions on a substrate, wherein the gate line gap regions are located between the stacking regions adjacent to each other in a first direction; forming a plurality of channel holes and a plurality of dummy channel holes, wherein the plurality of channel holes penetrate the alternately stacked gate sacrificial layers and insulating layers in the stacking region, and the plurality of dummy channel holes penetrate the alternately stacked gate sacrificial layers and insulating layers in the gate line gap region; and A gate line slit is formed to pass through the alternately stacked gate sacrificial layer and the insulating layer in the gate line gap region to remove the plurality of dummy channel holes.

20. The method for manufacturing a three-dimensional memory according to claim 19, wherein: The plurality of dummy channel holes are formed in the process of forming the plurality of channel holes.

21. The method for manufacturing a three-dimensional memory according to claim 19, wherein: The plurality of channel structures are arranged along a second direction to form a row of channel structures, and the plurality of dummy channel holes are arranged along the second direction to form a row of dummy channel holes, wherein the second direction intersects the first direction; In the first direction, the plurality of channel holes are arranged in multiple rows, and the plurality of virtual channel holes include at least one row of virtual channel holes.

22. The method for manufacturing a three-dimensional memory according to claim 21, wherein: The spacing distance between a row of dummy channel holes and a row of channel holes adjacent thereto in the first direction is equal to the spacing distance between two adjacent rows of channel holes.

23. The method for manufacturing a three-dimensional memory according to claim 19, wherein: The plurality of channel holes have the same pore diameter.

24. The method for manufacturing a three-dimensional memory according to claim 23, wherein: The virtual channel holes and the channel holes have the same aperture, and the spacing distance between any two adjacent channel holes, the spacing distance between any two adjacent virtual channel holes, and the spacing distance between any adjacent channel hole and one virtual channel hole are equal.

25. The method for manufacturing a three-dimensional memory according to claim 19, wherein: The forming of the plurality of channel holes and the plurality of dummy channel holes specifically includes: Providing a mask, the mask comprising a first region and a second region distributed along the first direction, the mask in the first region having a plurality of first openings, and the mask in the second region having a plurality of second openings; The alternately stacked gate sacrificial layer and the insulating layer are etched according to the multiple first openings to form a plurality of channel holes penetrating the alternately stacked gate sacrificial layer and the insulating layer located in the stacking area, and the alternately stacked gate sacrificial layer and the insulating layer are etched according to the multiple second openings to form a plurality of virtual channel holes penetrating the alternately stacked gate sacrificial layer and the insulating layer located in the gate line gap area.

26. The method for manufacturing a three-dimensional memory according to claim 19, wherein: Before forming the gate line slits penetrating the alternately stacked gate sacrificial layers and the insulating layers in the gate line gap region, the method further includes: forming a dummy channel structure in the dummy channel hole; A channel structure is formed in the channel hole.

27. The method for manufacturing a three-dimensional memory according to claim 26, wherein: The forming of a virtual channel structure in the virtual channel hole specifically includes: forming a mask layer covering the channel hole and the dummy channel hole on the alternately stacked gate sacrificial layer and the insulating layer; Etching the mask layer on the gate line gap region to form a third opening, wherein the third opening exposes the dummy channel hole; A dummy channel structure is formed in the dummy channel hole according to the third opening.

28. The method for manufacturing a three-dimensional memory according to claim 27, wherein: Before forming a mask layer covering the channel hole and the dummy channel hole on the alternately stacked gate sacrificial layer and the insulating layer, the method further includes: A protection layer is formed on inner walls of the channel hole and the dummy channel hole.

29. The method for manufacturing a three-dimensional memory according to claim 27, wherein: Before forming the channel structure in the channel hole, the method further includes: The mask layer located on the stacking region is removed to expose the channel hole.

30. The method for manufacturing a three-dimensional memory according to claim 26, wherein: The forming of the gate line slits penetrating the alternately stacked gate sacrificial layers and the insulating layers located in the gate line gap region specifically includes: Parts of the alternately stacked gate sacrificial layer, the insulating layer, and the dummy channel structure located in the gate line gap region are removed to form the gate line slit.

31. The method for manufacturing a three-dimensional memory according to claim 26, wherein: The material of the virtual channel structure is insulating material.

32. The method for manufacturing a three-dimensional memory according to claim 19, wherein: Also includes: The gate sacrificial layer is replaced by a gate layer through the gate line slits to form a stacked structure.

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