Preparation method of stacked transistor, stacked transistor, device and electronic equipment

Abstract

The invention provides a preparation method of a stacked transistor, the stacked transistor, a device and electronic equipment. The method comprises the following steps: forming a front active structure and a back active structure which are stacked in a first direction on a substrate; forming a front first source-drain structure, a front gate structure, a front second source-drain structure and a front gate side wall in the front transistor based on the front active structure; reversing the wafer and thinning the substrate; forming a back first source drain structure, a back gate structure, a back second source drain structure and a back gate side wall in the back transistor based on the back active structure; on the basis of the first grid side wall on the back side, downward self-aligned etching is carried out in the first direction, etching is stopped to the bottom of the front grid structure or the front transistor, and a first groove is formed; depositing a metal material in the first groove to form a first gate contact structure; and under the condition that the etching is stopped to the front gate structure, the first gate contact structure penetrates through the back gate structure and is in contact with the front gate structure.

Description

Technical Field

[0001] The present application relates to the field of semiconductors, and in particular to a method for preparing a stacked transistor, a stacked transistor, a device, and an electronic device. Background Art

[0002] As Moore's Law continues to deepen, further advancing transistor scaling is a hot topic in the industry. Stacked transistors, by integrating two or more layers of transistors vertically, further increase transistor integration density and become a key technology for further scaling integrated circuits.

[0003] The current stacking scheme of vertical field-effect transistors faces challenges such as high process complexity. Its gate interconnection design is not suitable for flipped stacking structure and has strict requirements on lithography precision, which restricts its practical application potential. Summary of the Invention

[0004] The present application provides a method for preparing a stacked transistor, a stacked transistor, a device, and an electronic device, which can simplify the process.

[0005] In a first aspect, an embodiment of the present application provides a method for preparing a stacked transistor, the method comprising: forming an active structure on a substrate; the active structure comprising a front active structure and a back active structure stacked in a first direction; forming a front first source-drain structure, a front gate structure, a front second source-drain structure and a front gate sidewall in the front transistor based on the front active structure; the front gate sidewall comprises a front first gate sidewall extending in a first direction and a front second gate sidewall extending in a second direction; the second direction is perpendicular to the first direction; flipping and thinning the substrate; forming a back first source-drain structure, a back gate structure, a back second source-drain structure and a back gate sidewall in the back transistor based on the back active structure. The front sidewall is provided with a first gate sidewall; the back sidewall includes a first gate sidewall extending in a first direction and a second gate sidewall extending in a second direction; the front transistor and the back transistor are stacked in the first direction; based on the first gate sidewall, self-aligned etching is performed downward along the first direction, and the etching stops at the bottom of the front gate structure or the front transistor to form a first groove; a metal material is deposited in the first groove to form a first gate contact structure; when the etching stops at the front gate structure, the first gate contact structure passes through the back gate structure and contacts the front gate structure; when the etching stops at the bottom of the front transistor, the first gate contact structure passes through the back gate structure and the front gate structure.

[0006] In some possible embodiments, based on the first back gate sidewall, self-aligned etching is performed downward along a first direction, and the etching stops at the bottom of the front gate structure or the front transistor to form a first groove, including: forming a first photoresist plate on the surface of the back transistor away from the front transistor; under the mask action of the first photoresist plate, selectively etching the back transistor and the front transistor along the first direction, and stopping at the bottom of the front gate structure or the front transistor to form a first groove; wherein, the first back gate sidewall is not selectively etched.

[0007] In some possible embodiments, when the first gate contact structure penetrates the back gate structure and contacts the front gate structure; before flipping the wafer and thinning the substrate, the method further includes: based on the front first gate sidewall, self-aligned etching is performed downward along the first direction, and the etching stops at the front gate structure to form a second groove; metal material is deposited in the second groove to form a second gate contact structure; and the second gate contact structure contacts the front gate structure.

[0008] In some possible embodiments, based on the first front gate sidewall, self-aligned etching is performed downward along a first direction, and the etching stops at the front gate structure to form a second groove, including: forming a second photoresist plate on the surface of the front transistor away from the back transistor; under the mask of the second photoresist plate, the front transistor is selectively etched along the first direction, and the etching stops at the front gate structure to form a second groove; wherein the first front gate sidewall is not selectively etched.

[0009] In some possible embodiments, based on the front active structure, a front first source-drain structure, a front gate structure, a front second source-drain structure and a front gate sidewall are formed in the front transistor, including: based on the front active structure, forming a front first source-drain structure at the bottom of the front active structure; depositing insulating material on the first front source-drain structure to form a front bottom isolation layer of a preset height; the front bottom isolation layer wraps the front first source-drain structure; forming a front gate structure on the front bottom isolation layer; the front bottom isolation layer is used to isolate the front gate structure and the front first source-drain structure; depositing insulating material on the front gate structure to form a front top isolation layer of a preset height; forming a front second source-drain structure on the front top isolation layer; the front top isolation layer is used to isolate the front gate structure and the front second source-drain structure; depositing insulating material on the sidewalls of the front gate structure to form a front gate sidewall.

[0010] In some possible embodiments, after forming the first source and drain structure on the front side, the method further includes: depositing semiconductor material on the side of the first source and drain structure on the front side to form a front placeholder structure; wherein the front bottom isolation layer wraps the front placeholder structure; the method further includes: depositing dielectric material on the front bottom isolation layer to form a front interlayer dielectric layer in the front transistor; performing photolithography on the front interlayer dielectric layer, and stopping etching to the front placeholder structure to form a third groove; removing the front placeholder structure to form a fourth groove; and depositing metal material in the third groove and the fourth groove to form the first source and drain metal on the front side.

[0011] In some possible implementations, the front side transistor and the back side transistor are vertical field effect transistors.

[0012] In a second aspect, an embodiment of the present application provides a stacked transistor, which is prepared using the method of the first aspect, and the stacked transistor includes: a front transistor; a back transistor; the front transistor and the back transistor are stacked in a first direction; a first gate contact structure; the first gate structure passes through the back gate structure and contacts the front gate structure; or, the first gate contact structure passes through the back gate structure and the front gate structure.

[0013] In a third aspect, an embodiment of the present application provides a semiconductor device, which includes: a stacked transistor as described in the above embodiment.

[0014] In a fourth aspect, an embodiment of the present application provides an electronic device, which includes: a circuit board and a semiconductor device as described in the above embodiment, wherein the semiconductor device is arranged on the circuit board.

[0015] In the present application, a first gate contact structure that penetrates the back gate structure and contacts the front gate structure, or a first gate contact structure that penetrates the back gate structure and the front gate structure is formed in the stacked transistor through a self-aligned etching process, which can relax the requirements for lithography accuracy, simplify the process, and improve process stability.

[0016] Furthermore, the gate interconnection between the back-side transistor and the front-side transistor can be led out from the back side only or from both sides (ie, the front side and the back side), thereby improving process flexibility.

[0017] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0019] Figure 1This is a schematic diagram of a first structure of a stacked transistor in an embodiment of the present application;

[0020] Figure 2 A schematic diagram of an implementation process of a method for preparing a stacked transistor in an embodiment of the present application;

[0021] Figures 3A to 3C A schematic diagram of a process for preparing a stacked transistor in an embodiment of the present application;

[0022] Figure 4 This is a schematic diagram of a second structure of a stacked transistor in an embodiment of the present application;

[0023] Figure 5 This is a schematic diagram of a third structure of a stacked transistor in an embodiment of the present application;

[0024] The above pictures:

[0025] 10. Stacked transistor; 11. Front-side transistor; 111. Front-side active structure; 112. Front-side bottom isolation layer; 113. Front-side interlayer dielectric layer; 114. Front-side gate dielectric layer; 115. Front-side gate structure; 116. Front-side top isolation layer; 1171. Front-side first source / drain structure; 1172. Front-side second source / drain structure; 1181. Front-side first gate sidewall; 1182. Front-side second gate sidewall; 1191. Front-side first source / drain metal; 1192. Front-side second source / drain metal; 12. Back-side transistor; 121. Back-side active structure; 122. Back-side bottom isolation layer; 123. Back-side interlayer dielectric layer; 124 , back gate dielectric layer; 125, back gate structure; 126, back top isolation layer; 1271, back first source and drain structure; 1272, back second source and drain structure; 1281, back first gate sidewall; 1282, back second gate sidewall; 1291, back first source and drain metal; 1292, back second source and drain metal; 13, insulating layer; 14, carrier wafer; 21, substrate; 22, protective layer; 23, shallow trench isolation structure; 231, shallow trench isolation layer; 241, front placeholder structure; 242, back placeholder structure; 25, first groove; 26, first gate contact structure; 27, second gate contact structure. DETAILED DESCRIPTION

[0026] Exemplary embodiments are described in detail herein, with examples illustrated in the accompanying drawings. When the following description refers to the drawings, identical numerals in different drawings represent identical or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with this application.

[0027] As Moore's Law continues to evolve, further scaling transistors beyond the gate-all-around (GAA) technology node is a hot topic in the industry. Stacked transistors, through three-dimensional transistor stacking, enable the integration of two or more layers of transistors in a vertical space, helping to further increase transistor integration density and improve circuit performance. This is considered a key technology for continuing integrated circuit scaling.

[0028] The vertical field-effect transistor (VFET) is considered one of the contenders with the greatest scaling potential after the fin field-effect transistor (FinFET) and lateral-GAA transistor. Its vertical stacking of the source, gate, and drain electrodes on the wafer plane frees it from the limitations of the chemical grinding process (CGP), allowing for further size reduction. Furthermore, VFETs lack high aspect ratio processes, and as a result, have attracted considerable attention.

[0029] The current vertical field-effect transistor stacking scheme has the following characteristics: 1. To isolate the lower and upper devices, sacrificial materials are buried in advance and undergo multiple steps of high-aspect-ratio trench deposition and lateral etching processes. 2. The bottom and top source and drain of the lower device, as well as the bottom source and drain of the upper device, are formed by depositing highly doped materials on both sides of the channel to form the source and drain regions. The purpose is to facilitate metal lead-out after patterning. 3. All metal leads are single-sided. In order to set up six terminals (source, gate, and drain of the lower device, source, gate, and drain of the upper device) within the limited space near the channel, two mutually perpendicular directions, x and y, are used. This gate interconnection process is not suitable for flipped stacked device structures and requires high lithography precision.

[0030] In order to solve the above technical problems, an embodiment of the present application provides a method for preparing a stacked transistor, which can simplify the process.

[0031] In some embodiments, the stacked transistor may include a front side transistor and a back side transistor that are stacked and arranged “back to back”. Both the front side transistor and the back side transistor are vertical field effect transistors.

[0032] In some embodiments, the front transistor includes a front first source-drain structure, a front gate structure, and a front second source-drain structure stacked in a vertical direction (ie, a first direction).

[0033] In some embodiments, the back-side transistor includes a back-side first source-drain structure, a back-side gate structure, and a back-side second source-drain structure stacked in a vertical direction.

[0034] In some embodiments, a shallow trench isolation (STI) layer is disposed between the front transistor and the back transistor, and the shallow trench isolation layer is used to isolate the front transistor from the back transistor.

[0035] In some embodiments, the stacked transistor includes a first gate contact structure, which has two forms: the first form is to penetrate the back gate structure and contact the front gate structure; the second form is to penetrate the back gate structure and the front gate structure.

[0036] It can be understood that the first gate contact structure is formed through processes such as lithography, etching, and deposition. During the etching process, it can be etched directly from the back transistor to the surface of the front transistor away from the back transistor, or it can be stopped after etching only to the front gate structure, as long as the first gate contact structure finally formed can electrically connect the back gate structure and the front gate structure at the same time.

[0037] In some embodiments, the first gate contact structure realizes gate interconnection between the front transistor and the back transistor by contacting the back gate structure and the front gate structure at the same time.

[0038] In an embodiment of the present application, by leading out a first gate contact structure inside the stacked transistor to realize gate interconnection between the front transistor and the back transistor, the volume of the stacked transistor can be saved, thereby improving the integration of the semiconductor device composed of the stacked transistor.

[0039] In the embodiments of the present application, the term "source-drain structure" is short for a source structure or a drain structure. Furthermore, the first source-drain structure and the second source-drain structure in the same transistor are different, i.e., one is a source structure and the other is a drain structure. For example, in a front-side transistor, when the first source-drain structure on the front side is a source structure, the second source-drain structure on the front side is a drain structure; or, when the first source-drain structure on the front side is a drain structure, the second source-drain structure on the front side is a source structure.

[0040] Figure 1 This is a schematic diagram of the first structure of the stacked transistor in the embodiment of the present application. Figure 1 (a) is the design layout of stacked transistors. Figure 1 (b) is a cross-sectional view of the stacked transistor along the AA' direction in the design layout; Figure 1 (c) is a cross-sectional view of the stacked transistor along the BB' direction in the design layout.

[0041] The following combination Figure 1 The method for preparing the stacked transistor provided in the embodiment of the present application is described.

[0042] Figure 2 This is a schematic diagram of an implementation process of the method for preparing a stacked transistor in an embodiment of the present application. Figure 2 As shown, the method for preparing the stacked transistor may include:

[0043] Step S201 : forming an active structure on a substrate, wherein the active structure includes a front active structure and a back active structure stacked in a first direction.

[0044] As can be understood, a substrate is provided, and then an active structure is patterned on the substrate, and then etched to form the active structure. The active structure includes a front active structure and a back active structure, which are stacked in a first direction. The front active structure is used to prepare a front transistor, and the back active structure is used to prepare a back transistor.

[0045] In some embodiments, the front active structure and the back active structure are formed by the same etching process, so that the active region of the front transistor and the active region of the back transistor are self-aligned.

[0046] In some embodiments, a silicon-on-insulator (SOI) substrate may be selected, and an insulating layer in the middle of the SOI substrate may be used to isolate the front active structure from the back active structure.

[0047] In some embodiments, when an SOI substrate is not selected, in order to achieve isolation between the front active structure and the back active structure, an intermediate isolation layer formed of an insulating material can be set between the front active structure and the back active structure during the preparation of the stacked transistor.

[0048] In some embodiments, after forming the active structure on the substrate, an insulating material can be deposited on the substrate and the active structure to form a shallow trench isolation structure. The shallow trench isolation structure encapsulates the active structure and covers the substrate. Next, a portion of the shallow trench isolation structure is etched back until the front active structure is exposed, while the back active structure remains encapsulated by the shallow trench isolation structure. In this way, the back active structure will not be damaged during the preparation of the front transistor, maintaining the integrity of the back active structure.

[0049] Step S202 : Based on the front active structure, a front first source-drain structure, a front gate structure, a front second source-drain structure and a front gate sidewall are formed in the front transistor.

[0050] In some embodiments, the front gate spacer includes a first front gate spacer extending along a first direction and a second front gate spacer extending along a second direction; the second direction is perpendicular to the first direction.

[0051] It can be understood that after the active structure is formed, a front first source and drain structure can be formed at the bottom of the front active structure (i.e., the portion of the front active structure close to the back active structure) by source and drain epitaxial growth. Then, according to the standard process for forming a vertical field effect transistor, a front gate structure in the front transistor is formed, and a front second source and drain structure is formed on the front gate structure. After forming the front first source and drain structure, the front gate structure, and the front second source and drain structure stacked in sequence, an insulating material is deposited on the surface of the front gate structure to form a front gate sidewall. The front gate sidewall covers the surface of the front gate structure parallel to the first direction and the surface parallel to the second direction. The front gate structure includes a front first gate sidewall and a front second gate sidewall, wherein the front first gate sidewall extends along the first direction, i.e., parallel to the first direction; the front second gate sidewall extends along the second direction, i.e., parallel to the second direction.

[0052] In some possible embodiments, the above-mentioned step S202 may include: based on the front active structure, forming a front first source-drain structure at the bottom of the front active structure; depositing insulating material on the first front source-drain structure to form a front bottom isolation layer of a preset height; the front bottom isolation layer wraps the first front source-drain structure; forming a front gate structure on the front bottom isolation layer; the front bottom isolation layer is used to isolate the front gate structure and the first front source-drain structure; depositing insulating material on the front gate structure to form a front top isolation layer of a preset height; forming a front second source-drain structure on the front top isolation layer; the front top isolation layer is used to isolate the front gate structure and the second front source-drain structure; depositing insulating material on the sidewall of the front gate structure to form a front gate sidewall.

[0053] In one example, a front first source-drain structure is formed at the bottom of the front active structure (i.e., the portion of the front active structure close to the back active structure), and then an insulating material is deposited on the front first source-drain structure and the shallow trench isolation structure to form a front bottom isolation layer of a preset height; the height of the front bottom isolation layer is greater than the height of the front first source-drain structure, so that the front bottom isolation layer can completely wrap the front first source-drain structure. According to the standard process for preparing vertical field effect transistors, a front gate dielectric layer and a front gate structure in the front transistor are formed. Then a front top isolation layer is formed on the front gate structure. The front top isolation layer and the front bottom isolation layer can be made of the same insulating material or different insulating materials, which is not specifically limited in the embodiments of the present application. Source and drain epitaxial growth is performed on the front top isolation layer to form a front second source-drain structure. Among them, the front top isolation layer is used to isolate the front gate structure and the front second source-drain structure. Finally, an insulating material is deposited on the sidewalls of the front gate structure to form a front gate sidewall.

[0054] It should be noted that the insulating material forming the front gate sidewall is different from the insulating material forming the front top isolation layer and the front bottom isolation layer.

[0055] In some embodiments, after forming the front bottom isolation layer, an interlayer dielectric material may be deposited in the front transistor to form a front interlayer dielectric (ILD) layer. The front interlayer dielectric layer is located between different structures in the front transistor to isolate them.

[0056] In some embodiments, after forming the front interlayer dielectric layer, a portion of the front interlayer dielectric layer may be etched to form other structures in the front transistor and to provide space for the other structures. For example, during the process of forming the front gate structure, a gate region of the front transistor may be formed in the front interlayer dielectric layer by photolithography, and a metal material may be deposited in the gate region of the front transistor to form the front gate structure.

[0057] In some possible embodiments, during the preparation of the front transistor, after forming the front first source and drain structure, the above method may further include: depositing semiconductor material on the side of the front first source and drain structure to form a front placeholder structure; wherein the front bottom isolation layer wraps the front placeholder structure.

[0058] It is understandable that since the source, drain and gate in the vertical field effect transistor are stacked in the vertical direction, if you want to lead out the bottom source or drain (such as the front first source and drain structure in the embodiment of the present application), you need to prepare source and drain metal next to the bottom source or drain. The front placeholder structure in the embodiment of the present application is the placeholder structure of the front first source and drain metal of the front first source and drain structure, that is, the front placeholder structure contacting the front first source and drain structure is first formed, and then the other structures in the front transistor are formed. In the interconnection process of the front transistor, the front placeholder structure is removed to form a fourth groove, and then the front first source and drain metal is formed in the fourth groove.

[0059] In some embodiments, the front placeholder structure and the front first source and drain structure are wrapped together by a front bottom isolation structure, and the front bottom isolation structure is used to isolate the front placeholder structure, the front first source and drain structure, and the front gate structure.

[0060] In some possible embodiments, during the process of forming the front transistor, the above method also includes: depositing a dielectric material on the front bottom isolation layer to form a front interlayer dielectric layer in the front transistor; performing photolithography on the front interlayer dielectric layer, and stopping etching to the front placeholder structure to form a third groove; removing the front placeholder structure to form a fourth groove; and depositing metal material in the third groove and the fourth groove to form a front first source and drain metal.

[0061] As will be appreciated, before forming the front-side first source and drain metal, a portion of the front-side interlayer dielectric layer located above the front-side placeholder structure is removed by photolithography to form a third recess. The front-side placeholder structure is then removed to form a fourth recess. The third and fourth recesses are connected. Metal material is then simultaneously filled into the third and fourth recesses to form the front-side first source and drain metal.

[0062] Step S203: flipping the wafer and thinning the substrate.

[0063] It can be understood that the wafer is flipped and the substrate is thinned until the back active structure is exposed, so that the back active structure is placed upward to facilitate the preparation of the back transistor.

[0064] In some embodiments, the substrate may be thinned by a chemical-mechanical planarization (CMP) process.

[0065] In some possible embodiments, before the above step S203, the above method for preparing the stacked transistor may further include: depositing an insulating material on a surface of the front transistor away from the back active structure to form an insulating layer; and bonding the insulating layer to the carrier wafer.

[0066] In an embodiment of the present application, the bonded carrier wafer can provide physical support for the flipped front transistor after flipping over, effectively preventing the front transistor from being broken by external force during the preparation of the back transistor.

[0067] Step S204 , forming a back first source-drain structure, a back gate structure, a back second source-drain structure and a back gate sidewall in the back transistor based on the back active structure.

[0068] In some embodiments, the back gate spacer includes a back first gate spacer extending along a first direction and a back second gate spacer extending along a second direction; the front transistor and the back transistor are stacked in the first direction.

[0069] It can be understood that after the active structure is formed, a back first source and drain structure can be formed at the bottom of the back active structure (i.e., the portion of the back active structure close to the front active structure) by source and drain epitaxial growth. Then, according to the standard process for forming a vertical field effect transistor, a back gate structure in the back transistor is formed, and a back second source and drain structure is formed on the back gate structure. After forming the back first source and drain structure, the back gate structure, and the back second source and drain structure stacked in sequence, an insulating material is deposited on the surface of the back gate structure to form a back gate sidewall. The back gate sidewall covers the surface of the back gate structure parallel to the first direction and the surface parallel to the second direction. The back gate structure includes a back first gate sidewall and a back second gate sidewall, wherein the back first gate sidewall extends along the first direction, i.e., parallel to the first direction; the back second gate sidewall extends along the second direction, i.e., parallel to the second direction.

[0070] In some possible embodiments, the above-mentioned step S204 may include: based on the back active structure, forming a back first source and drain structure at the bottom of the back active structure; depositing an insulating material on the back first source and drain structure to form a back bottom isolation layer of a preset height; the back bottom isolation layer wraps the back first source and drain structure; forming a back gate structure on the back bottom isolation layer; the back bottom isolation layer is used to isolate the back gate structure and the back first source and drain structure; depositing an insulating material on the back gate structure to form a back top isolation layer of a preset height; forming a back second source and drain structure on the back top isolation layer; the back top isolation layer is used to isolate the back gate structure and the back second source and drain structure; depositing insulating material on the sidewall of the back gate structure to form a back gate sidewall.

[0071] In one example, a back first source and drain structure is formed at the bottom of the back active structure (i.e., the portion of the back active structure close to the back active structure), and then an insulating material is deposited on the back first source and drain structure and the shallow trench isolation structure to form a back bottom isolation layer of a preset height; the height of the back bottom isolation layer is greater than the height of the back first source and drain structure, so that the back bottom isolation layer can completely wrap the back first source and drain structure. According to the standard process for preparing vertical field effect transistors, a back gate dielectric layer and a back gate structure in the back transistor are formed. Then a back top isolation layer is formed on the back gate structure. The back top isolation layer and the back bottom isolation layer can be made of the same insulating material or different insulating materials, which is not specifically limited in the embodiment of the present application. Source and drain epitaxial growth is performed on the back top isolation layer to form a back second source and drain structure. Among them, the back top isolation layer is used to isolate the back gate structure and the back second source and drain structure. Finally, an insulating material is deposited on the sidewalls of the back gate structure to form back gate sidewalls.

[0072] It should be noted that the insulating material forming the back gate sidewall is different from the insulating material forming the back top isolation layer and the back bottom isolation layer.

[0073] In some embodiments, after forming the back-side bottom isolation layer, an interlayer dielectric material may be deposited in the back-side transistor to form a back-side interlayer dielectric layer. The back-side interlayer dielectric layer is located between different structures in the back-side transistor to isolate the different structures.

[0074] In some embodiments, after forming the back-side interlayer dielectric layer, a portion of the back-side interlayer dielectric layer may be etched to form other structures in the back-side transistor and to provide space for the other structures. For example, in the process of forming the back-side gate structure, the gate region of the back-side transistor may be formed in the back-side interlayer dielectric layer by photolithography, and a metal material may be deposited in the gate region of the back-side transistor to form the back-side gate structure.

[0075] In step S205 , based on the back first gate sidewall, self-aligned etching is performed downward along a first direction, and the etching stops at the bottom of the front gate structure or the front transistor to form a first groove.

[0076] It can be understood that after the back transistor is formed, the gates of the front transistor and the back transistor are interconnected inside the stacked transistor. In the gate interconnection process, the back first gate side wall and the area on the side of the back first gate side wall are aligned, and the structure on the side of the back first gate side wall (such as the back interlayer dielectric layer, the back gate structure, the back bottom isolation layer, the shallow trench isolation structure, the front bottom isolation layer, etc.) is removed by selective etching. In this process, a selective etching process is selected, and the back first gate side wall is used as an etching barrier layer and will not be etched away, which provides the verticality of the etching and realizes self-aligned etching. The etching stops at the front gate structure (that is, the front gate structure is exposed) or stops at the bottom of the front transistor (that is, the part of the front transistor away from the back transistor) to form a first groove.

[0077] In some possible embodiments, the above-mentioned step S205 may include: forming a first photoresist on the surface of the back transistor away from the front transistor; under the action of the mask of the first photoresist, selectively etching the back transistor and the front transistor along a first direction, and stopping the etching to the bottom of the front gate structure or the front transistor to form a first groove; wherein, the back first gate sidewall is not selectively etched.

[0078] It can be understood that the first groove is formed by photolithography, and the first gate sidewall on the back side provides an etching barrier.

[0079] In some embodiments, during the process of forming the first groove, taking wet etching as an example, the back interlayer dielectric layer located on the side of the back first gate sidewall is first etched. When etching reaches the back second gate sidewall, the etching solvent is replaced, and the back second gate sidewall is continued to be selectively etched downward along the etched groove until the groove formed by etching passes through the back second gate sidewall, exposing the back gate structure; then, the etching solvent is continued to be replaced to selectively etch the back gate structure; according to this selective etching method, different structures are etched downward in turn until the first groove is formed.

[0080] In the embodiment of the present application, during the process of etching to form the first groove, the first gate sidewall on the back side blocks the etching under the selective effect of etching, thereby providing a more precise etching position and relaxing the requirements for photolithography.

[0081] Step S206 , depositing a metal material in the first groove to form a first gate contact structure.

[0082] In some embodiments, when etching stops at the front gate structure, the first gate contact structure penetrates the back gate structure and contacts the front gate structure; when etching stops at the bottom of the front transistor, the first gate contact structure penetrates the back gate structure and the front gate structure.

[0083] As can be understood, there are two forms of the first gate contact structure connecting the back gate structure and the front gate structure: the first form penetrates the back gate structure and contacts the surface of the front gate structure near the back transistor; the second form penetrates both the back gate structure and the front gate structure. The etching depth of the second form is greater than that of the first form. The two forms of the first gate contact structure can be selected based on actual conditions.

[0084] In some possible embodiments, when the first gate contact structure penetrates the back gate structure and contacts the front gate structure; before flipping the wafer and thinning the substrate, the above method may further include: based on the front first gate sidewall, self-aligned etching downward along the first direction, and stopping the etching at the front gate structure to form a second groove; depositing metal material in the second groove to form a second gate contact structure; the second gate contact structure contacts the front gate structure.

[0085] It can be understood that when the first gate contact structure does not penetrate the front gate structure, a second gate contact structure can be formed during the preparation of the front transistor. The preparation process of the second gate contact structure is the same as the preparation process of the first gate contact structure, and the etching stop position is in the front gate structure away from the surface of the back transistor.

[0086] In the embodiment of the present application, the introduction of the second gate contact structure can lead out the electrical connection of the gate from the front side of the stacked transistor while realizing the front transistor and the back transistor; in addition, when the second gate contact structure is formed, the etching depth of the first gate contact structure is smaller. Compared with simultaneously passing the first gate contact structure through the back gate structure and the front gate structure, the process is simpler and the requirement for the etching depth is lower.

[0087] In some possible embodiments, based on the first front gate sidewall, self-aligned etching is performed downward along a first direction, and the etching stops at the front gate structure to form a second groove, including: forming a second photoresist plate on the surface of the front transistor away from the back transistor; under the mask of the second photoresist plate, the front transistor is selectively etched along the first direction, and the etching stops at the front gate structure to form a second groove; wherein the first front gate sidewall is not selectively etched.

[0088] It can be understood that the second groove is formed by photolithography, and the front first gate sidewall provides an etching barrier.

[0089] In some embodiments, during the process of forming the second groove, taking wet etching as an example, the front interlayer dielectric layer located on the side of the front first gate side wall is first etched. When etching reaches the front second gate side wall, the etching solvent is replaced, and the front second gate side wall is continued to be selectively etched downward along the etched groove until the groove formed by etching passes through the front second gate side wall, exposing the front gate structure; then, the etching solvent is continued to be replaced, and the front gate structure is selectively etched until the front gate structure is exposed to form a second groove.

[0090] Below, the stacked transistor provided in the embodiment of the present application is described by taking the front transistor and the back transistor as vertical field effect transistors and the substrate as an SOI substrate as an example.

[0091] Figure 1 The stacked transistor 10 shown may be Figures 3A to 3C The process shown is prepared Figures 3A to 3C A schematic diagram of the preparation process of the stacked transistor in an embodiment of the present application.

[0092] Step 1: Provide a substrate 21 (see Figure 3A (a) in the figure.

[0093] Step 2: Deposit a layer of oxide on the substrate 21, and then deposit a layer of insulating material to form a protective layer 22. Then, etch the protective layer 22 and the substrate 21 to form an active structure, which includes a front active structure 111 and a back active structure 121 (see Figure 3A (b) in FIG. 1 ). The front active structure 111 and the back active structure 121 are isolated by an insulating layer in the middle of the SOI substrate.

[0094] In some embodiments, during the process of forming the active structure by etching, the etching depth is controlled by the etching time.

[0095] Step 3: Deposit insulating material on the active structure and the substrate 21 to form a shallow trench isolation structure 23; etch back the shallow trench isolation structure 23 to expose the front active structure 111, and based on the front active structure 111, form the front first source and drain structure 1171, the front placeholder structure 241, the front bottom isolation layer 112, the front interlayer dielectric layer 113, the front gate dielectric layer 114, the front gate structure 115, the front top isolation layer 116, the front second source and drain structure 1172, the front first gate sidewall 1181 and the front second gate sidewall 1182 in the front transistor 11 (see FIG. 2 ). Figure 3A (c) in the figure.

[0096] Step 4: Remove a portion of the front interlayer dielectric layer 113 and the front placeholder structure 241 by photolithography to form a third groove and a fourth groove, and deposit metal material in the third groove and the fourth groove to form a front first source and drain metal 1191; remove a portion of the front interlayer dielectric layer 113 above the front second source and drain structure to form a groove, and deposit metal material in the groove to form a front second source and drain metal 1192 (see Figure 3B (a) in the figure.

[0097] Step 5: Deposit insulating material on the front transistor 11 to form an insulating layer 13; bond the carrier wafer 14 to the insulating layer 13 (see Figure 3B (b) in the figure.

[0098] Step 6: Flip the wafer and thin the substrate 21 so that the surface of the front active structure 111 away from the back active structure 121 is exposed (see Figure 3B (c) in the figure.

[0099] Step 7: Etch back a portion of the shallow trench isolation structure 23 until the back active structure 121 is exposed; at the same time, retain a portion of the shallow trench isolation structure 23. The shallow trench isolation structure 23 that has not been etched is the shallow trench isolation layer 231. The shallow trench isolation layer 231 is used to isolate the front transistor 11 from the back transistor 12. The back first source and drain structure 1271, the back placeholder structure 242, the back bottom isolation layer 122, the back interlayer dielectric layer 123, the back gate dielectric layer 124, the back gate structure 125, the back top isolation layer 126, the back second source and drain structure 1272, the back first gate sidewall 1281 and the back second gate sidewall 1282 in the back transistor 12 are prepared according to the same process as that for preparing the front transistor 11 (see Figure 3C (a) in the figure.

[0100] Step 8: According to the process of forming the first source-drain metal 1191 on the front side and the second source-drain metal 1192 on the front side, form the first source-drain metal 1291 and the second source-drain metal 1292 on the back side (see Figure 3C (b) in the figure.

[0101] Step 9: Etch the first groove 25 by photolithography (see Figure 3C (c) in the figure.

[0102] Step 10: Deposit metal material in the first groove 25 to form a first gate contact structure 26 (see Figure 1 ).

[0103] At this point, the stacked transistor 10 is completed according to the above manufacturing method.

[0104] Figure 4This is a schematic diagram of the second structure of the stacked transistor in the embodiment of the present application, see Figure 4 As shown, the first gate contact structure 26 penetrates both the back gate structure 125 and the front gate structure 115 . Figure 4 The stacked transistor 10 shown has a height of Figure 1 Except for the height of the first gate contact structure 26 shown, other structures are the same, and will not be described in detail in the embodiment of the present application.

[0105] Figure 5 This is a schematic diagram of the third structure of the stacked transistor in the embodiment of the present application, see Figure 5 As shown, the first gate contact structure 26 passes through the back gate structure 125 and contacts the surface of the front gate structure 115 close to the back transistor 12, and the second gate contact structure 27 is led out from the surface of the front transistor 11 away from the back transistor 12 and extends to the surface of the front gate structure 115 away from the back transistor 12. Figure 5 The stacked transistor 10 shown has the same structure as the second gate contact structure 27. Figure 1 The stacked transistors 10 shown are the same and will not be described in detail in the embodiment of the present application.

[0106] In an embodiment of the present application, a first gate contact structure that penetrates the back gate structure and contacts the front gate structure, or a first gate contact structure that penetrates the back gate structure and the front gate structure is formed in the stacked transistor through a self-aligned etching process. This can relax the requirements for lithography accuracy, simplify the process, and improve process stability.

[0107] Furthermore, the gate interconnection between the back-side transistor and the front-side transistor can be led out from the back side only or from both sides (ie, the front side and the back side), thereby improving process flexibility.

[0108] Furthermore, the stacking of vertical field effect transistors and the interconnection of gates within the stacked transistors greatly reduce the area of ​​standard cells and improve the integration of semiconductor devices.

[0109] Furthermore, the stacked transistor provided in the embodiments of the present application can be inspected using an inspection and analysis instrument, such as a scanning electron microscope (SEM), a transmission electron microscope (TEM), a scanning transmission electron microscopy (STEM), etc. Taking TEM as an example, the stacked transistor provided in the embodiments of the present application can be inspected using TEM slicing, for example, the first gate contact structure penetrates the back gate structure and contacts the front gate structure, or penetrates both the back gate structure and the front gate structure.

[0110] The present application provides a semiconductor device, including: a stacked transistor as described in the above embodiment. The specific definition of the stacked transistor can be found in the above Figure 1 、 Figure 4 and Figure 5 The structure shown is not described in detail here.

[0111] The present application provides an electronic device, comprising: a circuit board and a semiconductor device as described in the above embodiment, wherein the semiconductor device is arranged on the circuit board. The semiconductor device includes the stacked transistor described above. The specific definition of the stacked transistor can be found in the above Figure 1 、 Figure 4 and Figure 5 , I will not go into details here.

[0112] In the description of this application, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the embodiments of the present application. In this application, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine different embodiments or examples described in this application and features of different embodiments or examples without contradiction.

[0113] The above are merely preferred embodiments of the present application and are not intended to limit the present application. Persons skilled in the art will readily appreciate that various modifications and variations are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present application shall be included within the scope of protection of the present application.

Claims

1. A method for preparing a stacked transistor, characterized in that: include: An active structure is formed on a substrate; the active structure includes a front active structure and a back active structure stacked in a first direction; Based on the front active structure, forming a front first source-drain structure, a front gate structure, a front second source-drain structure and a front gate sidewall in the front transistor; The front gate spacer includes a first front gate spacer extending along the first direction and a second front gate spacer extending along a second direction; the second direction is perpendicular to the first direction; flipping and thinning the substrate; Based on the back active structure, a back first source-drain structure, a back gate structure, a back second source-drain structure, and a back gate spacer are formed in the back transistor; the back gate spacer includes a back first gate spacer extending along the first direction and a back second gate spacer extending along the second direction; the front transistor and the back transistor are stacked in the first direction; Based on the back first gate sidewall, self-aligned etching is performed downward along the first direction, and the etching stops at the bottom of the front gate structure or the front transistor to form a first groove; Depositing a metal material in the first groove to form a first gate contact structure; when the etching stops at the front gate structure, the first gate contact structure penetrates the back gate structure and contacts the front gate structure; When the etching stops at the bottom of the front-side transistor, the first gate contact structure penetrates the back-side gate structure and the front-side gate structure.

2. The method for preparing a stacked transistor according to claim 1, wherein: The step of performing self-aligned etching downward along the first direction based on the back first gate sidewall, and stopping the etching at the bottom of the front gate structure or the front transistor to form a first groove, comprises: forming a first photoresist on a surface of the backside transistor away from the frontside transistor; Under the action of the mask of the first photoresist, the back transistor and the front transistor are selectively etched along the first direction, and the etching stops at the bottom of the front gate structure or the front transistor to form a first groove; wherein, the back first gate sidewall is not selectively etched.

3. The method for preparing a stacked transistor according to claim 1, wherein: In a case where the first gate contact structure penetrates the back gate structure and contacts the front gate structure; Before flipping the wafer and thinning the substrate, the method further includes: Based on the front first gate sidewall, self-aligned etching is performed downward along the first direction, and the etching stops at the front gate structure to form a second groove; A metal material is deposited in the second groove to form a second gate contact structure; the second gate contact structure contacts the front gate structure.

4. The method for preparing a stacked transistor according to claim 3, wherein: The method of self-aligning and etching downward along the first direction based on the front first gate sidewall, stopping at the front gate structure to form a second groove, comprises: forming a second photoresist on a surface of the front transistor away from the back transistor; Under the mask of the second photoresist, the front transistor is selectively etched along the first direction, and the etching stops at the front gate structure to form a second groove; wherein the front first gate sidewall is not selectively etched.

5. The method for preparing a stacked transistor according to claim 1, wherein: The method of forming a front first source-drain structure, a front gate structure, a front second source-drain structure and a front gate sidewall in a front transistor based on the front active structure includes: Based on the front active structure, forming the front first source-drain structure at the bottom of the front active structure; Depositing an insulating material on the first front source and drain structure to form a front bottom isolation layer of a preset height; the front bottom isolation layer wraps the first front source and drain structure; forming the front gate structure on the front bottom isolation layer; the front bottom isolation layer is used to isolate the front gate structure from the front first source and drain structure; Depositing an insulating material on the front gate structure to form a front top isolation layer of a preset height; forming the front second source-drain structure on the front top isolation layer; the front top isolation layer is used to isolate the front gate structure and the front second source-drain structure; An insulating material is deposited on the sidewalls of the front gate structure to form the front gate sidewalls.

6. The method for preparing a stacked transistor according to claim 5, wherein: After forming the first front source and drain structure, the method further comprises: depositing a semiconductor material on a side of the first front source and drain structure to form a front placeholder structure; wherein the front bottom isolation layer wraps the front placeholder structure; The method also includes: depositing a dielectric material on the front bottom isolation layer to form a front interlayer dielectric layer in the front transistor; performing photolithography on the front interlayer dielectric layer, and stopping the etching to the front placeholder structure to form a third groove; removing the front placeholder structure to form a fourth groove; and depositing metal material in the third groove and the fourth groove to form a front first source and drain metal.

7. The method for preparing a stacked transistor according to claim 1, wherein: The front transistor and the back transistor are vertical field effect transistors.

8. A stacked transistor, characterized in that: The stacked transistor is manufactured using the method for manufacturing a stacked transistor according to any one of claims 1 to 7, and the stacked transistor comprises: front-side transistor; Back side transistor; the front side transistor and the back side transistor are stacked in a first direction; a first gate contact structure; the first gate structure penetrates the back gate structure and contacts the front gate structure; or the first gate contact structure penetrates the back gate structure and the front gate structure.

9. A semiconductor device, characterized in that: include: The stacked transistor as claimed in claim 8.

10. An electronic device, characterized in that: include: A circuit board and the semiconductor device according to claim 9, wherein the semiconductor device is provided on the circuit board.

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