Fin-type field-effect transistor devices and their fabrication methods

Abstract

This application provides a finned field-effect transistor device and its fabrication method, relating to the field of semiconductor technology. The finned field-effect transistor device includes: a first substrate, a device layer, and a capping layer stacked sequentially; the device layer includes a plurality of field-effect transistors; the field-effect transistors include: a fin and a source, a first spacer layer, a gate, a second spacer layer, and a drain sequentially disposed along the extension direction of the fin, the source and drain being respectively disposed at both ends of the fin and respectively connected to the fin; the sides of the fin, source, gate, and drain covered by the capping layer are flush with each other.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a fin field-effect transistor device and its fabrication method. Background Technology

[0002] In the FinFET architecture, the gate is a forked structure resembling a fish fin. This design can significantly shorten the gate length of the transistor, thus leading to its widespread application. Consequently, those skilled in the art are keen to advance the technology related to FinFET devices. Summary of the Invention

[0003] This application provides a fin field-effect transistor device and its fabrication method to address the problem of how to improve fin field-effect transistor devices.

[0004] To solve the above-mentioned technical problems, this application is implemented as follows:

[0005] In a first aspect, embodiments of this application provide a fin field-effect transistor device.

[0006] The finned field-effect transistor device provided in this application includes: a first substrate, a device layer, and a capping layer stacked sequentially; the device layer includes a plurality of field-effect transistors; the field-effect transistor includes: a fin and a source, a first spacer layer, a gate, a second spacer layer, and a drain sequentially disposed along the extension direction of the fin, the source and the drain being respectively disposed at both ends of the fin and respectively connected to the fin; the sides of the fin, the source, the gate, and the drain covered by the capping layer are flush with each other.

[0007] Secondly, embodiments of this application provide a method for fabricating a fin field-effect transistor device.

[0008] The method for fabricating a finned field-effect transistor (FET) device provided in this application includes: forming a device layer on a second substrate, wherein the device layer includes a plurality of FETs, each FET including a fin and a source, a first spacer layer, a gate, a second spacer layer, and a drain sequentially disposed along the extension direction of the fin, wherein the source and the drain are respectively disposed at both ends of the fin and respectively connected to the fin; bonding the first substrate and the device layer to fix the device layer to the first substrate; thinning the second substrate while retaining the device layer, such that the sides of the fin, the source, the gate, and the drain are all exposed on the outer surface of the device layer.

[0009] The above-described technical solutions adopted in the embodiments of this application can achieve the following beneficial effects:

[0010] In the embodiments of this application, the sides of the fins, source, gate and drain covered by the capping layer are flush with each other, so that the source, gate and drain interconnects of the field effect transistor can be brought out simultaneously, which simplifies the steps of the electrode lead-out process, reduces the difficulty and complexity of the subsequent metal interconnect process, and thus can improve the chip yield.

[0011] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0012] To more clearly illustrate the technical solutions in the embodiments or related technologies of this application, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 This is a schematic diagram of a fin field-effect transistor device provided in an embodiment of this application, showing that the second dielectric layer on the side of the first spacer layer and the second spacer layer is in a transparent state, and the first dielectric layer on top of the fin field-effect transistor device is in a transparent state.

[0014] Figure 2 A schematic diagram of a fin field-effect transistor device provided in this application embodiment shows that in Figure 1 The diagram shows a fin field-effect transistor device with the first dielectric layer and connecting electrodes hidden.

[0015] Figure 3 A top view of a fin field-effect transistor device provided for an embodiment of this application;

[0016] Figure 4 for Figure 3 The image shows a cross-sectional view of a fin field-effect transistor device along section AA.

[0017] Figure 5 for Figure 3 The image shows a cross-sectional view of a fin field-effect transistor device along section BB.

[0018] Figure 6 A flowchart illustrating a method for fabricating a finned field-effect transistor device provided in this application embodiment;

[0019] Figure 7A flowchart illustrating a method for forming a device layer on a second substrate, as provided in this application embodiment;

[0020] Figure 8 A flowchart illustrating a method for forming a fin, a first spacer layer, a dummy gate layer, and a second spacer layer on a second substrate, provided for an embodiment of this application;

[0021] Figure 9 A schematic diagram of a second substrate including an ion implantation layer provided for an embodiment of this application;

[0022] Figure 10 A schematic diagram of a second substrate with fins formed, provided for an embodiment of this application;

[0023] Figure 11 A schematic diagram of a second substrate having fins, an isolation structure, a third dielectric layer, and a dummy gate layer formed, provided for an embodiment of this application;

[0024] Figure 12 for Figure 11 The image shows a left view of a second substrate having fins, an isolation structure, a third dielectric layer, and a dummy gate layer.

[0025] Figure 13 for Figure 12 The image shows a cross-sectional view along the CC section of a second substrate having fins, an isolation structure, a third dielectric layer, and a dummy gate layer formed thereon.

[0026] Figure 14 Provided for the embodiments of this application Figure 10 The diagram shown shows a second substrate with fins, an isolation structure, a third dielectric layer, and a dummy gate layer formed, with a portion of the third dielectric layer and fins removed.

[0027] Figure 15 for Figure 14 The top view shown is of a second substrate having fins, an isolation structure, a third dielectric layer, and a dummy gate layer formed thereon.

[0028] Figure 16 for Figure 15 The image shows a cross-sectional view along the DD section of a second substrate having fins, an isolation structure, a third dielectric layer, and a dummy gate layer formed thereon.

[0029] Figure 17 A schematic diagram of a second substrate having fins, an isolation structure, a third dielectric layer, a dummy gate layer, a source electrode, and a drain electrode provided for an embodiment of this application;

[0030] Figure 18 for Figure 17 The image shows a front view of a second substrate having fins, an isolation structure, a third dielectric layer, a dummy gate layer, a source, and a drain.

[0031] Figure 19 A schematic diagram of a second substrate having fins, an isolation structure, a third dielectric layer, a dummy gate layer, a source electrode, a drain electrode, and a second dielectric layer provided for embodiments of this application;

[0032] Figure 20 Provided for the embodiments of this application Figure 19 The diagram shows a second substrate with fins, an isolation structure, a third dielectric layer, a dummy gate layer, a source, a drain, and a second dielectric layer. The dummy gate layer is removed to form a gate trench.

[0033] Figure 21 A schematic diagram of a second substrate having fins, an isolation structure, a third dielectric layer, a source electrode, a drain electrode, a second dielectric layer, and a gate electrode provided for embodiments of this application;

[0034] Figure 22 for Figure 21 The top view shown is of a second substrate having fins, an isolation structure, a third dielectric layer, a source, a drain, a second dielectric layer, and a gate.

[0035] Figure 23 for Figure 22 The image shows a cross-sectional view along the EE section of a second substrate having fins, an isolation structure, a third dielectric layer, a source, a drain, a second dielectric layer, and a gate.

[0036] Figure 24 A schematic diagram of a first substrate and a second substrate having a device layer formed thereon provided for implementation of this application shows the situation before the first substrate and the second substrate are bonded;

[0037] Figure 25 A scenario where the device layers of a first substrate and a second substrate are in a bonded state, provided for implementation of this application;

[0038] Figure 26 A schematic diagram of a first substrate and a device layer provided for implementation of this application;

[0039] Figure 27 for Figure 26 The top view of the first substrate and device layer is shown in the figure.

[0040] Explanation of reference numerals in the attached figures:

[0041] 1-Fin Field-Effect Transistor Device;

[0042] 10-First substrate; 11-Oxide layer;

[0043] 20a - Second substrate; 20b - Ion implantation layer;

[0044] 20 - Device layer; 21 - Field-effect transistor; 211 - Fin; 212 - Source; 213 - First spacer layer; 214 - Gate; 215 - Second spacer layer; 216 - Drain; 217 - Dummy gate layer; 218 - Second dielectric layer; 219 - Gate trench; 2110 - Isolation structure; 2111 - Third dielectric layer;

[0045] 30 - Cover layer; 31 - First dielectric layer; 311 - Through hole; 32 - Connecting electrode. Detailed Implementation

[0046] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below in conjunction with specific embodiments and corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0047] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0048] Furthermore, although the terminology used in this application is selected from commonly known and used terms, some terms mentioned in this application specification may have been selected by the applicant at his or her own discretion, and their detailed meanings are explained in the relevant sections of this description.

[0049] Furthermore, this application is required to be understood not only through the actual terms used, but also through the meaning implied by each term.

[0050] The technical solutions provided by the various embodiments of this application are described in detail below with reference to the accompanying drawings.

[0051] This application provides a FinFET (Fin Field-Effect Transistor) device. Reference Figures 1 to 5 The fin field-effect transistor device 1 provided in this application embodiment includes: a first substrate 10, a device layer 20 and a capping layer 30 stacked sequentially.

[0052] Device layer 20 includes a plurality of field-effect transistors 21. Exemplarily, the field-effect transistors 21 may be a P-type metal-oxide-semiconductor field-effect transistor (PMOS) or an N-type metal-oxide-semiconductor field-effect transistor (NMOS).

[0053] The field-effect transistor 21 includes a fin 211 and a source 212, a first spacer layer 213, a gate 214, a second spacer layer 215, and a drain 216, which are sequentially arranged along the extending direction of the fin 211. In other words, the field-effect transistor 21 includes a fin 211, a source 212, a first spacer layer 213, a gate 214, a second spacer layer 215, and a drain 216. The source 212, the first spacer layer 213, the gate 214, the second spacer layer 215, and the drain 216 are arranged sequentially along the extending direction of the fin 211.

[0054] The source 212 and drain 216 are respectively disposed at both ends of the fin 211 and are respectively connected to the fin 211. The sides of the fin 211, source 212, gate 214 and drain 216 covered by the capping layer 30 are flush with each other. In other words, the sides of the fin 211, source 212, gate 214 and drain 216 that are away from the first substrate 10 are flush with each other.

[0055] In this way, in the embodiments of this application, the sides of the fin 211, source 212, gate 214 and drain 216 covered by the capping layer 30 are flush with each other, so that the interconnection of the source 212, gate 214 and drain 216 of the field effect transistor 21 can be simultaneously brought out, which simplifies the steps of the electrode lead-out process, reduces the difficulty and complexity of the subsequent metal interconnection process, and thus can improve the chip yield.

[0056] It should be noted that in related technologies, the bottom surface of the fin is integrally connected to the substrate, which easily leads to leakage current in the fin-effect transistor. However, in the solution provided by this application embodiment, the surface of the fin 211 facing away from the first substrate 10 is exposed on the outer surface of the device layer 20, making it less prone to forming leakage current channels during operation. Since leakage current channels directly affect the power consumption and operating frequency response of the fin field-effect transistor device 1, the solution provided by this application embodiment can reduce the power consumption of the fin field-effect transistor device 1 and improve its operating frequency response.

[0057] In some embodiments, the gate 214 has a recess 2141. The portion of the fin 211 located between the first spacer layer 213 and the second spacer layer 215 is accommodated in the recess 2141. In other words, with... Figure 4Taking the illustrated orientation as an example, the left, lower, and right sides of fin 211 are respectively surrounded by gate 214. Using the solution provided in this application embodiment, since the left, lower, and right sides of fin 211 are respectively surrounded by gate 214, the control capability of gate 214 over the channel can be improved, solving the leakage current channel problem of fin field-effect transistor devices in related technologies, and further reducing chip power consumption and improving frequency response.

[0058] In some embodiments, the cover layer 30 includes a first dielectric layer 31 and a plurality of connection electrodes 32. A plurality of vias 311 are provided in the portion of the first dielectric layer 31 opposite to the source 212, gate 214, and drain 216. A connection electrode 32 is provided in each via 311, and each connection electrode 32 is correspondingly connected to the source 212, gate 214, and drain 216.

[0059] For example, a first dielectric layer 31 can be formed on the side of the fin field-effect transistor device 1 away from the first substrate 10, and through-holes 311 can be formed in the first dielectric layer 31 at the positions opposite to the source 212, gate 214 and drain 216, respectively. Then, connection electrodes 32 can be formed in each through-hole 311, so that each connection electrode 32 is connected to the corresponding source 212, gate 214 and drain 216, respectively. This simplifies the connection electrode lead-out process, reduces the difficulty and complexity of subsequent metal interconnect processes, and thus improves chip yield.

[0060] This application provides a method for fabricating a fin field-effect transistor device, used to fabricate any of the fin field-effect transistor devices provided in this application. (Reference) Figure 6 The method for fabricating a fin field-effect transistor device provided in this application includes:

[0061] Step 410: A device layer is formed on the second substrate, wherein the device layer includes a plurality of field-effect transistors, and the field-effect transistors include: a fin and a source, a first spacer layer, a gate, a second spacer layer and a drain arranged sequentially along the extension direction of the fin, wherein the source and drain are respectively disposed at both ends of the fin and are respectively connected to the fin.

[0062] Step 420: Bond the first substrate and the device layer to fix the device layer to the first substrate.

[0063] Step 430: Thin the second substrate while retaining the device layer, so that the sides of the fins, source, gate and drain are all exposed on the outer surface of the device layer.

[0064] Combination Figures 21 to 24In the embodiments of this application, a device layer 20 can be formed on the second substrate 20a first. The device layer 20 includes a plurality of field-effect transistors 21. Each field-effect transistor 21 includes a fin 211 and a source 212, a first spacer layer 213, a gate 214, a second spacer layer 215, and a drain 216 arranged sequentially along the extension direction of the fin 211. The source 212 and the drain 216 are respectively disposed at both ends of the fin 211 and are respectively connected to the fin 211.

[0065] Furthermore, the first substrate 10 and the device layer 20 are bonded together to fix the device layer 20 to the first substrate 10.

[0066] Furthermore, the second substrate 20a is thinned while retaining the device layer 20, so that the sides of the fin 211, source 212, gate 214 and drain 216 are exposed to the outer surface of the device layer 20.

[0067] refer to Figure 7 In some embodiments, step 410 involves forming a device layer on the second substrate, wherein the device layer includes a plurality of field-effect transistors, the field-effect transistors including:

[0068] Step 411: A fin, a first spacer layer, a pseudo gate layer, and a second spacer layer are formed on the second substrate, wherein the two ends of the fin along its own extension direction are exposed on the outer surfaces of the first spacer layer and the second spacer layer, respectively.

[0069] Step 412: A source electrode is formed at one end of the fin along its own extension direction, and a drain electrode is formed at the other end.

[0070] Step 413: A second dielectric layer is disposed on the side of the first spacer layer opposite to the second spacer layer and on the side of the second spacer layer opposite to the first spacer layer, respectively.

[0071] Step 414: Remove the dummy gate layer to form a gate trench.

[0072] Step 415: Form the gate in the gate trench.

[0073] refer to Figures 14 to 21 In some embodiments, the device layer 20 can be formed on the second substrate 20a in the following manner.

[0074] A fin 211, a first spacer layer 213, a pseudo gate layer 217, and a second spacer layer 215 are formed on a second substrate 20a, wherein the two ends of the fin 211 along its own extension direction are exposed on the outer surfaces of the first spacer layer 213 and the second spacer layer 215, respectively.

[0075] Furthermore, a source electrode 212 is formed at one end of the fin 211 along its own extension direction, and a drain electrode 216 is formed at the other end.

[0076] Furthermore, a second dielectric layer 218 is provided on the side of the first spacer layer 213 opposite to the second spacer layer 215, and on the side of the second spacer layer 215 opposite to the first spacer layer 213.

[0077] Further, the dummy gate layer 217 is removed to form the gate trench 219.

[0078] Furthermore, a gate 214 is formed in the gate trench 219.

[0079] refer to Figure 8 In some embodiments, step 411, forming a fin, a first spacer layer, a dummy gate layer, and a second spacer layer on the second substrate, wherein the two ends of the fin along its own extension direction are exposed on the outer surfaces of the first spacer layer and the second spacer layer, respectively, includes:

[0080] Step 4111: Form fins on the second substrate.

[0081] Step 4112: Form an isolation structure between adjacent fins, wherein the top surface of the isolation structure is lower than the top surface of the fin.

[0082] Step 4113: Deposit a third dielectric layer on the top surface of the second substrate.

[0083] Step 4114: Deposit a pseudo gate layer on the third dielectric layer.

[0084] Step 4115: A first spacer layer and a second spacer layer are formed on opposite sides of the pseudo-gate layer along the extension direction of the fin, respectively.

[0085] Step 4116: Remove the portions of the third dielectric layer that are not covered by the first spacer layer, the pseudo gate layer, and the second spacer layer.

[0086] Step 4117: Remove the top of the fin that is not covered by the first spacer layer, the pseudo-gate layer, and the second spacer layer, so that the top surface of the fin is lower than the top surface of the isolation structure.

[0087] refer to Figures 9 to 14 In some embodiments, the fin 211, the first spacer layer 213, the dummy gate layer 217, and the second spacer layer 215 can be formed on the second substrate 20a in the following manner.

[0088] Fins 211 are formed on the second substrate 20a.

[0089] Furthermore, an isolation structure 2110 is formed between adjacent fins 211, wherein the top surface of the isolation structure 2110 is lower than the top surface of the fin 211.

[0090] Furthermore, a third dielectric layer 2111 is deposited on the top surface of the second substrate 20a;

[0091] Furthermore, a pseudo gate layer 217 is deposited on the third dielectric layer 2111;

[0092] Furthermore, a first spacer layer 213 and a second spacer layer 215 are formed on the two sides of the pseudo gate layer 217 that are opposite to each other along the extension direction of the fin 211.

[0093] Furthermore, the portions of the third dielectric layer 2111 not covered by the first spacer layer 213, the dummy gate layer 217, and the second spacer layer 215 are removed;

[0094] Furthermore, the top of the fin 211 that is not covered by the first spacer layer 213, the pseudo gate layer 217, and the second spacer layer 215 is removed so that the top surface of the fin 211 is lower than the top surface of the isolation structure 2110.

[0095] In some embodiments, step 420, bonding the first substrate and the device layer to fix the device layer to the first substrate, includes: performing a thermal oxidation process on the surface of the first substrate to form an oxide layer on the surface of the first substrate; and bonding the device layer to the side of the first substrate with the oxide layer to fix the device layer to the oxide layer.

[0096] For example, refer to Figure 24 and Figure 25 First, a thermal oxidation process can be performed on the surface of the first substrate 10 to form an oxide layer 11 on the surface of the first substrate 10. Further, the side of the first substrate 10 with the oxide layer 11 is bonded to the device layer 20 to fix the device layer 20 to the oxide layer 11.

[0097] In some embodiments, before forming a device layer on the second substrate, the fabrication method further includes: performing ion implantation to a target depth in the second substrate to form an ion implantation layer within the second substrate.

[0098] For example, refer to Figure 9 Ion implantation is performed at a target depth in the second substrate 20a to form an ion implantation layer 20b within the second substrate 20a.

[0099] In some embodiments, step 430, thinning the second substrate while retaining the device layer, so that the sides of the fins, source, gate, and drain are all exposed to the outer surface of the device layer, includes: peeling the second substrate from the ion implantation layer; and thinning the second substrate after the peeling process while retaining the device layer, so that the sides of the fins, source, gate, and drain are all exposed to the outer surface of the device layer.

[0100] For example, refer to Figures 25 to 27First, the second substrate 20a can be peeled off from the ion implantation layer 20b. Then, the second substrate 20a after peeling is thinned, retaining the device layer 20, so that the sides of the fin 211, source 212, gate 214 and drain 216 are exposed on the outer surface of the device layer 20.

[0101] In this way, by performing ion implantation at the target depth of the second substrate 20a, the ion implantation layer 20b can be made into a brittle layer, which facilitates the removal of a portion of the second substrate 20a through the ion implantation layer 20b in subsequent process flows.

[0102] In some embodiments, after thinning the second substrate, the method for fabricating a fin field-effect transistor device further includes: forming a first dielectric layer on the side of the device layer so that the device layer is located between the first substrate and the first dielectric layer; forming a plurality of vias at the locations of the first dielectric layer opposite to the source, gate and drain; and forming connection electrodes in each via so that each connection electrode is respectively connected to the source, gate and drain.

[0103] For example, refer to Figures 1 to 5 First, a first dielectric layer 31 is formed on the side of the device layer 20, so that the device layer 20 is located between the first substrate 10 and the first dielectric layer 31. Multiple vias 311 are formed in the first dielectric layer 31 at locations opposite to the source 212, gate 214, and drain 216. Connection electrodes 32 are provided in each via 311, so that each connection electrode 32 is respectively connected to the source 212, gate 214, and drain 216.

[0104] To facilitate those skilled in the art in better implementing the solutions provided in the embodiments of this application, more detailed examples are provided below for reference.

[0105] refer to Figure 9 In some embodiments, before forming the device layer 20 on the second substrate 20a, a silicon dioxide layer can be grown on the second substrate 20a by a thermal oxidation process, and hydrogen ions can be implanted into the second substrate 20a using an ion implanter to form an ion implantation layer 20b in the second substrate 20a, with the ion implantation layer 20b serving as a bonding separation layer.

[0106] The second substrate 20a is a semiconductor substrate, which can be P-type, N-type, or undoped. The second substrate 20a can be made of materials such as Si, Ge, SiC, GaAs, GaP, InP, InAs, InSb; or SiGe, GaAsP, AlGaAs, AlInAs, GaInAs, GaInP, or GaInAsP. After forming the ion implantation layer 20b, the silicon dioxide layer can be removed.

[0107] refer to Figure 10 and Figure 11 Furthermore, after forming an ion implantation layer 20b within the second substrate 20a, fins 211 can be formed on the second substrate 20a. Multiple fins 211 are spaced apart on the second substrate 20a. The widths of the fins 211 can be the same or different, and the spacing between the fins 211 can be the same or different. Depending on the fabrication process requirements of NMOS and PMOS, the fins 211 can be classified.

[0108] After the fins 211 are formed on the second substrate 20a, an isolation structure 2110 can be formed between adjacent fins 211. The isolation structure 2110 is located between adjacent fins 211 and covers the lower part of the fins 211.

[0109] It should be noted that, for example, in Figure 10 Based on the second substrate 20a shown, semiconductor processing is performed to obtain, as shown Figure 11 The steps of the second substrate 20a shown include:

[0110] Step one involves covering the sides and top of fin 211 with insulating dielectric material using methods such as high-density plasma chemical vapor deposition (HDP-CVD) or flowable chemical vapor deposition (FCVD), followed by an annealing process. The insulating dielectric material can be an oxide (e.g., SiO) or a nitride (e.g., SiN or other materials).

[0111] Step two involves using a planarization process, such as chemical-mechanical planarization (CMP), to remove the insulating dielectric material extending beyond the upper end of fin 211.

[0112] Step 3: An etch-back process is used to remove the insulating dielectric material from the outer periphery of the upper end of the cover fin 211, leaving the remaining insulating dielectric material to form an isolation structure 2110. The isolation structure 2110 is commonly referred to as shallow trench isolation (STI). Methods for removing the insulating dielectric material from the outer periphery of the upper end of the cover fin 211 include wet etching, dry etching, or a combination of dry and wet etching.

[0113] Step four: The dielectric material is deposited on the fin 211 by chemical vapor deposition (CVD) or atomic layer deposition (ALD) to form the third dielectric layer 2111.

[0114] Step 5: The dummy gate material is prepared by low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD) and deposited on the third dielectric layer 2111. The dummy gate material can be amorphous silicon, polycrystalline silicon, or polycrystalline silicon-germanium. After the dummy gate material is deposited, a planarization process can be performed.

[0115] Step six: A patterned pseudo-gate layer 217 and a third dielectric layer 2111 are formed through a pseudo-gate patterning process.

[0116] Furthermore, after forming the patterned pseudo-gate layer 217 and the third dielectric layer 2111, a suitable spacer layer deposition and etching process can be used to form a first spacer layer 213 and a second spacer layer 215 on both sides of the pseudo-gate layer 217. For example, the first spacer layer 213 and the second spacer layer 215 can be made of materials such as SiO, SiN, SICN, SiOCN, SiC, SiOC, or SiON.

[0117] Furthermore, after forming the first spacer layer 213 and the second spacer layer 215 on both sides of the pseudo gate layer 217, a source electrode 212 can be formed at one end of the fin 211 along its own extension direction, and a drain electrode 216 can be formed at the other end.

[0118] It should be noted that, exemplarily, based on the formation of a first spacer layer 213 and a second spacer layer 215 on both sides of the dummy gate layer 217, semiconductor processing can be performed to obtain the following... Figure 21 The second substrate 20a is shown.

[0119] Step 1: Remove the top of fin 211 on the side of the first spacer layer 213 facing away from the second spacer layer 215, and the top of fin 211 on the side of the second spacer layer 215 facing away from the first spacer layer 213, so that the top surface of fin 211 in this part is slightly lower than the top surface of isolation structure 2110. The removal method can be etching.

[0120] Step two involves using selective epitaxy to grow source / drain strain materials on the etched fin 211 near both ends of the first spacer layer 213 and the second spacer layer 215, forming source 212 and drain 216. For P-type metal-oxide-semiconductor field-effect transistors, the grown strain materials include, but are not limited to, SiGe, SiGeB, Ge, InSb, GaSb, or InGaSb. For N-type metal-oxide-semiconductor field-effect transistors, the grown strain materials include, but are not limited to, SiC, SiP, SiCP, InP, GaAs, AlAs, InAs, InAlAs, InGaAs, or SiC / SiP. Alternatively, strain layers can be fabricated using ion implantation of N-type or P-type materials.

[0121] Step 3: A contact etch stop layer is formed on the upper part of the second substrate 20a, thereby forming the second dielectric layer 218. For example, chemical vapor deposition, plasma-enhanced chemical vapor deposition, or atomic layer deposition can be used to deposit the contact etch stop layer on the upper surface of the second substrate 20a. For example, the contact etch stop layer covers the surfaces of the source electrode 212, drain electrode 216, isolation structure 2110, and fins 211 exposed outside the second substrate 20a. For example, the contact etch stop layer can be made of SiN, SiC, SiOC, SiON, SiCN, SiOCN, or combinations thereof.

[0122] Furthermore, a second dielectric layer 218 can be deposited on the contact etch barrier layer using processes such as chemical vapor deposition, plasma-enhanced chemical vapor deposition, fluid chemical vapor deposition, and spin coating. For example, the second dielectric layer 218 can be made of SiO, SiOC, silicon glass, BPSG, FSG, PSG, BSG, or a low-k material, wherein the low-k material can be BCB, FLARE, SILK, HSQ, or SiOF.

[0123] Step four involves using a planarization process, such as chemical mechanical polishing, to remove the contact etch barrier layer and the second dielectric layer 218 deposited above the pseudo gate layer 217 structure, thereby exposing the pseudo gate layer 217.

[0124] It should be noted that, for example, it can be done in the following ways: Figure 19 Based on the second substrate 20a shown, semiconductor processing is performed to obtain, as shown Figure 21 The second substrate 20a is shown.

[0125] Step one: Using dry etching or dry and / or wet etching processes, the dummy gate layer 217 is removed, forming the gate trench 219. (Reference) Figure 20The gate trench 219 is divided into a left gate trench and a right gate trench. For example, the left gate trench is used to form the gate of a P-type metal-oxide-semiconductor field-effect transistor; the right gate trench is used to form the gate of an N-type metal-oxide-semiconductor field-effect transistor. Figure 20 Taking the orientation shown as an example, the trench in the area where the two fins 211 (unmarked) are located in the upper left corner is the left gate trench, and the trench in the area where the two fins 211 (unmarked) are located in the lower right corner is the right gate trench.

[0126] Step two involves forming a gate material layer in the gate trench 219 using processes such as chemical vapor deposition, plasma-enhanced chemical vapor deposition, physical vapor deposition (PVD), and atomic layer deposition. The gate material layer typically consists of a dielectric layer, a work function layer, and a metal electrode layer. P-type work function gate material layers generally include TiN, WN, TaN, and conductive metal oxides. N-type work function gate material layers include Ta, TiAl, TiAlN, TaC, TaCN, TaSiN, TiSiN, and conductive metal oxides.

[0127] Step 3: Planarize to remove excess gate material layer, and the remaining gate material layer forms gate 214.

[0128] In the embodiments of this application, the device layer 20 and the first substrate 10 can be bonded in the following manner.

[0129] Step 1: A silicon oxide layer is formed on the surface of the first substrate 10 by a thermal oxidation process.

[0130] Step 2: Bond and cure the device layer 20 to the first substrate 10.

[0131] In the embodiments of this application, the second substrate 20a can be thinned in the following manner.

[0132] Step 1: Heat treatment is used to separate and remove the side of the second substrate 20a that is opposite to the first substrate 10 along the ion implantation layer 20b (bonding separation layer).

[0133] Step two, a planarization process is performed. The second substrate 20a is thinned on the side away from the first substrate 10 using a chemical mechanical polishing process until the fin 211, source 212, gate 214 and drain 216 are exposed.

[0134] In some embodiments, the connection electrode 32 may be formed in the following manner.

[0135] Step 1: Deposit a first dielectric layer 31 on the surface of the first substrate 10. The material can be SiO, SiN, SiOC, silicon glass, BPSG, FSG, PSG, BSG, or a low-k value material. Among them, the low-k value material is BCB, FLARE, SILK, HSQ, or SiOF, etc.

[0136] Step 2: Through-hole 311 is fabricated on the first dielectric layer 31 using a dry etching process, according to the requirements of metal patterned interconnection;

[0137] Step 3: Sequentially deposit and fill the via 311 with the corresponding electrode material, for example, the electrode material includes a metal adhesion layer, a barrier layer and a metal layer, and then perform a planarization process to expose the first dielectric layer 31, thereby removing excess metal material and realizing the electrode lead-out of the source / drain and gate.

[0138] Step 4, metal interconnect process: Design the back-end multilayer metal interconnect process according to the functional requirements of the fin field-effect transistor device 1.

[0139] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.

[0140] Although embodiments of this application have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and variations can be made to these embodiments without departing from the principles and spirit of the embodiments of this application, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A fin field effect transistor device, characterized by, The application relates to a fin field effect transistor device and a preparation method thereof. The fin field effect transistor device comprises a first substrate (10), a device layer (20) and a cover layer (30) which are sequentially stacked; The device layer (20) comprises a plurality of field effect transistors (21); The field effect transistor (21) comprises a fin (211) and a source (212), a first interval layer (213), a gate (214), a second interval layer (215) and a drain (216) which are sequentially arranged along the extension direction of the fin (211), the source (212) and the drain (216) are respectively arranged at two ends of the fin (211) and are respectively connected with the fin (211); The side surfaces of the fin (211), the source (212), the gate (214) and the drain (216) which are covered by the cover layer (30) are flush with each other and are all exposed to the outer surface of the device layer (20), wherein the side surfaces of the fin (211), the source (212), the gate (214) and the drain (216) which are exposed to the outer surface of the device layer (20) are used for electrical connection.

2. The fin field effect transistor device of claim 1, wherein, The gate (214) has a groove (2141), and the part of the fin (211) between the first interval layer (213) and the second interval layer (215) is accommodated in the groove (2141).

3. The fin field effect transistor device of claim 1, wherein, The cover layer (30) comprises a first dielectric layer (31) and a plurality of connection electrodes (32), the part of the first dielectric layer (31) which is opposite to the source (212), the gate (214) and the drain (216) is respectively provided with a plurality of through holes (311), each through hole (311) is provided with a connection electrode (32), and each connection electrode (32) is respectively connected with the source (212), the gate (214) and the drain (216).

4. A method of fabricating a fin field effect transistor device, the method comprising: The preparation method of the fin field effect transistor device comprises the following steps: forming a device layer (20) on a second substrate (20a), wherein the device layer (20) comprises a plurality of field effect transistors (21), the field effect transistor (21) comprises a fin (211) and a source (212), a first interval layer (213), a gate (214), a second interval layer (215) and a drain (216) which are sequentially arranged along the extension direction of the fin (211), the source (212) and the drain (216) are respectively arranged at two ends of the fin (211) and are respectively connected with the fin (211); bonding a first substrate (10) and the device layer (20) to fix the device layer (20) with the first substrate (10); thinning the second substrate (20a) to retain the device layer (20), so that the side surfaces of the fin (211), the source (212), the gate (214) and the drain (216) are flush with each other and are all exposed to the outer surface of the device layer (20), wherein the side surfaces of the fin (211), the source (212), the gate (214) and the drain (216) which are exposed to the outer surface of the device layer (20) are used for electrical connection.

5. The method of claim 4, wherein the method further comprises: Forming a device layer (20) on the second substrate (20a) comprises: forming the fin (211), the first spacer layer (213), the dummy gate layer (217) and the second spacer layer (215) on the second substrate (20a), wherein the fin (211) is exposed to the outer surfaces of the first spacer layer (213) and the second spacer layer (215) at two ends along the extension direction of the fin (211) respectively; forming a source (212) at one end of the fin (211) along the extension direction of the fin (211) and a drain (216) at the other end; forming a second dielectric layer (218) on the side of the first spacer layer (213) away from the second spacer layer (215) and on the side of the second spacer layer (215) away from the first spacer layer (213) respectively; removing the dummy gate layer (217) to form a gate trench (219); forming a gate (214) in the gate trench (219).

6. The method of claim 5, wherein the method further comprises: Forming the fin (211), the first spacer layer (213), the dummy gate layer (217) and the second spacer layer (215) on the second substrate (20a) comprises: forming the fin (211) on the second substrate (20a); forming an isolation structure (2110) between adjacent fins (211), wherein the top surface of the isolation structure (2110) is lower than the top surface of the fin (211); depositing a third dielectric layer (2111) on the top surface of the second substrate (20a); depositing a dummy gate layer (217) on the third dielectric layer (2111); forming a first spacer layer (213) and a second spacer layer (215) on the two sides of the dummy gate layer (217) away from each other along the extension direction of the fin (211) respectively; removing the part of the third dielectric layer (2111) not covered by the first spacer layer (213), the dummy gate layer (217) and the second spacer layer (215); removing the top part of the fin (211) not covered by the first spacer layer (213), the dummy gate layer (217) and the second spacer layer (215) so that the top surface of the fin (211) is lower than the top surface of the isolation structure (2110).

7. The method of claim 4, wherein the method further comprises: Bonding the first substrate (10) and the device layer (20) to fixedly connect the device layer (20) and the first substrate (10) comprises: performing a thermal oxidation process on the surface of the first substrate (10) to form an oxide layer (11) on the surface of the first substrate (10); bonding the side of the first substrate (10) provided with the oxide layer (11) and the device layer (20) to fixedly connect the device layer (20) and the oxide layer (11).

8. The method of claim 4, wherein the method further comprises: Before forming the device layer (20) on the second substrate (20a), the preparation method further comprises: performing ion implantation on the second substrate (20a) to a target depth to form an ion implantation layer (20b) in the second substrate (20a).

9. The method of claim 8, wherein the method further comprises: The second substrate (20a) is thinned to keep the device layer (20) and expose the side surfaces of the fin (211), the source (212), the gate (214) and the drain (216) to the outer surface of the device layer (20), comprising: The second substrate (20a) is peeled from the ion implantation layer (20b); The second substrate (20a) is thinned to keep the device layer (20) and expose the side surfaces of the fin (211), the source (212), the gate (214) and the drain (216) to the outer surface of the device layer (20).

10. The method of claim 4, wherein the method further comprises: After the second substrate (20a) is thinned, the preparation method of the fin field effect transistor device further comprises: A first dielectric layer (31) is arranged on the side surface of the device layer (20) to keep the device layer (20) between the first substrate (10) and the first dielectric layer (31); A plurality of through holes (311) are formed in the first dielectric layer (31) opposite to the source (212), the gate (214) and the drain (216); A connecting electrode (32) is arranged in each through hole (311) to keep each connecting electrode (32) connected to the source (212), the gate (214) and the drain (216) respectively.

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