A power semiconductor device

Abstract

The application discloses a power semiconductor device, comprising: a first semiconductor body for forming a depletion mode transistor; a second semiconductor body on a first surface of the first semiconductor body; the second semiconductor body is used for forming an enhancement mode transistor and is connected in series with the depletion mode transistor; a third semiconductor body with a lower band gap than the second semiconductor body is on a side of the second semiconductor body away from the first semiconductor body; the third semiconductor body comprises a first semiconductor layer, a third semiconductor layer and a second semiconductor layer with a different conductivity type from the first semiconductor layer and the third semiconductor layer and located between the first semiconductor layer and the third semiconductor layer, and the first semiconductor layer is used as a gate of the enhancement mode transistor; a first electrode is electrically connected with the second semiconductor body, the first semiconductor body and the third semiconductor layer; and a second electrode is on a second surface. The technical scheme provided by the application realizes passive over-temperature shutdown capability of the device by integrating a polysilicon NPN structure, and improves the robustness of the device.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of semiconductor technology, and particularly relate to a power semiconductor device. BACKGROUND

[0002] A field effect transistor (FET) is a semiconductor device that controls current using the electric field effect, and the core thereof is to modulate the channel conductivity by changing the gate voltage.

[0003] In the related art, since the SiC MOSFET (Metal Oxide Semiconductor Field Effect Transistor) has lower switching loss than the bipolar transistor, such as the IGBT (Insulate-Gate Bipolar Transistor), it is more competitive in high-frequency application scenarios, such as being used as a switching device in a bridge circuit.

[0004] However, due to the high channel interface state density of the silicon carbide MOSFET, the effective channel mobility is very low, which will increase the on-resistance of the device, and the chip will heat up on the surface; taking a SiC MOSFET bridge circuit working at high frequency as an example, the high switching speed of high frequency will increase dv / dt, and the rapid change of the Switch node voltage will cause the rapid charging and discharging of the Miller capacitor in the power MOSFET, and the charging and discharging current will form a potential difference between the gate and the source of the power MOSFET through the peripheral driving circuit, and this potential difference reaching a certain magnitude will cause the device to be mistakenly turned on, so that the upper and lower transistors are short-circuited, and finally the device is burned out.

[0005] This overcurrent damage is essentially caused by the heat on the surface of the device, which is usually collected by a sensor to convert the temperature signal into an electrical signal and transmit it to the driving circuit for processing and judgment, and then the device is turned off for protection. However, such feedback requires a lot of time, and the device is often damaged before it is turned off in time.

[0006] Therefore, how to realize the rapid over-temperature protection of the power semiconductor device to improve the robustness of the power semiconductor device has become a technical problem to be solved by those skilled in the art. SUMMARY

[0007] Embodiments of the present application provide a power semiconductor device to realize rapid over-temperature protection of the power semiconductor device and improve the robustness of the power semiconductor device.

[0008] The embodiment of the present application provides a power semiconductor device, comprising at least one cell structure, wherein the cell structure comprises:

[0009] a first semiconductor body comprising a first surface and a second surface arranged oppositely; the first semiconductor body is used for forming a depletion mode transistor;

[0010] a second semiconductor body located on the first surface of the first semiconductor body; the second semiconductor body is used for forming an enhancement mode transistor; wherein the material of the first semiconductor body is different from the material of the second semiconductor body, and the depletion mode transistor formed by the first semiconductor body is connected in series with the enhancement mode transistor formed by the second semiconductor body;

[0011] a third semiconductor body located on a side of the second semiconductor body away from the first semiconductor body and electrically isolated from the second semiconductor body; the material of the third semiconductor body has a lower band gap than the material of the second semiconductor body; wherein the third semiconductor body comprises a first semiconductor layer, a third semiconductor layer and a second semiconductor layer located between the first semiconductor layer and the third semiconductor layer, the second semiconductor layer has a different conductivity type from the first semiconductor layer and the third semiconductor layer, and the first semiconductor layer is used as a gate of the enhancement mode transistor;

[0012] a first electrode electrically connected with the second semiconductor body, the first semiconductor body and the third semiconductor layer;

[0013] a second electrode located on the second surface.

[0014] Optionally, the material of the first semiconductor body comprises SiC, the material of the second semiconductor body comprises GaN, and the material of the third semiconductor body comprises polysilicon.

[0015] Optionally, the first semiconductor body comprises a first ohmic contact region and a second ohmic contact region having different conductivity types, and the first ohmic contact region and the second ohmic contact region are arranged at the first surface and are spaced apart.

[0016] The first semiconductor body further comprises a buried layer located on a side of the first ohmic contact region and the second ohmic contact region close to the second surface.

[0017] The buried layer and the second ohmic contact region have the same conductivity type as the second semiconductor layer, and the depletion mode transistor formed by the first semiconductor body is a depletion mode junction field effect transistor.

[0018] Optionally, a projection of the first ohmic contact region onto the second surface is located in a projection of the buried layer onto the second surface, and the first ohmic contact region extends from a boundary of the first surface to the second ohmic contact region;

[0019] A part of the second ohmic contact region onto the second surface overlaps with a projection of the buried layer onto the second surface.

[0020] Optionally, the second semiconductor body comprises a third ohmic contact region and a fourth ohmic contact region, which are arranged at a surface of the second semiconductor body away from the first semiconductor body; the third ohmic contact region and the fourth ohmic contact region have a different conductivity type from the conductivity type of the second semiconductor body;

[0021] The enhanced transistor formed by the second semiconductor body is a metal-oxide-semiconductor field-effect transistor, a channel region of the enhanced transistor is located between the third ohmic contact region and the fourth ohmic contact region, and a projection of the first semiconductor layer onto the second semiconductor body covers the channel region of the enhanced transistor.

[0022] Optionally, in the third semiconductor body, a direction of the first semiconductor layer pointing to the third semiconductor layer is parallel to the first surface, and the third semiconductor layer is closer to the first electrode relative to the first semiconductor layer.

[0023] The cell structure further comprises a conductive structure; the conductive structure and the first electrode are located on opposite sides of the second semiconductor body; the first ohmic contact region and the second ohmic contact region of the exposed part of the second semiconductor body;

[0024] One end of the conductive structure is electrically connected with the exposed first ohmic contact region, and the other end of the conductive structure is electrically connected with the third ohmic contact region; the first electrode is electrically connected with the exposed second contact region, the fourth contact region and the third semiconductor layer.

[0025] Optionally, the cell structure further comprises:

[0026] A first insulating layer is located between the conductive structure and the sidewall of the second semiconductor body;

[0027] A second insulating layer is located between the first electrode and the sidewall of the second semiconductor body;

[0028] A third insulating layer is located between the first semiconductor body and the second semiconductor body.

[0029] Optionally, the cell structure further comprises:

[0030] a first ohmic contact layer on a surface of the first ohmic contact region away from the second surface, the conductive structure being electrically connected to the first ohmic contact region through the first ohmic contact layer;

[0031] and / or a second ohmic contact layer on a surface of the second ohmic contact region away from the second surface, the first electrode being electrically connected to the second ohmic contact region through the second ohmic contact layer;

[0032] and / or a third ohmic contact layer on a surface of part of the third ohmic contact region, the conductive structure being electrically connected to the third ohmic contact region through the third ohmic contact layer;

[0033] and / or a fourth ohmic contact layer on a surface of part of the fourth ohmic contact region, the first electrode being electrically connected to the fourth ohmic contact region through the fourth ohmic contact layer.

[0034] Optionally, the cell structure further comprises:

[0035] a fourth insulating layer between the third semiconductor body away from the first semiconductor body, the conductive structure away from the first semiconductor body, and the third semiconductor body and the conductive structure;

[0036] the first electrode is further on a surface of the fourth insulating layer away from the first semiconductor body, and extends along a sidewall of the fourth insulating layer, a sidewall of the third semiconductor body, a sidewall of the second semiconductor body, to the second ohmic contact region.

[0037] Optionally, the power semiconductor device comprises at least two of the cell structures, two adjacent cell structures being mirror-symmetrical in a first direction; the first direction being parallel to the first surface.

[0038] The technical scheme provided by the embodiment of the present application can improve the withstand voltage of the whole power semiconductor device by using the depletion mode transistor formed by the first semiconductor body, and on this basis, a third semiconductor body is arranged on the side of the second semiconductor body away from the first semiconductor body, the third semiconductor body comprises a first semiconductor layer, a third semiconductor layer and a second semiconductor layer between the first semiconductor layer and the third semiconductor layer, the second semiconductor layer is different from the first semiconductor layer and the third semiconductor layer in the conduction type, so that a PN junction is formed between the first semiconductor layer and the second semiconductor layer, and a PN junction is formed between the third semiconductor layer and the second semiconductor layer; wherein the first semiconductor layer is used as the gate of the enhancement mode transistor and is connected to the gate voltage capable of controlling the on state of the enhancement mode transistor, and the third semiconductor layer is electrically connected with the first electrode; when the power semiconductor device works normally, the gate and the first electrode of the device are electrically isolated by the PN junction, when the device occurs overcurrent, short circuit, overtemperature and the like, the surface of the second semiconductor body is seriously heated, the PN junction in the third semiconductor body will be intrinsically invalid, the gate voltage is clamped to the voltage of the first electrode to force the device to be turned off, at this time, because the band gap of the material of the second semiconductor body is higher than the band gap of the material of the third semiconductor body, the PN junction in the second semiconductor body will remain normal function and maintain blocking capability, avoiding damage of the device due to overtemperature, realizing the rapid overtemperature protection of the power semiconductor device, and improving the robustness of the power semiconductor device; in addition, the first semiconductor layer and the third semiconductor layer simultaneously provide an additional capacitance for the device, which makes the device form a lower voltage drop between the gate and the first electrode when the crosstalk current comes, thereby preventing the device from being mistakenly turned on due to crosstalk, realizing the short circuit protection of the power semiconductor device in high frequency application, and further improving the reliability of the power semiconductor device.

[0039] It should be understood that the content described in this part is not intended to identify key or important features of the embodiments of the present application, nor is it used to limit the scope of the present application. Other features of the present application will become apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0040] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0041] Figure 1 is a structure schematic diagram of a power semiconductor device provided by the embodiment of the present application;

[0042] Figure 2 is Figure 1 the equivalent circuit diagram of the structure shown in

[0043] Figure 3 is Figure 1 the working principle diagram of the structure shown in

[0044] Figure 4 is Figure 1 the working principle diagram of the structure shown in

[0045] Figure 5 is Figure 1 the working principle diagram of the third semiconductor body in the structure shown in

[0046] Figure 6 is Figure 1 another equivalent circuit diagram of the structure shown in

[0047] Figure 7 is a partial circuit schematic diagram of a half-bridge circuit provided by an embodiment of the present application. DETAILED DESCRIPTION

[0048] In order for those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor should fall within the scope of protection of the present application.

[0049] It should be noted that the terms "first", "second", and the like in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device that includes a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but can include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0050] An embodiment of the present application provides a power semiconductor device, Figure 1 is a structural schematic diagram of a power semiconductor device provided by an embodiment of the present application, Figure 2 is Figure 1 the equivalent circuit diagram of the structure shown in, reference Figure 1 andFigure 2 The power semiconductor device comprises at least one cell structure 01, and the cell structure 01 comprises:

[0051] A first semiconductor body 10 comprises a first surface and a second surface arranged oppositely; the first semiconductor body 10 is used for forming a depletion mode transistor;

[0052] A second semiconductor body 20 is located on the first surface of the first semiconductor body 10; the second semiconductor body 20 is used for forming an enhancement mode transistor; the depletion mode transistor formed by the first semiconductor body 10 and the enhancement mode transistor formed by the second semiconductor body 20 are connected in series; wherein the material of the first semiconductor body 10 is different from the material of the second semiconductor body 20;

[0053] A third semiconductor body 30 is located on the side of the second semiconductor body 20 away from the first semiconductor body 10 and is electrically isolated from the second semiconductor body 20; the material of the third semiconductor body 30 has a lower band gap than the material of the second semiconductor body 20; wherein the third semiconductor body 30 comprises a first semiconductor layer 31, a third semiconductor layer 33 and a second semiconductor layer 32 located between the first semiconductor layer 31 and the third semiconductor layer 33; the second semiconductor layer 32 has a different conductivity type from the first semiconductor layer 31 and the third semiconductor layer 33; the first semiconductor layer 31 is used as a gate G of the enhancement mode transistor;

[0054] A first electrode 1 is electrically connected with the second semiconductor body 20, the first semiconductor body 10 and the third semiconductor layer 33;

[0055] A second electrode 2 is located on the second surface.

[0056] Specifically, the first semiconductor body 10 is used for forming a first transistor 101, and the first transistor 101 is a depletion mode transistor and is in a normally open state. The second semiconductor body 20 is used for forming a second transistor 201, and the second transistor 201 is an enhancement mode transistor and is in a normally closed state, and the second transistor 201 can be controlled to be turned on by a gate voltage. The first transistor 101 and the second transistor 201 are connected in series, so that the on and off of the entire power semiconductor device is controlled by the second transistor 201 formed by the second semiconductor body 20.

[0057] A third semiconductor body 30 is arranged on the side of the second semiconductor body 20 away from the first semiconductor body 10, and the third semiconductor body 30 comprises a first semiconductor layer 31, a third semiconductor layer 33 and a second semiconductor layer 32 between the first semiconductor layer 31 and the third semiconductor layer 33, the second semiconductor layer 32 is different from the first semiconductor layer 31 and the third semiconductor layer 33 in the conduction type, so that a PN junction is formed between the first semiconductor layer 31 and the second semiconductor layer 32, and a PN junction is formed between the third semiconductor layer 33 and the second semiconductor layer 32; wherein the first semiconductor layer 31 is used as a gate G of an enhancement mode transistor (second transistor 201), and the gate voltage capable of controlling the on state of the enhancement mode transistor is accessed; the third semiconductor layer 33 is electrically connected with the first electrode 1.

[0058] When the power semiconductor device is normally working, the gate G (the first semiconductor layer 31) of the device and the first electrode 1 are electrically isolated by the PN junction. After the enhancement mode transistor formed by the second semiconductor body 20 is turned on, the first electrode 1 and the second electrode 2 are turned on through the depletion mode transistor formed by the first semiconductor body 10 and the enhancement mode transistor formed by the second semiconductor body 20, and the depletion mode transistor formed by the first semiconductor body 10 and the enhancement mode transistor formed by the second semiconductor body 20 together divide the voltage applied between the first electrode 1 and the second electrode 2, so as to improve the withstand voltage of the power semiconductor device. That is, by cascading the enhancement mode transistor formed by the second semiconductor body 20 and the depletion mode transistor formed by the first semiconductor body 10, the withstand voltage of the entire power semiconductor device can be improved by the depletion mode transistor formed by the first semiconductor body 10. Compared with forming an enhancement mode transistor by the first semiconductor body 10, the embodiment of the present application forms a depletion mode transistor by the first semiconductor body 10, which can reduce the resistance of the entire power semiconductor device. Wherein the first electrode 1 can be the source S, and the second electrode 2 is the drain D; or the first electrode 1 can be the drain D, and the second electrode 2 is the source S. Figure 1 In the structure shown, the first electrode 1 is the source S, and the second electrode 2 is the drain D.

[0059] When the power semiconductor device is in overcurrent, short circuit, over-temperature and other conditions, the second semiconductor body 20 surface is seriously heated, the PN junction in the third semiconductor body 30 will be intrinsic failure, the gate voltage on the first semiconductor layer 31 is clamped to the voltage of the first electrode 1, thereby forcing the device to shut down. At this time, due to the band gap of the material of the second semiconductor body 20 is higher than the band gap of the material of the third semiconductor body 30, the PN junction in the second semiconductor body 20 will remain normal function, maintain the blocking capability, avoid the device damage due to over-temperature, realize the fast over-temperature protection of the power semiconductor device, to improve the robustness of the power semiconductor device; in addition, the first semiconductor layer 31 and the third semiconductor layer 33 simultaneously provide additional gate-source capacitance for the device, which makes the device form a lower voltage drop between the gate G and the first electrode 1 when the crosstalk current comes, thereby preventing the device from being mistakenly turned on due to crosstalk, realizing the short circuit protection of the power semiconductor device in high frequency application, and further improving the reliability of the power semiconductor device.

[0060] The above is the core of the application, the structure of the power semiconductor device will be described in detail below with reference to the drawings.

[0061] Reference Figure 1 The first semiconductor body 10 can be formed by one-time epitaxy or by multiple epitaxy. That is, the first semiconductor body 10 can be a first semiconductor epitaxial layer 12, or a laminated structure formed by multiple first semiconductor epitaxial layers 12. The first semiconductor body 10 can also include a substrate 11, that is, the first semiconductor body 10 includes a substrate 11 and at least one first semiconductor epitaxial layer 12 formed on one side of the substrate 11. The material of the substrate 11 is the same as that of the first semiconductor epitaxial layer 12.

[0062] In the case where the first semiconductor body 10 includes a substrate 11 and a first semiconductor epitaxial layer 12, the second surface is the surface of the substrate 11 away from the first semiconductor epitaxial layer 12, and the first surface is the surface of the first semiconductor epitaxial layer 12 away from the substrate 11. Figure 1 The first semiconductor body 10 shown includes a substrate 11 and a first semiconductor epitaxial layer 12 on one side of the substrate 11, the first surface is the surface of the first semiconductor epitaxial layer 12 away from the substrate 11, and the second surface is the surface of the substrate 11 away from the first semiconductor epitaxial layer 12. The second semiconductor body 20 is arranged on the first surface of the first semiconductor body 10, and the second semiconductor body 20 can be formed by one-time epitaxy or by multiple epitaxy. That is, the second semiconductor body 20 can include a second semiconductor epitaxial layer, or a laminated structure formed by multiple second semiconductor epitaxial layers.

[0063] On the basis of the above embodiments, reference Figure 1Optionally, the first semiconductor body 10 comprises a first ohmic contact region 121 and a second ohmic contact region 122 with different conductive types, both of which are located on the first surface, and the first ohmic contact region 121 and the second ohmic contact region 122 are arranged in a spaced manner; the first semiconductor body 10 further comprises a buried layer 123 located on the side of the first ohmic contact region 121 and the second ohmic contact region 122 close to the second surface; wherein the buried layer 123 and the second ohmic contact region 122 have the same conductive type as the second semiconductor layer 32; the first ohmic contact region 121 has the same conductive type as the first semiconductor layer 31 and the third semiconductor layer 32; the first transistor 101 formed by the first semiconductor body 10 is a depletion mode junction field-effect transistor (JFET).

[0064] Specifically, the first semiconductor epitaxial layer 12 comprises a first ohmic contact region 121 and a second ohmic contact region 122 with different conductive types, and a buried layer 123 with the same conductive type as the second ohmic contact region 122, the buried layer 123 being located on the side of the first ohmic contact region 121 and the second ohmic contact region 122 close to the substrate 11. Among them, the conductive type of the first ohmic contact region 121 is the same as that of the first semiconductor epitaxial layer 12, both of which are the first conductive type, and the doping concentration of the first conductive type ions in the first ohmic contact region 121 is greater than that in the first semiconductor epitaxial layer 12; the conductive type of the second ohmic contact region 122 is the second conductive type. The first ohmic contact region 121 and the second ohmic contact region 122 are both heavily doped regions. The second ohmic contact region 122 and the buried layer 123 can be formed by implanting the second conductive type ions in the first semiconductor epitaxial layer 12, and the doping concentration of the second conductive type ions in the second ohmic contact region 122 can be equal to or not equal to that in the buried layer 123.

[0065] The orthographic projection of the first ohmic contact region 121 on the second surface is located in the orthographic projection of the buried layer 123 on the second surface, and the first ohmic contact region 121 extends from the boundary of the first surface to the second ohmic contact region 122; the partial orthographic projection of the second ohmic contact region 122 on the second surface overlaps the orthographic projection of the buried layer 123 on the second surface, and the partial orthographic projection of the second ohmic contact region 122 on the second surface does not overlap the orthographic projection of the buried layer 123 on the second surface. The region of the first semiconductor epitaxial layer 12 other than the buried layer 123, the first ohmic contact region 121 and the second ohmic contact region 122 is a drift region. The width between the buried layer 123 and the second ohmic contact region 122 satisfies that the channel can still be ensured not to be pinched off by the depletion region formed between the buried layer 123 and the drift region and the depletion region formed between the second ohmic contact region 122 and the drift region, so that the current flows between the second electrode 2 and the first ohmic contact region 121. The first ohmic contact region 121 is used to be electrically connected with the second semiconductor body 20 to realize the series connection of the enhancement mode transistor formed by the second semiconductor body 20.

[0066] The first conductive type can be N type and the second conductive type can be P type, that is, the conductive type of the first ohmic contact region 121 is N type and the conductive type of the second ohmic contact region 122 is P type. Alternatively, the first conductive type can be P type and the second conductive type can be N type, that is, the conductive type of the first ohmic contact region 121 is P type and the conductive type of the second ohmic contact region 122 is N type. Figure 1 In the structure shown, the conductive type of the first ohmic contact region 121 is N type and the conductive type of the second ohmic contact region 122 is P type. The first electrode 1 is a source S and the second electrode 2 is a drain D.

[0067] On the basis of each of the above embodiments, with reference to Figure 1 Optionally, the second semiconductor body 20 includes a third ohmic contact region 21 and a fourth ohmic contact region 22, which are arranged at the surface of the second semiconductor body 20 away from the first semiconductor body 10; the conductive types of the third ohmic contact region 21 and the fourth ohmic contact region 22 are different from the conductive type of the second semiconductor body 20; wherein the second transistor 201 formed by the second semiconductor body 20 is an enhancement mode metal oxide semiconductor field effect transistor (MOSFET).

[0068] Specifically, the third ohmic contact region 21 and the fourth ohmic contact region 22 can be formed by ion implantation on the surface of the second semiconductor body 20 away from the first semiconductor body 10. The third ohmic contact region 21 and the fourth ohmic contact region 22 have the same conductivity type, the channel region of the enhancement-mode transistor formed by the second semiconductor body 20 is located between the third ohmic contact region 21 and the fourth ohmic contact region 22, and the orthographic projection of the first semiconductor layer 31 on the second semiconductor body 20 covers the channel region of the enhancement-mode transistor, and the first semiconductor layer 31 is used as the gate G of the enhancement-mode transistor.

[0069] In the embodiment of the application, the second transistor 201 formed by the second semiconductor body 20 is an enhancement-mode MOSFET. The third ohmic contact region 21 has the same conductivity type as the first ohmic contact region 121, and the third ohmic contact region 21 and the first ohmic contact region 121 are electrically connected through the conductive structure 40, thereby realizing the series connection of the depletion-mode JFET formed by the first semiconductor body 10 and the enhancement-mode MOSFET formed by the second semiconductor body 20.

[0070] Further, when the conductivity type of the first ohmic contact region 121 is N type, the conductivity types of the third ohmic contact region 21 and the fourth ohmic contact region 22 are both N type, the conductivity type of the second semiconductor body 20 is P type, and the second transistor 201 formed by the second semiconductor body 20 is an enhancement-mode N-type MOSFET. The third ohmic contact region 21 is used as the source contact region of the second transistor 201, and the fourth ohmic contact region 22 is used as the drain contact region of the second transistor 201. The material of the conductive structure 40 includes a metal material. The conductive structure 40 electrically connects the first semiconductor body 10 and the second semiconductor body 20 by using a metal, thereby avoiding the problem of increased conduction loss caused by a heterojunction barrier, and avoiding the problem of increased leakage or reduced breakdown voltage caused by lattice mismatch.

[0071] On the basis of the above-mentioned embodiment, optionally, the material of the first semiconductor body 10 includes SiC, and the material of the second semiconductor body 20 includes GaN.

[0072] Specifically, the first transistor 101 formed by the first semiconductor body 10 is a depletion-mode SiC JFET, and the second transistor 201 formed by the second semiconductor body 20 is an enhancement-mode GaN MOSFET, so that the power semiconductor device includes a cascade of a high-voltage SiC JFET and a low-voltage GaN MOSFET. When the power semiconductor device is in a conduction state, the current flows from the drain D to the source S through the SiC JFET channel and the GaN MOSFET channel; when the device is in a blocking state, the SiC JFET bears most of the voltage, and the GaN MOSFET bears a small amount of voltage division.

[0073] The technical scheme provided by the embodiments of the present application replaces the SiC MOSFET structure in the related art with the GaN MOSFET, avoids the problem of too high interface state density of the SiC MOSFET, improves the channel mobility, and reduces the specific on-resistance of the device; and replacing the SiC MOSFET structure in the related art with the GaN MOSFET can also avoid the reliability problem caused by too large tunneling current of the SiC and the gate oxide layer (SiO2 layer).

[0074] When the power semiconductor device is turned on, referring to Figure 3 , and combining Figure 1 , the current flows from the drain D (the second electrode 2) of the power semiconductor device, passes through the drift region in the first semiconductor body 10, reaches the first ohmic contact region 121, and flows to the third ohmic contact region 21 through the interconnection metal, then reaches the fourth ohmic contact region 22 through the GaN MOSFET channel, and finally flows out from the source S (the first electrode 1) of the power semiconductor device. In the current I DS flowing path, the heterojunction is not needed to be passed through, and thus the influence of the heterojunction barrier on the on-state characteristics can be completely avoided.

[0075] When the power semiconductor device is reverse blocked, referring to Figure 4 , and combining Figure 1 , the PN junctions formed by the P-type buried layer 123 and the P-type second ohmic contact region 122 and the N-type drift region 124 are in a reverse bias state, so that the depletion region is widened, and the potential of the drain D of the device mainly drops in the depletion region, and thus the SiC JFET part will bear most of the voltage. In addition, since the second ohmic contact region 122 is electrically connected with the first electrode 1, the breakdown current will flow out through the second ohmic contact region 122 and the first electrode 1, and will not pass through the second semiconductor body 20, and thus the lattice mismatch between the second semiconductor body 20 and the first semiconductor body 10 will not affect the blocking characteristics of the device.

[0076] On the basis of the above embodiments, optionally, in the third semiconductor body 30, the direction (the first direction X) of the first semiconductor layer 31 pointing to the third semiconductor layer 33 is parallel to the first surface, and the third semiconductor layer 33 is relatively close to the first electrode 1 relative to the first semiconductor layer 31.

[0077] Specifically, the conductivity type of the first semiconductor layer 31 and the conductivity type of the third semiconductor are the same as the conductivity type of the first ohmic contact region 121, and the conductivity type of the second semiconductor layer 32 is the same as the conductivity type of the second ohmic contact region 122. Figure 1In the shown structure, the first ohmic contact region 121 is of N type, and the second ohmic contact region 122 is of P type; the first semiconductor layer 31 and the third semiconductor layer are both of N type, and the second semiconductor layer is of P type.

[0078] Reference Figure 5 , and in combination Figure 1 , the third semiconductor body 30 forms a lateral NPN structure, i.e. two reverse PN diodes. When the power semiconductor device is normally working, the PN diode formed between the first semiconductor layer 31 and the second semiconductor layer 32 is reverse biased, and the gate G of the power semiconductor device is electrically isolated from the first electrode 1 through the PN junction formed between the first semiconductor layer 31 and the second semiconductor layer 32; when the device is in overcurrent, short circuit, overtemperature, etc., the surface of the second semiconductor body 20 is seriously heated, and the PN junction in the third semiconductor body 30 will be intrinsically disabled, clamping the gate voltage on the first semiconductor layer 31 to the voltage of the first electrode 1, thereby forcing the device to shut down; at this time, since the band gap of the material of the second semiconductor body 20 is higher than that of the material of the third semiconductor body 30, the PN junction in the second semiconductor body 20 will remain normal function and maintain blocking capability, avoiding damage to the device due to overtemperature, and realizing rapid overtemperature protection of the power semiconductor device. The material of the second semiconductor body 20 includes but is not limited to GaN, and the material of the third semiconductor body 30 includes but is not limited to polysilicon.

[0079] In addition, in the related art, when the power MOSFET is applied to a high-frequency scenario, for example, in a bridge circuit, since the opening process of the upper bridge transistor is completed in a very short time, the voltage drop at the Switch point (the point at which the upper bridge transistor and the lower bridge transistor are electrically connected) changes rapidly during the opening process, and this voltage change will charge and discharge on the Miller capacitor (the capacitor between the gate G and the drain D) of the lower bridge transistor, and the charging and discharging current will form a potential difference on the peripheral driving loop, thereby causing the normally off lower bridge transistor to be mistakenly turned on, at this time the upper bridge transistor has already been turned on, and ultimately causing a short circuit between the voltage terminal VDD and the ground terminal GND, and the device is burned out.

[0080] Reference Figure 6 , and in combination Figure 7 , in the embodiment of the present application, the NPN structure formed by the first semiconductor layer 31, the second semiconductor layer 32 and the third semiconductor layer 33 can be equivalent to a capacitor , and the capacitor equivalent to the NPN structure is connected in parallel with the gate-source capacitor , i.e. the capacitor equivalent to the NPN structure provides an additional gate-source capacitor for the device. Reference Figure 1 , theFigure 1 The power semiconductor device shown is applied to the lower bridge transistor in a half-bridge circuit, and the NPN structure is equivalent to a capacitor The gate-source capacitor Connected in parallel, which makes the power semiconductor device form a lower voltage drop across the gate G and the source S when a crosstalk current comes, thereby avoiding the power semiconductor device from being mistakenly turned on due to crosstalk, achieving short-circuit protection for the power semiconductor device in high-frequency applications, and thereby improving the reliability of the power semiconductor device. Among them, the capacitor is the capacitor formed between the gate G and the source S, the capacitor is the capacitor formed between the first semiconductor layer 31 and the third semiconductor layer 33, the capacitor is the capacitor formed between the drain D and the source S; the resistance is the equivalent resistance of the first semiconductor layer 31, the resistance R is the external gate-source resistance, the inductance is the equivalent inductance of the line in the peripheral driving circuit, the resistance is the external gate resistance, the current is the Miller capacitor The crosstalk current formed by charging and discharging, is the driving gate voltage.

[0081] On the basis of the above embodiment, with reference to Figure 1 Optionally, the conductive structure 40 and the first electrode 1 are located on opposite sides of the second semiconductor body 20, and the first ohmic contact area 121 and the second ohmic contact area 122 of the exposed part of the second semiconductor body 20; wherein one end of the conductive structure 40 is electrically connected with the exposed first ohmic contact area 121, and the other end of the conductive structure 40 is electrically connected with the third ohmic contact area 21; the first electrode 1 is electrically connected with the exposed second ohmic contact area 122, the fourth ohmic contact area 22 and the third semiconductor layer 33.

[0082] On the basis of the above embodiment, optionally, the cell structure 01 further comprises:

[0083] The first insulating layer 51 is located between the conductive structure 40 and the side wall of the second semiconductor body 20;

[0084] The second insulating layer 52 is located between the first electrode 1 and the side wall of the second semiconductor body 20.

[0085] Specifically, the second semiconductor body 20 covers the first surface of the first semiconductor body 10 to expose part of the first ohmic contact region 121 and part of the second ohmic contact region 122, thereby facilitating the electrical connection of the conductive structure 40 with the first ohmic contact region 121 and the electrical connection of the first gate G with the second contact region. The exposed first ohmic contact region 121 and the exposed second ohmic contact region 122 are located on opposite sides of the second semiconductor body 20, and the conductive structure 40 and the first electrode 1 are located on opposite sides of the second semiconductor body 20. The first insulating layer 51 is arranged between the conductive structure 40 and the sidewall of the second semiconductor body 20, which can prevent the electrical connection of the conductive structure 40 and the sidewall of the second semiconductor body 20. The second insulating layer 52 is arranged between the first electrode 1 and the other sidewall of the second semiconductor body 20, which can prevent the electrical connection of the first electrode 1 and the sidewall of the second semiconductor body 20. The material of the first insulating layer 51 includes but is not limited to silicon oxide, and the material of the second insulating layer 52 includes but is not limited to silicon oxide. The first insulating layer 51 and the second insulating layer 52 can be formed synchronously. The material of the first insulating layer 51 and the second insulating layer 52 can also be a high-K dielectric material, such as 、 or .

[0086] Further, the cell structure 01 further comprises a third insulating layer 53, which is arranged between the third semiconductor body 30 and the second semiconductor body 20 to electrically isolate the third semiconductor body 30 and the second semiconductor body 20; the third insulating layer 53 can be understood as the gate insulating layer of the second transistor 201. The material of the third insulating layer 53 includes but is not limited to silicon oxide. The material of the third insulating layer 53 can also be a high-K dielectric material, such as 、 or .

[0087] On the basis of the above-mentioned embodiments, the cell structure 01 further comprises:

[0088] a first ohmic contact layer 61, which is arranged on the surface of the first ohmic contact region 121 away from the second surface, and the conductive structure 40 is electrically connected with the first ohmic contact region 121 through the first ohmic contact layer 61, thereby reducing the contact resistance between the conductive structure 40 and the first ohmic contact region 121;

[0089] and / or a second ohmic contact layer 62, which is arranged on the surface of the second ohmic contact region 122 away from the second surface, and the first electrode 1 is electrically connected with the second ohmic contact region 122 through the second ohmic contact layer 62, thereby reducing the contact resistance between the first electrode 1 and the second ohmic contact region 122;

[0090] And / or, a third ohmic contact layer 63 is located on a surface of a part of the third ohmic contact region 21, and the conductive structure 40 is electrically connected with the third ohmic contact region 21 through the third ohmic contact layer 63, so as to reduce the contact resistance between the conductive structure 40 and the third ohmic contact region 21.

[0091] And / or, a fourth ohmic contact layer 64 is located on a surface of a part of the fourth ohmic contact region 22, and the first electrode 1 is electrically connected with the fourth ohmic contact region 22 through the fourth ohmic contact layer 64, so as to reduce the contact resistance between the first electrode 1 and the fourth ohmic contact region 22.

[0092] On the basis of the above-mentioned embodiments, optionally, the cell structure 01 further comprises: a fourth insulating layer 54 located between the third semiconductor body 30 and the conductive structure 40, and away from the first semiconductor body 10; and the first electrode 1 is further located on a surface of the fourth insulating layer 54 away from the first semiconductor body 10, and extends along the sidewall of the fourth insulating layer 54, the sidewall of the third semiconductor body 30, the sidewall of the second semiconductor body 20, and the second ohmic contact region 122. Wherein, the fourth insulating layer 54 is used as an interlayer dielectric layer to electrically isolate the first electrode 1 from the third semiconductor body 30 and the conductive structure 40. The material of the fourth insulating layer 54 includes but is not limited to silicon oxide.

[0093] On the basis of the above-mentioned embodiments, with reference to ​ Optionally, the power semiconductor device comprises at least two cell structures 01, and the two adjacent cell structures 01 are mirror-symmetrical in a first direction X. The first direction X is perpendicular to a second direction Y, wherein the second direction Y is a direction in which the first surface points to the second surface.

[0094] Wherein, the two adjacent cell structures 01 share the same first electrode 1; and the two adjacent cell structures 01 share the same second electrode 2.

[0095] Further, the two adjacent cell structures 01 are synchronously prepared, that is, each same film layer in the two adjacent cell structures 01 is synchronously prepared.

[0096] It should be noted that the above only describes the preferred embodiments of the present application and the technical principles applied. Those skilled in the art will understand that the present application is not limited to the specific embodiments described herein, and those skilled in the art can make various obvious changes, re-adjustments and substitutions without departing from the scope of the present application. Therefore, although the present application has been described in detail through the above embodiments, the present application is not limited to the above embodiments, and can include more other equivalent embodiments without departing from the concept of the present application, and the scope of the present application is determined by the scope of the appended claims.

Claims

1. A power semiconductor device, characterized by, The power semiconductor device comprises at least one cell structure, the cell structure comprising: a first semiconductor body comprising a first surface and a second surface arranged oppositely; the first semiconductor body is configured to form a depletion mode transistor; a second semiconductor body located on the first surface of the first semiconductor body; the second semiconductor body is configured to form an enhancement mode transistor; the depletion mode transistor formed by the first semiconductor body and the enhancement mode transistor formed by the second semiconductor body are connected in series; wherein the material of the first semiconductor body is different from the material of the second semiconductor body; a third semiconductor body located on a side of the second semiconductor body away from the first semiconductor body and electrically isolated from the second semiconductor body; the material of the third semiconductor body has a lower band gap than the material of the second semiconductor body; wherein the third semiconductor body comprises a first semiconductor layer, a third semiconductor layer, and a second semiconductor layer located between the first semiconductor layer and the third semiconductor layer; the second semiconductor layer has a different conductivity type from the first semiconductor layer and a different conductivity type from the third semiconductor layer; the first semiconductor layer is configured as a gate electrode of the enhancement mode transistor; a first electrode electrically connected to the second semiconductor body, the first semiconductor body, and the third semiconductor layer; a second electrode located on the second surface.

2. The power semiconductor device according to claim 1, wherein: the material of the first semiconductor body comprises SiC, the material of the second semiconductor body comprises GaN; and the material of the third semiconductor body comprises polysilicon.

3. The power semiconductor device according to claim 1, wherein: the first semiconductor body comprises a first ohmic contact region and a second ohmic contact region having different conductivity types, both of which are located on the first surface and are arranged apart from each other; the first semiconductor body further comprises a buried layer located on a side of the first ohmic contact region and the second ohmic contact region close to the second surface; wherein the buried layer and the second ohmic contact region have the same conductivity type as the second semiconductor layer; and the depletion mode transistor formed by the first semiconductor body is a depletion mode junction field effect transistor.

4. The power semiconductor device according to claim 3, wherein: a normal projection of the first ohmic contact region on the second surface is located in a normal projection of the buried layer on the second surface, and the first ohmic contact region extends from a boundary of the first surface to the second ohmic contact region; a part of a normal projection of the second ohmic contact region on the second surface overlaps with the normal projection of the buried layer on the second surface.

5. The power semiconductor device according to claim 3, wherein: The second semiconductor body comprises a third ohmic contact region and a fourth ohmic contact region, which are arranged at a surface of the second semiconductor body away from the first semiconductor body; the third ohmic contact region and the fourth ohmic contact region are of a different conductivity type than the second semiconductor body; The enhancement-mode transistor formed by the second semiconductor body is a metal-oxide-semiconductor field-effect transistor, and a channel region of the enhancement-mode transistor is located between the third ohmic contact region and the fourth ohmic contact region; a normal projection of the first semiconductor layer on the second semiconductor body covers the channel region of the enhancement-mode transistor.

6. The power semiconductor device according to claim 5, wherein In the third semiconductor body, a direction in which the first semiconductor layer points to the third semiconductor layer is parallel to the first surface, and the third semiconductor layer is closer to the first electrode than the first semiconductor layer; The cell structure further comprises a conductive structure; the conductive structure and the first electrode are located on opposite sides of the second semiconductor body; the first ohmic contact region and the second ohmic contact region of the exposed part of the second semiconductor body; One end of the conductive structure is electrically connected to the exposed first ohmic contact region, and the other end of the conductive structure is electrically connected to the third ohmic contact region; the first electrode is electrically connected to the exposed second ohmic contact region, the fourth ohmic contact region, and the third semiconductor layer.

7. The power semiconductor device according to claim 6, characterized in that, The cell structure further comprises: A first insulating layer between the conductive structure and the sidewall of the second semiconductor body; A second insulating layer between the first electrode and the sidewall of the second semiconductor body; A third insulating layer between the third semiconductor body and the second semiconductor body.

8. The power semiconductor device of claim 6, wherein, The cell structure further comprises: A first ohmic contact layer on a surface of the first ohmic contact region away from the second surface, and the conductive structure is electrically connected to the first ohmic contact region through the first ohmic contact layer; And / or, a second ohmic contact layer on a surface of the second ohmic contact region away from the second surface, and the first electrode is electrically connected to the second ohmic contact region through the second ohmic contact layer; And / or, a third ohmic contact layer on a surface of part of the third ohmic contact region, and the conductive structure is electrically connected to the third ohmic contact region through the third ohmic contact layer; And / or, a fourth ohmic contact layer on a surface of part of the fourth ohmic contact region, and the first electrode is electrically connected to the fourth ohmic contact region through the fourth ohmic contact layer.

9. The power semiconductor device of claim 6, wherein, The cell structure further comprises: A fourth insulating layer between the third semiconductor body away from the first semiconductor body, the conductive structure away from the first semiconductor body, and the third semiconductor body and the conductive structure. The first electrode is also located on the surface of the fourth insulating layer far away from the first semiconductor body and extends along the sidewall of the fourth insulating layer, the sidewall of the third semiconductor body and the sidewall of the second semiconductor body to the second ohmic contact region.

10. The power semiconductor device of claim 1, wherein, The structure comprises at least two of the cell structures, and two adjacent cell structures are mirror-symmetrical in a first direction; the first direction is parallel to the first surface.

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