Preparation method of low-roughness n-type electrode LED chip and low-roughness n-type electrode LED chip

Abstract

The invention belongs to the technical field of LED chips, and particularly relates to a preparation method of a low-roughness n-type electrode LED chip, which comprises the following steps: taking a conventional first n-type contact electrode of an AlGaN ultraviolet LED chip as a sacrificial electrode, carrying out high-temperature annealing alloying on the first n-type contact electrode to form n-type ohmic contact, forming an epitaxial wafer barrier at the moment, and carrying out high-temperature annealing alloying on the sacrificial electrode to form n-type ohmic contact; the first n-type contact electrode is removed by adopting a wet etching method, and then the second n-type electrode with a proper work function is evaporated, so that the effects of thickening the electrode and expanding current are achieved at the same time, and excellent appearance and voltage of the second n-type electrode can be obtained. According to the invention, the problems of poor appearance, yield loss and reliability caused by roughness of the first n-type contact electrode after high-temperature annealing alloying can be effectively solved.

Description

Technical Field

[0001] The present invention belongs to the technical field of LED chips, and in particular relates to a low-roughness n-type electrode LED chip and a preparation method thereof. Background Art

[0002] Conventional n-type contact electrodes for AlGaN UV LED chips, such as CrAlTiAu and TiAlTiAu, generally contain aluminum metal. During the annealing and alloying process to form an ohmic contact, the Al in the Al-containing electrode migrates and remains molten, easily forming particles such as AlAu2 or AlAu4, which increases the surface roughness of the n-type ohmic contact electrode. Rough n-type contact electrodes will further cause metal electromigration, affecting device reliability. Furthermore, rough electrodes exhibit color differences during visual inspection of incoming chips, forcing them to be removed. This significantly increases the workload of post-process visual inspections and results in yield loss. In particular, when the n-type contact electrode becomes rough, forming large protrusions, the passivation layer above the electrode cannot cover them, causing the n-electrode to connect to the p-pad electrode, resulting in chip leakage and lamp failure, seriously affecting the chip's optoelectronic performance and yield. Summary of the Invention

[0003] In order to solve the technical problem that the conventional rough n-type contact electrode may further cause metal electromigration and affect device reliability, the present invention provides a low-roughness n-type electrode LED chip and a preparation method thereof.

[0004] In order to solve the above technical problems, the technical solution adopted by the present invention is: A method for preparing a low-roughness n-type electrode LED chip comprises the following steps: S1, growing an AlN buffer layer, an n-type semiconductor layer, a quantum well layer, and a p-type semiconductor layer on the substrate in order from bottom to top to prepare an epitaxial wafer structure; S2. Patterning an n-type semiconductor layer groove on the p-type semiconductor layer using a photoresist, and etching from top to bottom to the n-type semiconductor layer to prepare an n-type semiconductor groove; S3, patterning a first n-type contact electrode on the n-type semiconductor groove using a photoresist, and evaporating the first n-type contact electrode on the n-type semiconductor layer; S4, performing high-temperature rapid annealing on the first n-type contact electrode in a nitrogen atmosphere to form an n-type ohmic contact; S5, using the first n-type contact electrode as a sacrificial electrode and removing it by etching with a wet etching solution; S6. Patterning a first p-type contact electrode on the p-type semiconductor layer using a photoresist, and vapor-depositing the first p-type contact electrode on the p-type semiconductor layer; S7, annealing the first p-type contact electrode at a low temperature for a long time in an air atmosphere to form a p-type ohmic contact; S8. Patterning a second n-type electrode using photoresist at the location where the first n-type contact electrode is removed, patterning a second p-type electrode using photoresist on the first p-type contact electrode, and simultaneously evaporating a second n-type electrode and a second p-type electrode.

[0005] The depth of the groove of the n-type semiconductor layer in S2 is 400nm-900nm.

[0006] The first n-type contact electrode in S3 is made of one or more metals selected from the group consisting of Cr, Al, Ti, Au, Ni, and Pt.

[0007] The annealing temperature in S4 is 600° C.-1000° C., and the annealing time is 30s-400s.

[0008] The wet etching solution in S5 is one or more of nitric acid, hydrochloric acid, aqua regia, buffered oxide etching solution, phosphoric acid, gold etching solution, hydrofluoric acid, sulfuric acid, hydrogen peroxide, chromium etching solution, and aluminum etching solution.

[0009] The first p-type contact electrode in S6 is made of one or more metals selected from Ni, Au, Pt, Ti, and Rh.

[0010] The annealing temperature in S7 is 400° C.-700° C., and the annealing time is 60s-1200s.

[0011] In the step S8 , the second n-type electrode has the same line width and shape as the first n-type contact electrode, and the second p-type electrode has the same line width and shape as the first p-type contact electrode.

[0012] The second n-type electrode and the second p-type electrode in S8 are both made of one or more metals selected from the group consisting of Cr, Al, Ti, Au, Ni, and Pt.

[0013] A low-roughness n-type electrode LED chip comprises a substrate, an AlN buffer layer, an n-type semiconductor layer, a quantum well layer, a p-type semiconductor layer, a first n-type contact electrode, a first p-type contact electrode, a second n-type electrode, and a second p-type electrode. The AlN buffer layer is grown on the substrate, the n-type semiconductor layer is grown on the AlN buffer layer, the quantum well layer is grown on the n-type semiconductor layer, and the p-type semiconductor layer is grown on the quantum well layer. The p-type semiconductor layer is etched from top to bottom to form an n-type semiconductor groove. The first n-type contact electrode is grown on the n-type semiconductor groove, the first p-type contact electrode is grown on the p-type semiconductor layer, the first n-type contact electrode is removed by etching with a wet etching solution, the second n-type electrode is grown at the position where the first n-type contact electrode is removed, and the second p-type electrode is grown on the first p-type contact electrode.

[0014] Compared with the prior art, the present invention has the following beneficial effects: This invention uses the conventional first n-type contact electrode of an AlGaN UV LED chip as a sacrificial electrode. This first n-type contact electrode undergoes high-temperature annealing and alloying to form an n-type ohmic contact. At this point, the epitaxial wafer barrier is formed. The first n-type contact electrode is then removed using wet etching, followed by vapor deposition of a second n-type electrode with an appropriate work function. This thickens the electrode and spreads the current, resulting in an excellent second n-type electrode appearance and voltage. This invention effectively addresses the issues of poor appearance, yield loss, and reliability caused by the roughness of the first n-type contact electrode after high-temperature annealing and alloying. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] To more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for the embodiments or the description of the prior art. Obviously, the drawings described below are merely exemplary, and those skilled in the art can, without inventive effort, derive other implementation drawings based on the provided drawings.

[0016] The structures, proportions, sizes, etc. illustrated in this specification are intended solely to complement the contents disclosed herein and to facilitate understanding and reading by persons skilled in the art. They are not intended to limit the conditions under which the present invention may be implemented and therefore have no substantive technical significance. Any structural modifications, changes in proportions, or adjustments in sizes, without affecting the efficacy and objectives of the present invention, shall remain within the scope of the technical contents disclosed herein.

[0017] Figure 1 Schematic diagram of the epitaxial wafer structure of the present invention; Figure 2 This is a schematic diagram of the present invention after forming the first n-type contact electrode; Figure 3 A schematic diagram of the present invention after forming the second n-type electrode and the second p-type electrode; Figure 4 This is the appearance morphology of the n-type contact electrode of the control example after annealing and alloying; Figure 5 This is a topographical image of the first n-type contact electrode after wet etching of the present invention; Figure 6 This is a comparison of the appearance of the control example and the embodiment after evaporation of the second n-type electrode; Figure 7 This is the mapping diagram of the control example VF1; Figure 8 This is the mapping diagram of the control example IR; Figure 9This is the mapping diagram of VF1 in the embodiment of the present invention; Figure 10 This is the mapping diagram of the IR embodiment of the present invention.

[0018] Wherein: 101 is a substrate, 102 is an AlN layer, 103 is an n-type semiconductor layer, 104 is a quantum well layer, 105 is a p-type semiconductor layer, 201 is a first n-type contact electrode, 202 is a first p-type contact electrode, 301 is a second n-type electrode, and 302 is a second p-type electrode. DETAILED DESCRIPTION

[0019] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are only part of the embodiments of this application, not all the embodiments. These descriptions are only to further illustrate the features and advantages of the present invention, rather than to limit the claims of the present invention. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0020] The following embodiments of the present invention are described in further detail with reference to the accompanying drawings and examples. The following embodiments are used to illustrate the present invention but are not intended to limit the scope of the present invention.

[0021] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature specified as "first" or "second" may explicitly or implicitly include one or more of such features. Throughout this application, unless otherwise specified, "plurality" means two or more.

[0022] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed, detachable, or integral connections; mechanical or electrical connections; direct or indirect connections through an intermediate medium; and internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances. Example

[0023] This embodiment provides a method for preparing a low-roughness n-type electrode LED chip, comprising the following steps: Step 1: Prepare an AlN buffer layer 102, an n-type semiconductor layer 103, a quantum well layer 104 and a p-type semiconductor layer 105 on a substrate 101 from bottom to top to obtain an epitaxial wafer structure.

[0024] Step 2: Based on the structure of step 1, use photoresist to pattern the n-type semiconductor layer groove, and use ICP dry etching to etch from top to bottom to the n-type semiconductor layer 103 to obtain the n-type semiconductor groove.

[0025] Furthermore, in step 2, the depth of the groove of the n-type semiconductor layer is 400 nm-900 nm, and preferably, the etching depth is 650 nm.

[0026] Step 3: Based on the structure in step 2, a first n-type contact electrode 201 is patterned using photoresist, and the first n-type contact electrode 201 is evaporated on the n-type semiconductor layer 103 using a vacuum metal evaporation machine.

[0027] Furthermore, in step 3, the first n-type contact electrode 201 is composed of one or more metals selected from Cr, Al, Ti, Au, Ni, and Pt. Preferably, the first n-type contact electrode 201 is CrAlNiAuTi, and the thickness of each metal layer is 20nm / 100nm / 10nm / 50nm / 10nm, respectively.

[0028] Step 4: The first n-type contact electrode 201 is subjected to high-temperature rapid annealing in a nitrogen atmosphere to form an n-type ohmic contact.

[0029] Furthermore, in step 4, the annealing temperature is 600° C.-1000° C., and the annealing time is 30s-400s. Preferably, the annealing temperature is 900° C., and the annealing time is 30s.

[0030] Step 5: Based on the structure of step 4, the first n-type contact electrode 201 is used as a sacrificial electrode and is removed using a wet etching solution.

[0031] The wet etching solution uses one or more of nitric acid, hydrochloric acid, aqua regia, BOE (buffered oxide etchant), phosphoric acid, gold etching solution, hydrofluoric acid, sulfuric acid, hydrogen peroxide, chromium etching solution, and aluminum etching solution.

[0032] Preferably, the surface is first placed in BOE (buffered oxide etchant) for 10 minutes, rinsed with ultrapure water in a quick-drain and quick-rinse tank for 3 cycles, then placed in aqua regia solution for 20 minutes, rinsed with ultrapure water in a quick-drain and quick-rinse tank for 3 cycles, and finally placed in chromium etching solution for 20 minutes, rinsed with ultrapure water in a quick-drain and quick-rinse tank for 5 cycles, and dried in a spin dryer.

[0033] Step 6: Based on the structure of step 5, the first p-type contact electrode 202 is patterned using photoresist, and the first p-type contact electrode 202 is evaporated on the p-type semiconductor layer 105 using a vacuum metal evaporation machine.

[0034] Furthermore, in step 6, the first p-type contact electrode 202 is made of one or more metals selected from Ni, Au, Pt, Ti, and Rh. Preferably, the first p-type contact electrode 202 is NiAu, and the metal thicknesses are 30 nm / 30 nm, respectively.

[0035] Step 7: The first p-type contact electrode 202 is annealed at a low temperature for a long time in an air atmosphere to form a p-type ohmic contact.

[0036] Furthermore, in step 7, the annealing temperature is 400° C.-700° C., and the annealing time is 60s-1200s. Preferably, the annealing temperature is 500° C., and the annealing time is 400s.

[0037] Step 8: Based on the structure of step 7, use photoresist to pattern the second n-type electrode 301 and the second p-type electrode 302, and simultaneously evaporate the second n-type electrode 301 and the second p-type electrode 302 on the original position of the first n-type contact electrode 201 and on the first p-type contact electrode 202.

[0038] Furthermore, in step 8, the second n-type electrode 301 and the second p-type electrode 302 can play the role of thickening the electrodes and expanding the current. Their line width and shape are respectively consistent with the original first n-type contact electrode 201 and the first p-type contact electrode 202. The second n-type electrode 301 and the second p-type electrode 302 are composed of one or more metals selected from Cr, Al, Ti, Au, Ni, and Pt. Preferably, the second n-type electrode 301 and the second p-type electrode 302 are CrAlTiAu, and the thickness of each layer is 50nm / 500nm / 50nm / 50nm. Example

[0039] This embodiment provides a low-roughness n-type electrode LED chip, including a substrate 101, an AlN buffer layer 102, an n-type semiconductor layer 103, a quantum well layer 104, a p-type semiconductor layer 105, a first n-type contact electrode 201, a first p-type contact electrode 202, a second n-type electrode 301 and a second p-type electrode 302. The AlN buffer layer 102 is grown on the substrate 101, the n-type semiconductor layer 103 is grown on the AlN buffer layer 102, the quantum well layer 104 is grown on the n-type semiconductor layer 103, and the p-type semiconductor layer 105 is grown on the quantum well layer 104. The p-type semiconductor layer 105 is etched from top to bottom to the n-type semiconductor layer 103 to form an n-type semiconductor groove. The first n-type contact electrode 201 is grown on the n-type semiconductor groove, the first p-type contact electrode 202 is grown on the p-type semiconductor layer 105 , the second n-type electrode 301 is grown where the first n-type contact electrode 201 is removed, and the second p-type electrode 302 is grown on the first p-type contact electrode 202 .

[0040] Taking a 20mil*20mil chip as an example, the control example is a chip prepared by annealing and alloying the n-type contact electrode without removing the electrode, and the embodiment is a chip prepared by the method of embodiment 1 of the present invention. Figure 4 The appearance of the n-type contact electrode after annealing and alloying is relatively rough. Figure 5 This is the appearance of the first n-type contact electrode 201 after wet etching in the embodiment. The overall corrosion is relatively uniform, as shown in Table 1. The metal corrosion residue of the embodiment is characterized by SEM-EDS. Figure 6 The morphologies of the second n-type electrode 301 after vapor deposition of the control example and the embodiment are shown. The control example in the left figure is an n-type electrode prepared without etching the n-type contact electrode, and the n-type electrode has a rough appearance. The embodiment in the right figure is a second n-type electrode 301 prepared after wet etching the first n-type contact electrode 201, and the second n-type electrode 301 has a smooth appearance.

[0041] Table 1 Metal corrosion residues of the examples Elt. Line Intensity(c / s) Atomic% AtomicRatio Conc. Units Error2-sig MDL3-sig C Ka 9.62 1.021 0.3263 0.367 wt.% 0.077 0.228 N Ka 410.09 31.154 9.9597 13.065 wt.% 0.123 0.205 O Ka 88.93 3.128 1.0000 1.498 wt.% 0.051 0.137 Mg Ka 85.21 0.884 0.2826 0.643 wt.% 0.031 0.088 Al Ka 4,230.61 38.704 12.3734 31.268 wt.% 0.082 0.085 Si Ka 6.91 0.067 0.0215 0.057 wt.% 0.029 0.089 Ti Ka 3.13 0.024 0.0077 0.035 wt.% 0.031 0.094 Cr Ka 5.18 0.048 0.0154 0.075 wt.% 0.036 0.110 Ni Ka 2.36 0.037 0.0117 0.065 wt.% 0.055 0.168 Ga Ka 514.26 24.701 7.8968 51.566 wt.% 0.400 0.515 Au La 1.74 0.231 0.0738 1.361 wt.% 1.261 3.827 Total 100.000 100.000 Wt.% When the n-type contact electrode of the control example is rough and forms a large bulge, the chip leakage is dead. The chip on the wafer is tested with a spot tester. VF1 (turn-on voltage: representing the forward leakage situation) is tested at a current of 1μA, and IR (reverse current: representing the reverse leakage situation) is tested at a voltage of -5V. The test results are as follows Figure 7 、 Figure 8 As shown, the VF1 and IR of the chip with a large n-type contact electrode protrusion (usually appearing on the edge of the wafer or the entire wafer) are both NG, the chip VF1 is less than 4V, and the IR is greater than 0.05μA. Figure 9 、 Figure 10 The VF1 and IR yields of the embodiment are better.

[0042] The above only describes in detail the preferred embodiments of the present invention, but the present invention is not limited to the above embodiments. Various changes can be made within the knowledge of ordinary technicians in this field without departing from the purpose of the present invention, and various changes should be included in the scope of protection of the present invention.

Claims

1. A method for preparing a low-roughness n-type electrode LED chip, characterized in that: The following steps are involved: S1, growing an AlN buffer layer (102), an n-type semiconductor layer (103), a quantum well layer (104), and a p-type semiconductor layer (105) on a substrate (101) in order from bottom to top to obtain an epitaxial wafer structure; S2, patterning an n-type semiconductor layer groove on the p-type semiconductor layer (105) using photoresist, and etching from top to bottom to the n-type semiconductor layer (103), thereby preparing an n-type semiconductor groove; S3, patterning a first n-type contact electrode (201) on the n-type semiconductor groove using photoresist, and vapor-depositing the first n-type contact electrode (201) on the n-type semiconductor layer (103); S4, performing high-temperature rapid annealing on the first n-type contact electrode (201) in a nitrogen atmosphere to form an n-type ohmic contact; S5, using the first n-type contact electrode (201) as a sacrificial electrode and removing it by etching with a wet etching solution; S6, patterning a first p-type contact electrode (202) on the p-type semiconductor layer (105) using photoresist, and vapor-depositing the first p-type contact electrode (202) on the p-type semiconductor layer (105); S7, annealing the first p-type contact electrode (202) at a low temperature for a long time in an air atmosphere to form a p-type ohmic contact; S8. Using photoresist to pattern the second n-type electrode (301) at the position where the first n-type contact electrode (201) is removed, and using photoresist to pattern the second p-type electrode (302) on the first p-type contact electrode (202), and simultaneously vapor-depositing the second n-type electrode (301) and the second p-type electrode (302).

2. The method for preparing a low-roughness n-type electrode LED chip according to claim 1, characterized in that: The depth of the groove of the n-type semiconductor layer in S2 is 400nm-900nm.

3. The method for preparing a low-roughness n-type electrode LED chip according to claim 1, wherein: The first n-type contact electrode (201) in S3 is made of one or more metals selected from the group consisting of Cr, Al, Ti, Au, Ni, and Pt.

4. The method for preparing a low-roughness n-type electrode LED chip according to claim 1, characterized in that: The annealing temperature in S4 is 600° C.-1000° C., and the annealing time is 30s-400s.

5. The method for preparing a low-roughness n-type electrode LED chip according to claim 1, wherein: The wet etching solution in S5 is one or more of nitric acid, hydrochloric acid, aqua regia, buffered oxide etching solution, phosphoric acid, gold etching solution, hydrofluoric acid, sulfuric acid, hydrogen peroxide, chromium etching solution, and aluminum etching solution.

6. The method for preparing a low-roughness n-type electrode LED chip according to claim 1, characterized in that: The first p-type contact electrode (202) in S6 is made of one or more metals selected from the group consisting of Ni, Au, Pt, Ti, and Rh.

7. The method for preparing a low-roughness n-type electrode LED chip according to claim 1, characterized in that: The annealing temperature in S7 is 400° C.-700° C., and the annealing time is 60s-1200s.

8. The method for preparing a low-roughness n-type electrode LED chip according to claim 1, characterized in that: In the S8, the second n-type electrode (301) has the same line width and shape as the first n-type contact electrode (201), and the second p-type electrode (302) has the same line width and shape as the first p-type contact electrode (202).

9. The method for preparing a low-roughness n-type electrode LED chip according to claim 1, wherein: The second n-type electrode (301) and the second p-type electrode (302) in S8 are both made of one or more metals selected from the group consisting of Cr, Al, Ti, Au, Ni, and Pt.

10. A low-roughness n-type electrode LED chip, characterized by: The invention comprises a substrate (101), an AlN buffer layer (102), an n-type semiconductor layer (103), a quantum well layer (104), a p-type semiconductor layer (105), a first n-type contact electrode (201), a first p-type contact electrode (202), a second n-type electrode (301) and a second p-type electrode (302), wherein the AlN buffer layer (102) is grown on the substrate (101), the n-type semiconductor layer (103) is grown on the AlN buffer layer (102), the quantum well layer (104) is grown on the n-type semiconductor layer (103), and the p-type semiconductor layer (105) is grown on the substrate (101). On the quantum well layer (104), the p-type semiconductor layer (105) is etched from top to bottom to the n-type semiconductor layer (103), forming an n-type semiconductor groove; the first n-type contact electrode (201) is grown on the n-type semiconductor groove, the first p-type contact electrode (202) is grown on the p-type semiconductor layer (105), the first n-type contact electrode (201) is removed by etching with a wet etching solution, the second n-type electrode (301) is grown at the position where the first n-type contact electrode (201) is removed, and the second p-type electrode (302) is grown on the first p-type contact electrode (202).

Images