Preparation method of low-roughness n-type electrode LED chip and chip

Abstract

The present application belongs to the technical field of LED chip, and particularly relates to a preparation method of low-roughness n-type electrode LED chip, which takes the conventional first n-type contact electrode of an AlGaN ultraviolet LED chip as a sacrificial electrode, forms an n-type ohmic contact through high-temperature annealing and alloying of the first n-type contact electrode, at this time, the potential barrier of the epitaxial wafer has been formed, the first n-type contact electrode is removed by using a wet etching method, and then a second n-type electrode with a suitable work function is evaporated, which simultaneously plays a role of thickening the electrode and expanding the current, and excellent appearance and voltage of the second n-type electrode can be obtained. The present application can effectively solve the appearance defect, yield loss and reliability problem caused by the roughness after high-temperature annealing and alloying of the first n-type contact electrode.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of LED chips, and particularly relates to a low-roughness n-type electrode LED chip and a preparation method thereof. BACKGROUND

[0002] The conventional n-type contact electrode of an AlGaN ultraviolet LED chip, such as CrAlTiAu, TiAlTiAu, etc., generally contains Al metal. In the process of annealing and alloying to form an ohmic contact, Al is in a molten state and is easy to form particulate matters such as AlAu2 or AlAu4, thereby increasing the roughness of the surface of the n-type ohmic contact electrode. The rough n-type contact electrode will further cause metal electromigration, affecting the reliability of the device. Moreover, the rough electrode has color difference in the warehouse inspection of the chip, and has to be removed, which greatly increases the workload of the post-process inspection of the chip and causes loss of yield. Especially when the n-type contact electrode is rough and forms a large particle protrusion, the passivation layer on the electrode cannot wrap it, so that the n-type electrode is connected with the p-pad electrode, causing the chip to leak and die, which seriously affects the photoelectric performance and yield of the chip. SUMMARY

[0003] In view of the technical problem that the traditional rough n-type contact electrode will further cause metal electromigration and affect the reliability of the device, the application provides a low-roughness n-type electrode LED chip and a preparation method thereof.

[0004] To solve the above technical problem, the technical scheme adopted by the application is as follows:

[0005] A preparation method of a low-roughness n-type electrode LED chip, comprising the following steps:

[0006] S1, growing an AlN buffer layer, an n-type semiconductor layer, a quantum well layer and a p-type semiconductor layer on a substrate in sequence from bottom to top to prepare an epitaxial wafer structure;

[0007] S2, patterning an n-type semiconductor layer groove on the p-type semiconductor layer by using a photoresist, and etching from top to bottom to the n-type semiconductor layer to prepare an n-type semiconductor groove;

[0008] S3, patterning a first n-type contact electrode on the n-type semiconductor groove by using a photoresist, and evaporating the first n-type contact electrode on the n-type semiconductor layer;

[0009] S4, performing high-temperature rapid annealing on the first n-type contact electrode in a nitrogen atmosphere to form an n-type ohmic contact;

[0010] S5, using a wet etching solution to etch and remove the first n-type contact electrode as a sacrificial electrode;

[0011] S6, patterning the first p-type contact electrode on the p-type semiconductor layer using photoresist, and evaporating the first p-type contact electrode on the p-type semiconductor layer;

[0012] S7, annealing the first p-type contact electrode in an air atmosphere at a low temperature for a long time to form a p-type ohmic contact;

[0013] S8, patterning the second n-type electrode and the second p-type electrode on the first p-type contact electrode using photoresist, and evaporating the second n-type electrode and the second p-type electrode respectively.

[0014] The depth of the n-type semiconductor layer groove in S2 is 400-900 nm.

[0015] The first n-type contact electrode in S3 is composed of one or more of Cr, Al, Ti, Au, Ni, and Pt.

[0016] The annealing temperature in S4 is 600-1000℃, and the annealing time is 30-400 s.

[0017] The wet etching solution in S5 is one or more of nitric acid, hydrochloric acid, aqua regia, buffer oxide etching solution, phosphoric acid, gold etching solution, hydrofluoric acid, sulfuric acid, hydrogen peroxide, chromium etching solution, and aluminum etching solution.

[0018] The first p-type contact electrode in S6 is composed of one or more of Ni, Au, Pt, Ti, and Rh.

[0019] The annealing temperature in S7 is 400-700℃, and the annealing time is 60-1200 s.

[0020] The line width and shape of the second n-type electrode are consistent with those of the first n-type contact electrode, and the line width and shape of the second p-type electrode are consistent with those of the first p-type contact electrode.

[0021] The second n-type electrode and the second p-type electrode in S8 are composed of one or more of Cr, Al, Ti, Au, Ni, and Pt.

[0022] The low-roughness n-type electrode LED chip comprises a substrate, an AlN buffer layer, an n-type semiconductor layer, a quantum well layer, a p-type semiconductor layer, a first n-type contact electrode, a first p-type contact electrode, a second n-type electrode and a second p-type electrode, the AlN buffer layer is grown on the substrate, the n-type semiconductor layer is grown on the AlN buffer layer, the quantum well layer is grown on the n-type semiconductor layer, the p-type semiconductor layer is grown on the quantum well layer, the n-type semiconductor layer is etched from top to bottom to form an n-type semiconductor groove by the p-type semiconductor layer; the first n-type contact electrode is grown on the n-type semiconductor groove, the first p-type contact electrode is grown on the p-type semiconductor layer, the first n-type contact electrode is removed by etching with a wet etching solution, the second n-type electrode is grown on the position where the first n-type contact electrode is removed, and the second p-type electrode is grown on the first p-type contact electrode.

[0023] Compared with the prior art, the present application has the beneficial effects that:

[0024] In the present application, the conventional first n-type contact electrode of the AlGaN ultraviolet LED chip is used as a sacrificial electrode, an n-type ohmic contact is formed by high-temperature annealing and alloying of the first n-type contact electrode, at this time, the epitaxial wafer barrier has been formed, the first n-type contact electrode is removed by wet etching, and then a second n-type electrode with a suitable work function is evaporated, which simultaneously plays a role of thickening the electrode and current expansion, and excellent appearance and voltage of the second n-type electrode can be obtained. BRIEF DESCRIPTION OF DRAWINGS

[0025] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the following embodiment or prior art description will be briefly introduced. Obviously, the drawings in the following description are only exemplary, and those skilled in the art can also obtain other implementation drawings according to the provided drawings without creating any creative labor.

[0026] The structures, proportions, sizes, etc. shown in the specification are only used to cooperate with the content disclosed in the specification, to be understood and read by those skilled in the art, and do not define the limiting conditions for the implementation of the present application, so they do not have technical substantive significance. Any modification of the structure, change of the proportion relationship or adjustment of the size, without affecting the effects and purposes that can be achieved by the present application, should still fall within the scope of the technical content disclosed by the present application.

[0027] Figure 1 The present application is an epitaxial wafer structure schematic diagram;

[0028] Figure 2A schematic view of the first n-type contact electrode of the present application;

[0029] Figure 3 A schematic view of the second n-type electrode and the second p-type electrode of the present application;

[0030] Figure 4 An appearance morphology diagram of the n-type contact electrode of the control example after annealing and alloying;

[0031] Figure 5 An appearance morphology diagram of the first n-type contact electrode of the present application after wet etching;

[0032] Figure 6 An appearance morphology comparison diagram of the second n-type electrode of the control example and the example after evaporation;

[0033] Figure 7 A mapping diagram of the control example VF1;

[0034] Figure 8 A mapping diagram of the control example IR;

[0035] Figure 9 A mapping diagram of the example VF1 of the present application;

[0036] Figure 10 A mapping diagram of the example IR of the present application.

[0037] Wherein, 101 is a substrate, 102 is an AlN layer, 103 is an n-type semiconductor layer, 104 is a quantum well layer, 105 is a p-type semiconductor layer, 201 is a first n-type contact electrode, 202 is a first p-type contact electrode, 301 is a second n-type electrode, and 302 is a second p-type electrode. DETAILED DESCRIPTION

[0038] In order to make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme of the embodiments of the present application will be described clearly and completely below. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. These descriptions are only for further explaining the features and advantages of the present application, but not for limiting the claims of the present application. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without creative work are within the protection scope of the present application.

[0039] The specific embodiments of the present application will be further described in detail below in combination with the drawings and the embodiments. The following embodiments are used to illustrate the present application, but not to limit the scope of the present application.

[0040] The terms "first", "second", "third", etc. are used only for descriptive purposes and do not connote or imply relative importance or a number of the indicated technical features. Thus, features defined with "first", "second" or "third" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise specified.

[0041] In the description of the present application, it should be noted that unless otherwise explicitly specified and limited, the terms "mounting", "connecting", "connection" should be understood broadly, for example, it can be fixed connection, or detachable connection, or integral connection; it can be mechanical connection, or electrical connection; it can be direct connection, or indirect connection through intermediate medium, or internal communication of two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances. Embodiment

[0042] The embodiment provides a preparation method of a low-roughness n-type electrode LED chip, comprising the following steps:

[0043] Step 1: sequentially preparing an AlN buffer layer 102, an n-type semiconductor layer 103, a quantum well layer 104 and a p-type semiconductor layer 105 on a substrate 101 from bottom to top, to obtain an epitaxial wafer structure.

[0044] Step 2: on the basis of the structure in step 1, patterning the n-type semiconductor layer groove by using photoresist, and etching from top to bottom to the n-type semiconductor layer 103 by using ICP dry etching, to obtain an n-type semiconductor groove.

[0045] Further, in step 2, the depth of the n-type semiconductor layer groove is 400nm-900nm, preferably, the etching depth is 650nm.

[0046] Step 3: on the basis of the structure in step 2, patterning the first n-type contact electrode 201 by using photoresist, and evaporating the first n-type contact electrode 201 on the n-type semiconductor layer 103 by using a vacuum metal evaporator.

[0047] Further, in step 3, the first n-type contact electrode 201 is composed of one or more of Cr, Al, Ti, Au, Ni and Pt, preferably, the first n-type contact electrode 201 is CrAlNiAuTi, and the thickness of each layer of metal is 20nm / 100nm / 10nm / 50nm / 10nm.

[0048] Step 4: the first n-type contact electrode 201 is subjected to high-temperature rapid annealing in a nitrogen atmosphere to form an n-type ohmic contact.

[0049] Further, in step 4, the annealing temperature is 600-1000℃, and the annealing time is 30s-400s. Preferably, the annealing temperature is 900℃, and the annealing time is 30s.

[0050] In step 5, the first n-type contact electrode 201 is removed by a wet etching solution as a sacrificial electrode based on the structure of step 4.

[0051] The wet etching solution is one or more of nitric acid, hydrochloric acid, aqua regia, BOE (buffered oxide etch), phosphoric acid, gold etching solution, hydrofluoric acid, sulfuric acid, hydrogen peroxide, chromium etching solution, and aluminum etching solution.

[0052] Preferably, the wafer is first placed in BOE (buffered oxide etch) for 10 minutes, then rinsed with ultrapure water in a fast drain and flush tank for 3 cycles, then placed in aqua regia for 20 minutes, then rinsed with ultrapure water in a fast drain and flush tank for 3 cycles, and finally placed in a chromium etching solution for 20 minutes, then rinsed with ultrapure water in a fast drain and flush tank for 5 cycles, and then dried in a spin dryer.

[0053] In step 6, the first p-type contact electrode 202 is patterned using photoresist based on the structure of step 5, and the first p-type contact electrode 202 is evaporated on the p-type semiconductor layer 105 using a vacuum metal evaporator.

[0054] Further, in step 6, the first p-type contact electrode 202 is composed of one or more of Ni, Au, Pt, Ti, and Rh, and preferably the first p-type contact electrode 202 is NiAu with a metal thickness of 30nm / 30nm.

[0055] In step 7, the first p-type contact electrode 202 is annealed at a low temperature for a long time in an air atmosphere to form a p-type ohmic contact.

[0056] Further, in step 7, the annealing temperature is 400-700℃, and the annealing time is 60s-1200s. Preferably, the annealing temperature is 500℃, and the annealing time is 400s.

[0057] In step 8, the second n-type electrode 301 and the second p-type electrode 302 are patterned using photoresist based on the structure of step 7, and the second n-type electrode 301 and the second p-type electrode 302 are simultaneously evaporated on the original positions of the first n-type contact electrode 201 and the first p-type contact electrode 202, respectively.

[0058] Further, in step 8, the second n-type electrode 301 and the second p-type electrode 302 can play the role of thickening electrode and current expansion, the line width and shape thereof are consistent with the original first n-type contact electrode 201 and the first p-type contact electrode 202 respectively, the second n-type electrode 301 and the second p-type electrode 302 are composed of one or more of Cr, Al, Ti, Au, Ni, Pt, and preferably the second n-type electrode 301 and the second p-type electrode 302 are CrAlTiAu, and the thickness of each layer is 50nm / 500nm / 50nm / 50nm. Embodiment

[0059] The embodiment provides a low-roughness n-type electrode LED chip, which comprises a substrate 101, an AlN buffer layer 102, an n-type semiconductor layer 103, a quantum well layer 104, a p-type semiconductor layer 105, a first n-type contact electrode 201, a first p-type contact electrode 202, a second n-type electrode 301 and a second p-type electrode 302, the AlN buffer layer 102 is grown on the substrate 101, the n-type semiconductor layer 103 is grown on the AlN buffer layer 102, the quantum well layer 104 is grown on the n-type semiconductor layer 103, the p-type semiconductor layer 105 is grown on the quantum well layer 104, the n-type semiconductor groove is formed by etching from top to bottom of the p-type semiconductor layer 105 to the n-type semiconductor layer 103, the first n-type contact electrode 201 is grown on the n-type semiconductor groove, the first p-type contact electrode 202 is grown on the p-type semiconductor layer 105, the second n-type electrode 301 is grown on the position where the first n-type contact electrode 201 is removed, and the second p-type electrode 302 is grown on the first p-type contact electrode 202.

[0060] Taking a 20mil*20mil size chip as an example, a comparative example is a chip prepared without removing operation after the n-type contact electrode is annealed and alloyed, and an embodiment is a chip prepared by the method of the embodiment one of the application, Figure 4 The appearance of the n-type contact electrode after annealing and alloying in the comparative example is rough, Figure 5 The appearance of the first n-type contact electrode 201 after wet etching in the embodiment is shown in Table 1, and the metal corrosion residue of the embodiment is characterized by SEM-EDS. Figure 6 The appearance of the second n-type electrode 301 after evaporation in the comparative example and the embodiment is shown, wherein the left graph of the comparative example is an n-type electrode prepared without n-type contact electrode etching, and the appearance of the n-type electrode is rough; the right graph of the embodiment is the second n-type electrode 301 prepared after the first n-type contact electrode 201 is etched by wet etching, and the appearance of the second n-type electrode 301 is smooth.

[0061] Table 1 Metal corrosion residue table of the embodiment

[0062] Elt. Line Intensity(c / s) Atomic% AtomicRatio Conc. Units Error2-sig MDL3-sig C Ka 9.62 1.021 0.3263 0.367 wt.% 0.077 0.228 N Ka 410.09 31.154 9.9597 13.065 wt.% 0.123 0.205 O Ka 88.93 3.128 1.0000 1.498 wt.% 0.051 0.137 Mg Ka 85.21 0.884 0.2826 0.643 wt.% 0.031 0.088 Al Ka 4,230.61 38.704 12.3734 31.268 wt.% 0.082 0.085 Si Ka 6.91 0.067 0.0215 0.057 wt.% 0.029 0.089 Ti Ka 3.13 0.024 0.0077 0.035 wt.% 0.031 0.094 Cr Ka 5.18 0.048 0.0154 0.075 wt.% 0.036 0.110 Ni Ka 2.36 0.037 0.0117 0.065 wt.% 0.055 0.168 Ga Ka 514.26 24.701 7.8968 51.566 wt.% 0.400 0.515 Au La 1.74 0.231 0.0738 1.361 wt.% 1.261 3.827 Total 100.000 100.000 Wt.%

[0063] When the n-type contact electrode of the comparative example is roughened to form large protrusions, the chip will leak current and die. The chips on the wafer are tested by a point tester, VF1 (turn-on voltage: indicative of forward current leakage) is tested at a current of 1 μA, and IR (reverse current: indicative of reverse current leakage) is tested at a voltage of -5 V. The test results are shown in Table 1. Figure 7 、 Figure 8 As shown in Table 1, the chips with n-type contact electrodes forming large protrusions (usually appearing at the wafer edge or appearing on the whole wafer) have NG VF1 and IR, the chip VF1 is less than 4 V, and the IR is greater than 0.05 μA. Figure 9 、 Figure 10 The VF1 and IR yields of the embodiments in Table 2 are better.

[0064] The above only describes the preferred embodiments of the present application in detail, but the present application is not limited to the above-described embodiments, and various changes can be made within the knowledge of those skilled in the art without departing from the spirit of the present application, and all the changes shall be included in the protection scope of the present application.

Claims

1. A method for fabricating a low-roughness n-type electrode LED chip, characterized in that, The method comprises the following steps: S1, growing an AlN buffer layer (102), an n-type semiconductor layer (103), a quantum well layer (104), and a p-type semiconductor layer (105) on a substrate (101) in sequence from bottom to top to obtain an epitaxial wafer structure; S2, patterning an n-type semiconductor layer recess on the p-type semiconductor layer (105) by using a photoresist, and etching from top to bottom to the n-type semiconductor layer (103) to obtain an n-type semiconductor recess; S3, patterning a first n-type contact electrode (201) on the n-type semiconductor recess by using a photoresist, and evaporating the first n-type contact electrode (201) on the n-type semiconductor layer (103); S4, performing high-temperature rapid annealing on the first n-type contact electrode (201) in a nitrogen atmosphere to form an n-type ohmic contact; the annealing temperature in S4 is 600-1000 DEG C, and the annealing time is 30-400 s; S5, removing the first n-type contact electrode (201) by using a wet etching solution as a sacrificial electrode; S6, patterning a first p-type contact electrode (202) on the p-type semiconductor layer (105) by using a photoresist, and evaporating the first p-type contact electrode (202) on the p-type semiconductor layer (105); S7, performing low-temperature long-time annealing on the first p-type contact electrode (202) in an air atmosphere to form a p-type ohmic contact; the annealing temperature in S7 is 400-700 DEG C, and the annealing time is 60-1200 s; S8, patterning a second n-type electrode (301) on the position where the first n-type contact electrode (201) is removed by using a photoresist, patterning a second p-type electrode (302) on the first p-type contact electrode (202) by using a photoresist, and evaporating the second n-type electrode (301) and the second p-type electrode (302) at the same time.

2. The method of claim 1, wherein the method further comprises: forming a low roughness n-type electrode on the n-type layer. The depth of the n-type semiconductor layer recess in S2 is 400-900 nm.

3. The method of claim 1, wherein the n-type electrode LED chip has a low roughness. The first n-type contact electrode (201) in S3 is composed of one or more of Cr, Al, Ti, Au, Ni, and Pt.

4. The method of claim 1, wherein the n-type electrode LED chip has a low roughness. The wet etching solution in S5 is one or more of nitric acid, hydrochloric acid, aqua regia, a buffer oxide etching solution, phosphoric acid, a gold etching solution, hydrofluoric acid, sulfuric acid, hydrogen peroxide, a chromium etching solution, and an aluminum etching solution.

5. The method of claim 1, wherein the n-type electrode LED chip has a low roughness. The first p-type contact electrode (202) in S6 is composed of one or more of Ni, Au, Pt, Ti, and Rh.

6. The method of claim 1, wherein the n-type electrode LED chip has a low roughness. The line width and shape of the second n-type electrode (301) are consistent with those of the first n-type contact electrode (201), and the line width and shape of the second p-type electrode (302) are consistent with those of the first p-type contact electrode (202).

7. The method of claim 1, wherein the n-type electrode LED chip has a low roughness. The second n-type electrode (301) and the second p-type electrode (302) in S8 are each composed of one or more of Cr, Al, Ti, Au, Ni, and Pt.

8. A low-roughness n-type electrode LED chip, characterized by: The application relates to a semiconductor device, which comprises a substrate (101), an AlN buffer layer (102), an n-type semiconductor layer (103), a quantum well layer (104), a p-type semiconductor layer (105), a first n-type contact electrode (201), a first p-type contact electrode (202), a second n-type electrode (301) and a second p-type electrode (302), wherein the AlN buffer layer (102) is grown on the substrate (101), the n-type semiconductor layer (103) is grown on the AlN buffer layer (102), the quantum well layer (104) is grown on the n-type semiconductor layer (103), the p-type semiconductor layer (105) is grown on the quantum well layer (104), the n-type semiconductor layer (103) is etched from top to bottom to form an n-type semiconductor groove, the first n-type contact electrode (201) is grown on the n-type semiconductor groove, the first p-type contact electrode (202) is grown on the p-type semiconductor layer (105), the first n-type contact electrode (201) is removed by wet etching solution, the second n-type electrode (301) is grown on the position where the first n-type contact electrode (201) is removed, and the second p-type electrode (302) is grown on the first p-type contact electrode (202).

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