Power amplification system, power amplification method, and digital pre-distortion circuit

Abstract

A power amplification system (7) is provided with: a power amplifier (2); an output switching circuit (30) configured so as to selectively output at least one of the three or more discrete voltages to the power amplifier (2); and a DPD circuit (71) configured so as to pre-distort an input signal of the power amplifier (2), the output switching circuit (30) having a first mode in which at least one of a first subset of the three or more discrete voltages is selectively output, and a second mode in which at least one of a second subset of the three or more discrete voltages is selectively output. The average voltage of the first subset is higher than the average voltage of the second subset, the DPD circuit (71) predistorts an input signal of the power amplifier (2) using a first parameter in a first mathematical model in a first mode, uses a second parameter in a second mathematical model, or uses a third parameter in the first mathematical model, an input signal of a power amplifier (2) is pre-distorted.

Description

Technical Field

[0001] The invention relates to a power amplification system, a power amplification method and a digital predistortion circuit. Background Art

[0002] In recent years, improvements in power added efficiency have been achieved by applying tracking technology to power amplifier circuits. Patent Document 1 discloses a tracker circuit for digital envelope tracking (D-ET) that supplies a power supply voltage that varies over time at multiple discrete levels (hereinafter referred to as multiple discrete voltages). Furthermore, Patent Document 2 discloses a tracker circuit for symbol power tracking (SPT) that supplies multiple discrete voltages.

[0003] Patent Document 1: U.S. Patent No. 8,829,993

[0004] Patent Document 2: U.S. Patent No. 10,686,407

[0005] When supplying multiple discrete voltages to a power amplifier, digital pre-distortion (DPD) is sometimes used to reduce the nonlinear distortion caused by the power amplifier operating in a nonlinear region. DPD predistorts the input signal to the power amplifier to cancel out the nonlinear distortion generated by the power amplifier. In this case, it is desirable to reduce nonlinear distortion to a greater extent with a lower computational load. In other words, it is desirable to effectively improve the quality of the transmitted signal while suppressing an increase in power consumption. Summary of the Invention

[0006] Therefore, the present invention provides a power amplification system, a power amplification method, and a digital predistortion circuit capable of effectively improving the quality of a transmission signal while suppressing an increase in power consumption.

[0007] A power amplifier system according to one embodiment of the present invention includes: a power amplifier; an output switching circuit configured to selectively output at least one of three or more discrete voltages to the power amplifier; and a digital predistortion circuit configured to predistort an input signal of the power amplifier, wherein the output switching circuit has a first mode for selectively outputting at least one of a first subset of the three or more discrete voltages, and a second mode for selectively outputting at least one of a second subset of the three or more discrete voltages, wherein the average voltage of the first subset is higher than the average voltage of the second subset, and wherein the digital predistortion circuit predistorts the input signal of the power amplifier using first parameters in a first mathematical model for digital predistortion in the first mode, and predistorts the input signal of the power amplifier using second parameters in a second mathematical model for digital predistortion in the second mode, or using third parameters in the first mathematical model for digital predistortion.

[0008] A power amplification method according to one embodiment of the present invention selectively supplies at least one of a first subset of three or more discrete voltages to a power amplifier, predistorts a first input signal of the power amplifier using a first parameter in a first mathematical model for digital predistortion, amplifies the predistorted first input signal using the first subset of the three or more discrete voltages, selectively supplies at least one of a second subset of three or more discrete voltages to the power amplifier, predistorts the second input signal of the power amplifier using a second parameter in a second mathematical model for digital predistortion or using a third parameter in the first mathematical model, and amplifies the predistorted second input signal using the second subset of the three or more discrete voltages.

[0009] A digital predistortion circuit according to one embodiment of the present invention is configured to predistort an input signal of a power amplifier. In a first mode in which at least one of a first subset of three or more discrete voltages is selectively supplied to the power amplifier, the input signal of the power amplifier is predistorted using first parameters in a first mathematical model for digital predistortion. In a second mode in which at least one of a second subset of three or more discrete voltages is selectively supplied to the power amplifier, the input signal of the power amplifier is predistorted using second parameters in a second mathematical model for digital predistortion, or using third parameters in the first mathematical model. The average voltage of the first subset is higher than the average voltage of the second subset.

[0010] According to the power amplifier system and the like according to one aspect of the present invention, nonlinear distortion can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1A This is a graph showing an example of the transition of the power supply voltage in the APT (Average Power Tracking) mode.

[0012] Figure 1B This is a graph showing an example of the transition of the power supply voltage in the A-ET (Analog Envelope Tracking) mode.

[0013] Figure 1C This is a graph showing an example of the transition of the power supply voltage in the D-ET mode.

[0014] Figure 2 It is a circuit configuration diagram of a communication device according to an embodiment.

[0015] Figure 3 This is a circuit configuration diagram of a tracker circuit according to an embodiment.

[0016] Figure 4 1 is a flowchart showing a power amplification method according to an embodiment. DETAILED DESCRIPTION

[0017] The following describes embodiments of the present invention in detail using the accompanying drawings. The embodiments described below are generally or specifically examples. The values, shapes, materials, components, configurations of components, and connection methods shown in the following embodiments are examples and do not limit the present invention.

[0018] In addition, the figures are schematic diagrams that have been appropriately emphasized, omitted, or adjusted in ratio to illustrate the present invention, and are not necessarily strictly illustrated. Actual shapes, positional relationships, and ratios may differ. In the figures, substantially identical structures may be denoted by the same reference numerals, and repeated descriptions may be omitted or simplified.

[0019] In the circuit structure of the present invention, "connection" includes not only direct connection via connection terminals and / or wiring conductors, but also electrical connection via other circuit elements. "Direct connection" means direct connection via connection terminals and / or wiring conductors without passing through other circuit elements. "C is connected between A and B" means that one end of C is connected to A, and the other end of C is connected to B, and that they are arranged in series on the path connecting A and B. "The path connecting A and B" means the path formed by the conductor that electrically connects A and B.

[0020] In the following description, a "terminal" refers to a point where a conductor within an element ends. Furthermore, if the impedance of the conductors between elements is sufficiently low, a terminal can be interpreted not only as a single point but also as any point on the conductors between elements or as the entire conductor.

[0021] In addition, statements such as "parallel" and "perpendicular" that indicate the relationship between elements, statements such as "rectangular" that indicate the shape of elements, and numerical ranges do not only have strict meanings, but also include substantially equivalent ranges, such as errors of several percent.

[0022] First, as a technology for efficiently amplifying high-frequency signals, we will explain the tracking mode, which dynamically adjusts the power supply voltage applied to the power amplifier circuit based on the passage of high-frequency signals over time. Tracking mode refers to a mode that dynamically adjusts the power supply voltage applied to the power amplifier circuit. There are several types of tracking modes, but here, we will refer to Figure 1A Figure 1 illustrates the CAPT mode, A-ET mode, and D-ET mode. Figures 1A to 1C In FIG, the horizontal axis represents time and the vertical axis represents voltage. In addition, the thick solid line represents the power supply voltage, and the thin solid line (waveform) represents the modulation wave.

[0023] Figure 1A This graph shows an example of the power supply voltage transition in APT mode. In APT mode, the power supply voltage is varied to multiple discrete voltage levels per frame based on average power. As a result, the power supply voltage signal forms a rectangular wave.

[0024] A frame is the unit that makes up a high-frequency signal (modulated wave). For example, in 5GNR (5th Generation New Radio) and LTE (Long Term Evolution), a frame consists of ten subframes, each of which contains multiple time slots, each of which consists of multiple symbols. A subframe is 1ms long, and a frame is 10ms long.

[0025] Furthermore, a mode in which the voltage level is varied in units of one frame or larger based on average power is called an APT mode, and is distinguished from a mode in which the voltage level is varied in units smaller than one frame (eg, subframe, slot, or symbol).

[0026] Figure 1B This is a graph showing an example of the transition of the power supply voltage in the A-ET mode. In the A-ET mode, the power supply voltage is continuously varied based on the envelope signal to track the envelope of the modulation wave.

[0027] The envelope signal is a signal representing the envelope of the modulated wave. The envelope value is, for example, represented by (I 2 +Q 2 ). Here, (I, Q) represents a constellation point. A constellation point is a point on a constellation diagram that represents a digitally modulated signal. For example, (I, Q) is determined by a BBIC (Baseband Integrated Circuit) based on transmission information.

[0028] Figure 1C This graph shows an example of the power supply voltage transition in D-ET mode. In D-ET mode, the power supply voltage is varied to multiple discrete voltage levels within a frame based on an envelope signal, tracking the envelope of the modulated wave. As a result, the power supply voltage signal forms a rectangular wave.

[0029] (Implementation Method)

[0030] Hereinafter, embodiments will be described.

[0031] [1.1 Circuit Structure of Communication Device 6]

[0032] First, refer to Figure 2 The circuit configuration of the communication device 6 according to this embodiment will be described. Figure 2 It is a circuit configuration diagram of the communication device 6 according to this embodiment.

[0033] also, Figure 2 This is an exemplary circuit configuration, and the communication device 6 can be implemented using any of a variety of circuit implementations and circuit technologies. Therefore, the following description of the communication device 6 should not be interpreted in a limiting sense.

[0034] The communication device 6 in this embodiment corresponds to a user equipment (UE) in a cellular network, typically a mobile phone, smartphone, tablet computer, wearable device, etc. Alternatively, the communication device 6 may be an IoT (Internet of Things) sensor device, medical / healthcare equipment, a car, an unmanned aerial vehicle (UAV), or an automated guided vehicle (AGV). Furthermore, the communication device 6 may function as a base station (BS) in a cellular network.

[0035] like Figure 2 As shown, the communication device 6 includes a tracker circuit 1, a power amplifier 2, an RFIC (Radio Frequency Integrated Circuit) 3, a BBIC 4, and an antenna 5. In addition, the power amplification system 7 includes the tracker circuit 1, the power amplifier 2, and the RFIC 3.

[0036] The tracker circuit 1 can supply a plurality of discrete voltages as the power supply voltage Vcc to the power amplifier 2 in the tracking mode. In this embodiment, the high power mode and the low power mode of the DET mode are used as the tracking mode, but the present invention is not limited thereto.

[0037] The high power mode of the D-ET is an example of the first mode and is a voltage supply mode used when the output power of the power amplifier 2 is relatively high. On the other hand, the low power mode of the D-ET is an example of the second mode and is a voltage supply mode used when the output power of the power amplifier 2 is relatively low. In the high power mode, a first subset of multiple discrete voltages is used, and in the low power mode, a second subset of multiple discrete voltages is used. In this case, the average voltage of the first subset is higher than the average voltage of the second subset. Here, the average voltage of the subset refers to the average value of the discrete voltages contained in the subset. In addition, the high power mode and the low power mode are not limited to the D-ET mode.

[0038] The power amplifier 2 is connected between the RFIC 3 and the antenna 5. The power amplifier 2 is also connected to the tracker circuit 1. The power amplifier 2 can amplify the high-frequency signal RF received from the RFIC 3 using the power supply voltage Vcc supplied from the tracker circuit 1.

[0039] RFIC 3 is an example of a signal processing circuit that processes a high-frequency signal. RFIC 3 can receive a digital IQ signal from BBIC 4 and supply a high-frequency signal RF to the power amplifier 2. The internal structure of RFIC 3 will be described later.

[0040] BBIC 4 is a baseband signal processing circuit that performs signal processing using a frequency band lower than the high-frequency signal RF. BBIC 4 digitally modulates bit sequences representing, for example, image signals for display and / or audio signals for communication via a speaker, generating digital IQ signals. These generated digital IQ signals are supplied to RFIC 3. BBIC 4 may not be included in communication device 6.

[0041] The antenna 5 transmits the high-frequency signal RF amplified by the power amplifier 2 to the outside of the communication device 6. In addition, the antenna 5 may not be included in the communication device 6.

[0042] [1.2 Internal structure of RFIC3]

[0043] Reference Figure 2The internal structure of RFIC 3 is described below. RFIC 3 includes a DPD circuit 71, a digital-to-analog converter (DAC) 72, and a quadrature modulator 73. RFIC 3 may also include a control unit (not shown) for controlling the tracker circuit 1. Furthermore, some or all of the functions of RFIC 3's control unit may be implemented externally to RFIC 3.

[0044] The DPD circuit 71 can predistort the digital IQ signal supplied from the BBIC 4 using a mathematical model for DPD. For example, the DPD circuit 71 can generate a predistorted digital IQ signal based on the digital IQ signal. The predistorted digital IQ signal is supplied to the DAC 72. Alternatively, the DPD circuit 71 can skip the DPD process. In this case, the DPD circuit 71 can supply the digital IQ signal supplied from the BBIC 4 (i.e., the non-predistorted digital IQ signal) to the DAC 72.

[0045] The DAC 72 can convert the digital IQ signal supplied from the DPD circuit 71 into an analog IQ signal. The converted analog IQ signal is supplied to the quadrature modulator 73. A conventional DAC can be used as the DAC 72, and there is no particular limitation.

[0046] The quadrature modulator 73 can generate a high-frequency signal RF by performing quadrature modulation and up-conversion on the analog IQ signal supplied from the DAC 72. The generated high-frequency signal RF is supplied to the power amplifier 2. A conventional quadrature modulator can be used as the quadrature modulator 73, and there is no particular limitation.

[0047] also, Figure 2 The circuit configuration of the RFIC 3 shown is an example and is not limited thereto. For example, some or all of the DPD circuit 71, DAC 72, and quadrature modulator 73 may not be included in the RFIC 3. For example, the DPD circuit 71 may not be included in the BBIC 4.

[0048] Here, a description is given of a mathematical model used for DPD in the DPD circuit 71. In this embodiment, as the mathematical model used for DPD, a first mathematical model having a memory effect or a second mathematical model having no memory effect can be used.

[0049] The memory effect is defined as the change in distortion of a power amplifier caused by past input signals. Therefore, the first mathematical model models not only the distortion caused by the current input signal but also the change in distortion caused by past input signals. Therefore, the first mathematical model can reduce nonlinear distortion compared to the second mathematical model, but the computational load increases.

[0050] In this embodiment, to effectively reduce nonlinear distortion, the first mathematical model and the second mathematical model are switched according to the high power mode and the low power mode. For example, when power amplifier 2 is in high power mode, the first mathematical model is used to predistort the input signal of power amplifier 2, and when power amplifier 2 is in low power mode, the second mathematical model is used to predistort the input signal of power amplifier 2.

[0051] Here, a specific example of the second mathematical model without the memory effect will be described.

[0052] [Number 1]

[0053]

[0054] x[n]:predistorted signal

[0055] r[n]:original input signal

[0056] c i :DPD coefficients

[0057] N:polynomial order

[0058] The above formula (1) is an example of a polynomial used in the second mathematical model. The mathematical model using formula (1) is called a memoryless polynomial model. In formula (1), for the current input signal r[n], the input signal is multiplied by the exponential input signal. The polynomial degree N and the DPD coefficient c i These are parameters of the memoryless polynomial model and can be predetermined through experiments and / or experience, and stored in advance in a memory (not shown) included in the RFIC 3 , for example.

[0059] In equation (1), if the polynomial degree N is increased, nonlinear distortion can be expected to be reduced, but there is a concern that the computational load will increase. In addition, since equation (1) does not take into account the memory effect, the reduction of nonlinear distortion in the memoryless polynomial model is limited.

[0060] Next, a specific example of setting the first mathematical model of the memory effect will be described.

[0061] [Number 2]

[0062]

[0063] x[n]:predistorted signal

[0064] r[n]:original input signal

[0065] c qi :DPD coefficients

[0066] Q: memory depth

[0067] N:polynomial order

[0068] The above equation (2) is an example of a polynomial used in the first mathematical model. The mathematical model using equation (2) is called a memory polynomial model (MPM). In equation (2), for each input signal r[nq] from the past Q to the current 0, the input signal is multiplied by the exponential input signal. The polynomial degree N, the memory depth Q, and the DPD coefficient c are qi These are parameters of the MPM and can be predetermined through experiments and / or experience, and stored in advance in, for example, a memory (not shown) included in the RFIC 3 .

[0069] In equation (2), if the polynomial degree N and the memory depth Q increase, nonlinear distortion can be expected to decrease. However, there is a concern about an increase in the number of parameters, an increase in the computational load, and a decrease in convergence when determining the DPD coefficient cqi.

[0070] [Number 3]

[0071]

[0072] x[n]:predistorted signal

[0073] r[n]:original input signal

[0074] c qi , d qmi , e qmi :DPD coefficients

[0075] Q: sync memory depth

[0076] N:sync order

[0077] Q d :lag memory depth

[0078] M d :maximum lag

[0079] N d :lag order

[0080] Q e :lead memory depth

[0081] M e :maximum lead

[0082] N e :lead order

[0083] The above formula (3) is an example of a polynomial used in the first mathematical model. The mathematical model using formula (3) is called a generalized memory polynomial model (GMP). In formula (3), the sync term (3-1) is combined with the Lag term (3-2) and the Lead term (3-3). The sync term (3-1) is the same as the term of formula (2) used for MPM. In the Lag term (3-2), the input signal is multiplied by the past input signal that has been indexed. In the Lead term (3-3), the input signal is multiplied by the future input signal that has been indexed. The order of each term N, N d and N e , memory depth Q, and DPD coefficient c qi d qmi and e qmi These are parameters of GMP and can be predetermined through experiments and / or experience, and stored in advance in, for example, a memory (not shown) included in the RFIC 3 .

[0084] In formula (3), if the memory depth of each item is Q, Q d , Q e and cross width M d 、M e If the value is increased, the nonlinear distortion can be expected to decrease, but the number of parameters increases, the calculation load increases, and the DPD coefficient c increases. qi d qmi and e qmi There is concern about decreased convergence during decision making.

[0085] The effect of reducing nonlinear distortion increases in the order of the memoryless polynomial model, MPM, and GMP, but the number of parameters increases, and the computational load (i.e., power consumption) also increases. In other words, the GMP model reduces nonlinear distortion compared to the MPM and the memoryless polynomial model, while the MPM reduces nonlinear distortion compared to the memoryless polynomial model. Conversely, the memoryless polynomial model reduces the computational load compared to the MPM and GMP, while the MPM reduces the computational load compared to the GMP. Furthermore, the memoryless polynomial model reduces the amount of memory required to store parameters compared to the MPM and GMP, while the MPM reduces the amount of memory required to store parameters compared to the GMP.

[0086] Furthermore, the first mathematical model is not limited to MPM and GMP. In other words, the first mathematical model may use formulas different from equations (2) and (3). Furthermore, the second mathematical model is not limited to a memoryless polynomial model. In other words, the second mathematical model may use a formula different from equation (1).

[0087] [1.3 Circuit Structure of Tracker Circuit 1]

[0088] Next, refer to Figure 2 The circuit configuration of the tracker circuit 1 will be described. The tracker circuit 1 includes a pre-regulator circuit 10 , a switched capacitor circuit 20 , an output switch circuit 30 , a first filter circuit 41 , a second filter circuit 42 , switches S56 and S57 , and a digital control circuit 60 .

[0089] The pre-regulator circuit 10 can use a power inductor to convert the input voltage supplied from a DC power supply (not shown) into a regulated voltage. The pre-regulator circuit 10 includes a power inductor and a switch. A power inductor refers to an inductor used to step up and / or step down a DC (Direct Current) voltage. The power inductor is configured in series on the DC path. In addition, the power inductor can also be connected between the DC path and the ground (in other words, configured in parallel with the DC path). Such a pre-regulator circuit 10 is also called a magnetic regulator or a DC / DC converter.

[0090] The switched capacitor circuit 20 includes multiple capacitors and multiple switches and can generate multiple discrete voltages, each having multiple discrete voltage levels, based on the voltage supplied from the pre-regulator circuit 10. In this embodiment, the switched capacitor circuit 20 can generate three or more discrete voltages. The switched capacitor circuit 20 is also sometimes referred to as a switched-capacitor voltage balancer.

[0091] The output switch circuit 30 can selectively output at least one of the multiple discrete voltages generated by the switched capacitor circuit 20 to the power amplifier 2. Specifically, in the high-power mode of the D-ET, the output switch circuit 30 can selectively output at least one of a first subset of three or more discrete voltages to the power amplifier 2. Furthermore, in the low-power mode of the D-ET, the output switch circuit 30 can selectively output at least one of a second subset of three or more discrete voltages to the power amplifier 2.

[0092] For example, when the three or more discrete voltages generated by the switched capacitor circuit 20 are (V1, V2, V3, V4) and satisfy V1<V2<V3<V4, (V2, V3, V4) and (V1, V2, V3) can be used as the first subset and the second subset respectively. At this time, the average voltage (V2+V3+V4) / 3 of the first subset is higher than the average voltage (V1+V2+V3) / 3 of the second subset. In addition, (V1, V3, V4) and (V1, V2, V3) can also be used as the first subset and the second subset respectively. In this case, the average voltage (V1+V3+V4) / 3 of the first subset is also higher than the average voltage (V1+V2+V3) / 3 of the second subset. In addition, the first subset and the second subset are not limited to these.

[0093] The first filter circuit 41 and the second filter circuit 42 can attenuate noise from a plurality of discrete voltages supplied to the power amplifier 2. The first filter circuit 41 and the second filter circuit 42 are sometimes called pulse shaping filters or transition shaping filters.

[0094] Switches S56 and S57 are on / off switches for the first filter circuit 41 and the second filter circuit 42, respectively. Switch S56 is connected between the output switch circuit 30 and the first filter circuit 41. Switch S57 is connected between the output switch circuit 30 and the second filter circuit 42.

[0095] The digital control circuit 60 can control the pre-regulator circuit 10 , the switched capacitor circuit 20 , the output switch circuit 30 , and the switches S56 and S57 based on the digital control signal from the RFIC 3 .

[0096] Furthermore, the tracker circuit 1 may not include the pre-regulator circuit 10, the switched capacitor circuit 20, the output switch circuit 30, the first filter circuit 41 and the second filter circuit 42, the switches S56 and S57, and a portion of the digital control circuit 60. For example, the tracker circuit 1 may not include the pre-regulator circuit 10. For another example, the tracker circuit 1 may not include the first filter circuit 41 and the second filter circuit 42 and the switches S56 and S57. Furthermore, any combination of the pre-regulator circuit 10, the switched capacitor circuit 20, the output switch circuit 30, the first filter circuit 41 and the second filter circuit 42, and the switches S56 and S57 may be integrated into a single circuit. Furthermore, the tracker circuit 1 may include multiple voltage supply circuits instead of the pre-regulator circuit 10 and the switched capacitor circuit 20, as described in Patent Document 2. In this case, the output switch circuit 30 may be configured to select at least one of the multiple voltage supply circuits.

[0097] Next, refer to Figure 3 The circuit configuration of each circuit included in the tracker circuit 1 will be described. Figure 3 2 is a circuit configuration diagram of the tracker circuit 1 according to this embodiment.

[0098] also, Figure 3 This is an exemplary circuit configuration, and the tracker circuit 1 can be implemented using any of a variety of circuit implementations and circuit technologies. Therefore, the description of the tracker circuit 1 provided below should not be interpreted in a limiting sense.

[0099] [1.3.1 Circuit Structure of Switched Capacitor Circuit 20]

[0100] First, refer to Figure 3 , the circuit structure of the switched capacitor circuit 20 is described. Figure 3 As shown, the switched capacitor circuit 20 includes capacitors C11 to C16, capacitors C10, C20, C30, and C40, and switches S11 to S14, S21 to S24, S31 to S34, and S41 to S44. Energy and charge are input from the pre-regulator circuit 10 to the switched capacitor circuit 20 at nodes N1 to N4, and are then extracted from the switched capacitor circuit 20 to the output switch circuit 30 at nodes N1 to N4.

[0101] Capacitors C11-C16 each function as a flying capacitor (also sometimes called a flyby capacitor). In other words, each capacitor C11-C16 is used to boost or buck the regulated voltage supplied from the pre-regulator circuit 10. More specifically, capacitors C11-C16 transfer charge between capacitors C11-C16 and nodes N1-N4 to maintain voltages V1-V4 (relative to ground potential) at the four nodes N1-N4, satisfying the relationship V1:V2:V3:V4 = 1:2:3:4. These voltages V1-V4 correspond to multiple discrete voltages, each having multiple discrete voltage levels.

[0102] Capacitor C11 has two electrodes. One of the two electrodes of capacitor C11 is connected to one end of switch S11 and one end of switch S12. The other of the two electrodes of capacitor C11 is connected to one end of switch S21 and one end of switch S22.

[0103] Capacitor C12 has two electrodes. One of the two electrodes of capacitor C12 is connected to one end of switch S21 and one end of switch S22. The other of the two electrodes of capacitor C12 is connected to one end of switch S31 and one end of switch S32.

[0104] The capacitor C13 has two electrodes. One of the two electrodes of the capacitor C13 is connected to one end of the switch S31 and one end of the switch S32. The other of the two electrodes of the capacitor C13 is connected to one end of the switch S41 and one end of the switch S42.

[0105] Capacitor C14 has two electrodes. One of the two electrodes of capacitor C14 is connected to one end of switch S13 and one end of switch S14. The other of the two electrodes of capacitor C14 is connected to one end of switch S23 and one end of switch S24.

[0106] Capacitor C15 has two electrodes. One of the two electrodes of capacitor C15 is connected to one end of switch S23 and one end of switch S24. The other of the two electrodes of capacitor C15 is connected to one end of switch S33 and one end of switch S34.

[0107] Capacitor C16 has two electrodes. One of the two electrodes of capacitor C16 is connected to one end of switch S33 and one end of switch S34. The other of the two electrodes of capacitor C16 is connected to one end of switch S43 and one end of switch S44.

[0108] The group of capacitors C11 and C14 , the group of capacitors C12 and C15 , and the group of capacitors C13 and C16 can be complementarily charged and discharged by repeating the first stage and the second stage.

[0109] Specifically, in the first phase, switches S12, S13, S22, S23, S32, S33, S42, and S43 are turned on. Consequently, for example, one of the two electrodes of capacitor C12 is connected to node N3, the other of the two electrodes of capacitor C12 and one of the two electrodes of capacitor C15 are connected to node N2, and the other of the two electrodes of capacitor C15 is connected to node N1.

[0110] On the other hand, in the second phase, switches S11, S14, S21, S24, S31, S34, S41, and S44 are turned on. Consequently, for example, one of the two electrodes of capacitor C15 is connected to node N3, the other of the two electrodes of capacitor C15 and one of the two electrodes of capacitor C12 are connected to node N2, and the other of the two electrodes of capacitor C12 is connected to node N1.

[0111] By repeating the first and second stages, for example, when one of capacitors C12 and C15 is charged by node N2, the other of capacitors C12 and C15 can be discharged to capacitor C30. In other words, capacitors C12 and C15 can be charged and discharged in a complementary manner.

[0112] The group of capacitors C11 and C14 and the group of capacitors C13 and C16 can also be charged and discharged complementarily in the same manner as the group of capacitors C12 and C15 by repeating the first stage and the second stage.

[0113] The capacitors C10 , C20 , C30 , and C40 each function as a smoothing capacitor. In other words, the capacitors C10 , C20 , C30 , and C40 are used to hold and smooth the voltages V1 to V4 at the nodes N1 to N4 , respectively.

[0114] Capacitor C10 is connected between node N1 and the ground. Specifically, one of the two electrodes of capacitor C10 is connected to node N1, while the other of the two electrodes of capacitor C10 is connected to the ground.

[0115] Capacitor C20 is connected between nodes N2 and N1. Specifically, one of the two electrodes of capacitor C20 is connected to node N2. On the other hand, the other of the two electrodes of capacitor C20 is connected to node N1.

[0116] Capacitor C30 is connected between nodes N3 and N2. Specifically, one of the two electrodes of capacitor C30 is connected to node N3. On the other hand, the other of the two electrodes of capacitor C30 is connected to node N2.

[0117] Capacitor C40 is connected between nodes N4 and N3. Specifically, one of the two electrodes of capacitor C40 is connected to node N4. On the other hand, the other of the two electrodes of capacitor C40 is connected to node N3.

[0118] The switch S11 is connected between one of the two electrodes of the capacitor C11 and the node N3. Specifically, one end of the switch S11 is connected to one of the two electrodes of the capacitor C11. On the other hand, the other end of the switch S11 is connected to the node N3.

[0119] The switch S12 is connected between one of the two electrodes of the capacitor C11 and the node N4. Specifically, one end of the switch S12 is connected to one of the two electrodes of the capacitor C11. On the other hand, the other end of the switch S12 is connected to the node N4.

[0120] Switch S21 is connected between one of the two electrodes of capacitor C12 and node N2. Specifically, one end of switch S21 is connected to one of the two electrodes of capacitor C12 and the other of the two electrodes of capacitor C11. On the other hand, the other end of switch S21 is connected to node N2.

[0121] Switch S22 is connected between one of the two electrodes of capacitor C12 and node N3. Specifically, one end of switch S22 is connected to one of the two electrodes of capacitor C12 and the other of the two electrodes of capacitor C11. On the other hand, the other end of switch S22 is connected to node N3.

[0122] Switch S31 is connected between the other of the two electrodes of capacitor C12 and node N1. Specifically, one end of switch S31 is connected to the other of the two electrodes of capacitor C12 and one of the two electrodes of capacitor C13. On the other hand, the other end of switch S31 is connected to node N1.

[0123] Switch S32 is connected between the other of the two electrodes of capacitor C12 and node N2. Specifically, one end of switch S32 is connected to the other of the two electrodes of capacitor C12 and one of the two electrodes of capacitor C13. Meanwhile, the other end of switch S32 is connected to node N2. In other words, the other end of switch S32 is connected to the other end of switch S21.

[0124] The switch S41 is connected between the other of the two electrodes of the capacitor C13 and the ground. Specifically, one end of the switch S41 is connected to the other of the two electrodes of the capacitor C13. On the other hand, the other end of the switch S41 is connected to the ground.

[0125] Switch S42 is connected between the other of the two electrodes of capacitor C13 and node N1. Specifically, one end of switch S42 is connected to the other of the two electrodes of capacitor C13. On the other hand, the other end of switch S42 is connected to node N1. In other words, the other end of switch S42 is connected to the other end of switch S31.

[0126] Switch S13 is connected between one of the two electrodes of capacitor C14 and node N3. Specifically, one end of switch S13 is connected to one of the two electrodes of capacitor C14. The other end of switch S13 is connected to node N3. In other words, the other end of switch S13 is connected to the other end of switch S11 and the other end of switch S22.

[0127] Switch S14 is connected between one of the two electrodes of capacitor C14 and node N4. Specifically, one end of switch S14 is connected to one of the two electrodes of capacitor C14. On the other hand, the other end of switch S14 is connected to node N4. In other words, the other end of switch S14 is connected to the other end of switch S12.

[0128] Switch S23 is connected between one of the two electrodes of capacitor C15 and node N2. Specifically, one end of switch S23 is connected to one of the two electrodes of capacitor C15 and the other of the two electrodes of capacitor C14. On the other hand, the other end of switch S23 is connected to node N2. In other words, the other end of switch S23 is connected to the other end of switch S21 and the other end of switch S32.

[0129] Switch S24 is connected between one of the two electrodes of capacitor C15 and node N3. Specifically, one end of switch S24 is connected to one of the two electrodes of capacitor C15 and the other of the two electrodes of capacitor C14. On the other hand, the other end of switch S24 is connected to node N3. In other words, the other end of switch S24 is connected to the other end of switch S11, the other end of switch S22, and the other end of switch S13.

[0130] Switch S33 is connected between the other of the two electrodes of capacitor C15 and node N1. Specifically, one end of switch S33 is connected to the other of the two electrodes of capacitor C15 and one of the two electrodes of capacitor C16. Meanwhile, the other end of switch S33 is connected to node N1. In other words, the other end of switch S33 is connected to the other end of switch S31 and the other end of switch S42.

[0131] Switch S34 is connected between the other of the two electrodes of capacitor C15 and node N2. Specifically, one end of switch S34 is connected to the other of the two electrodes of capacitor C15 and one of the two electrodes of capacitor C16. On the other hand, the other end of switch S34 is connected to node N2. In other words, the other end of switch S34 is connected to the other end of switch S21, the other end of switch S32, and the other end of switch S23.

[0132] The switch S43 is connected between the other of the two electrodes of the capacitor C16 and the ground line. Specifically, one end of the switch S43 is connected to the other of the two electrodes of the capacitor C16. On the other hand, the other end of the switch S43 is connected to the ground line.

[0133] Switch S44 is connected between the other of the two electrodes of capacitor C16 and node N1. Specifically, one end of switch S44 is connected to the other of the two electrodes of capacitor C16. Meanwhile, the other end of switch S44 is connected to node N1. In other words, the other end of switch S44 is connected to the other end of switch S31, the other end of switch S42, and the other end of switch S33.

[0134] A first group of switches, including switches S12, S13, S22, S23, S32, S33, S42, and S43, and a second group of switches, including switches S11, S14, S21, S24, S31, S34, S41, and S44, are complementarily switched on and off based on a control signal S2. Specifically, in the first phase, the switches of the first group are turned on, while the switches of the second group are turned off. Conversely, in the second phase, the switches of the first group are turned off, while the switches of the second group are turned on.

[0135] For example, in one of the first and second phases, capacitors C11 to C13 are charged to capacitors C10 to C40, and in the other of the first and second phases, capacitors C14 to C16 are charged to capacitors C10 to C40. In other words, capacitors C11 to C13 or capacitors C14 to C16 are always charged to capacitors C10 to C40. Therefore, even if current flows rapidly from nodes N1 to N4 to the output switch circuit 30, nodes N1 to N4 can be replenished with charge at high speed, thereby suppressing fluctuations in the potential of nodes N1 to N4.

[0136] By operating in this manner, switched capacitor circuit 20 is able to maintain approximately equal voltages across capacitors C10, C20, C30, and C40. Specifically, at the four nodes labeled V1 to V4, voltages V1 to V4 (relative to ground potential) are maintained in the order V1:V2:V3:V4 = 1:2:3:4. The voltage levels of voltages V1 to V4 correspond to the multiple discrete voltage levels that can be supplied to output switch circuit 30 via switched capacitor circuit 20.

[0137] Furthermore, the voltage ratio (V1:V2:V3:V4) is not limited to (1:2:3:4). For example, the voltage ratio (V1:V2:V3:V4) may be (1:2:4:8).

[0138] in addition, Figure 3 The structure of the switched capacitor circuit 20 shown is an example and is not limited thereto. Figure 3 In the embodiment, the switched capacitor circuit 20 is configured to supply four discrete voltages, but the number of discrete voltages is not limited to this. The switched capacitor circuit 20 can also be configured to supply any number of discrete voltages, two or more. For example, when supplying two discrete voltages, the switched capacitor circuit 20 only needs to include capacitors C12 and C15, and switches S21 to S24, and S31 to S34.

[0139] [1.3.2 Circuit Structure of Output Switch Circuit 30]

[0140] Next, refer to Figure 3 , the circuit structure of the output switch circuit 30 is described. Figure 3 As shown, the output switch circuit 30 includes input terminals 131 to 134 , switches S51 to S54 , and an output terminal 130 .

[0141] The output terminal 130 is connected to the first filter circuit 41 and the second filter circuit 42. The output terminal 130 is a terminal for supplying a power supply voltage selected from the voltages V1 to V4 to the power amplifier 2 via the first filter circuit 41 and / or the second filter circuit 42.

[0142] Input terminals 131 to 134 are respectively connected to nodes N4 to N1 of the switched capacitor circuit 20 . Input terminals 131 to 134 are terminals for receiving voltages V4 to V1 from the switched capacitor circuit 20 .

[0143] The switch S51 is connected between the input terminal 131 and the output terminal 130. Specifically, the switch S51 has a terminal connected to the input terminal 131 and a terminal connected to the output terminal 130. In this connection configuration, the switch S51 can switch between connection and disconnection between the input terminal 131 and the output terminal 130 by switching on / off according to the control signal S3.

[0144] The switch S52 is connected between the input terminal 132 and the output terminal 130. Specifically, the switch S52 has a terminal connected to the input terminal 132 and a terminal connected to the output terminal 130. In this connection configuration, the switch S52 can switch between connection and disconnection between the input terminal 132 and the output terminal 130 by switching on / off according to the control signal S3.

[0145] The switch S53 is connected between the input terminal 133 and the output terminal 130. Specifically, the switch S53 has a terminal connected to the input terminal 133 and a terminal connected to the output terminal 130. In this connection structure, the switch S53 can switch between connection and disconnection between the input terminal 133 and the output terminal 130 by switching on / off according to the control signal S3.

[0146] The switch S54 is connected between the input terminal 134 and the output terminal 130. Specifically, the switch S54 has a terminal connected to the input terminal 134 and a terminal connected to the output terminal 130. In this connection configuration, the switch S54 can switch between connection and disconnection between the input terminal 134 and the output terminal 130 by switching on / off according to the control signal S3.

[0147] These switches S51 to S54 are controlled to be exclusively turned on. In other words, only one of the switches S51 to S54 is turned on, and the rest of the switches S51 to S54 are turned off. This allows the output switch circuit 30 to output one voltage selected from the voltages V1 to V4.

[0148] also, Figure 3 The illustrated structure of the output switch circuit 30 is an example and is not limited thereto. In particular, switches S51-S54 may have any configuration as long as they can selectively connect at least one of the four input terminals 131-134 to the output terminal 130. For example, the output switch circuit 30 may further include a switch connected between switches S51-S53, switch S54, and the output terminal 130. Furthermore, for example, the output switch circuit 30 may further include a switch connected between switches S51 and S52, switches S53 and S54, and the output terminal 130.

[0149] Furthermore, when voltages of two discrete voltage levels are supplied from the switched capacitor circuit 20 , the output switch circuit 30 only needs to include at least two of the switches S51 to S54 .

[0150] [1.3.3 Circuit Structure of Pre-regulator Circuit 10]

[0151] Next, refer to Figure 3 , the structure of the pre-regulator circuit 10 is described. Figure 3 As shown, the pre-regulator circuit 10 includes an input terminal 110 , output terminals 111 to 114 , switches S61 to S63 , S71 , and S72 , a power inductor L71 , and capacitors C61 to C64 .

[0152] The input terminal 110 is a terminal for inputting a DC voltage. In other words, the input terminal 110 is a terminal for receiving an input voltage from the DC power supply 50 .

[0153] Output terminal 111 is an output terminal for voltage V4. In other words, output terminal 111 is a terminal for supplying voltage V4 to switched capacitor circuit 20. Output terminal 111 is connected to node N4 of switched capacitor circuit 20.

[0154] Output terminal 112 is an output terminal for voltage V3. In other words, output terminal 112 is a terminal for supplying voltage V3 to switched capacitor circuit 20. Output terminal 112 is connected to node N3 of switched capacitor circuit 20.

[0155] Output terminal 113 is an output terminal for voltage V2. In other words, output terminal 113 is a terminal for supplying voltage V2 to switched capacitor circuit 20. Output terminal 113 is connected to node N2 of switched capacitor circuit 20.

[0156] Output terminal 114 is an output terminal for voltage V1. In other words, output terminal 114 is a terminal for supplying voltage V1 to switched capacitor circuit 20. Output terminal 114 is connected to node N1 of switched capacitor circuit 20.

[0157] Switch S71 is connected between input terminal 110 and one end of power inductor L71. Specifically, switch S71 has a terminal connected to input terminal 110 and a terminal connected to one end of power inductor L71. In this connection structure, switch S71 can switch between connection and disconnection between input terminal 110 and one end of power inductor L71 by switching on and off based on control signal S1.

[0158] Switch S72 is connected between one end of the power inductor L71 and the ground line. Specifically, switch S72 has a terminal connected to one end of the power inductor L71 and a terminal connected to the ground line. In this connection structure, switch S72 can switch between connecting and disconnecting one end of the power inductor L71 and the ground line by switching on and off based on control signal S1.

[0159] The switch S61 is connected between the other end of the power inductor L71 and the output terminal 111. Specifically, the switch S61 has a terminal connected to the other end of the power inductor L71 and a terminal connected to the output terminal 111. In this connection structure, the switch S61 can switch between connection and disconnection between the other end of the power inductor L71 and the output terminal 111 by switching on and off based on the control signal S1.

[0160] The switch S62 is connected between the other end of the power inductor L71 and the output terminal 112. Specifically, the switch S62 has a terminal connected to the other end of the power inductor L71 and a terminal connected to the output terminal 112. In this connection structure, the switch S62 can switch between connection and disconnection between the other end of the power inductor L71 and the output terminal 112 by switching on and off based on the control signal S1.

[0161] The switch S63 is connected between the other end of the power inductor L71 and the output terminal 113. Specifically, the switch S63 has a terminal connected to the other end of the power inductor L71 and a terminal connected to the output terminal 113. In this connection structure, the switch S63 can switch between connection and disconnection between the other end of the power inductor L71 and the output terminal 113 by switching on and off based on the control signal S1.

[0162] One of the two electrodes of the capacitor C61 is connected to the switch S61 and the output terminal 111. The other of the two electrodes of the capacitor C61 is connected to the switch S62, the output terminal 112, and one of the two electrodes of the capacitor C62.

[0163] One of the two electrodes of capacitor C62 is connected to switch S62, output terminal 112, and the other of the two electrodes of capacitor C61. The other of the two electrodes of capacitor C62 is connected to a path connecting switch S63, output terminal 113, and one of the two electrodes of capacitor C63.

[0164] One of the two electrodes of capacitor C63 is connected to switch S63, output terminal 113, and the other of the two electrodes of capacitor C62. The other of the two electrodes of capacitor C63 is connected to output terminal 114 and one of the two electrodes of capacitor C64.

[0165] One of the two electrodes of the capacitor C64 is connected to the output terminal 114 and the other of the two electrodes of the capacitor C63 , and the other of the two electrodes of the capacitor C64 is connected to the ground.

[0166] Switches S61-S63 are controlled to be exclusively turned on. In other words, only one of switches S61-S63 is turned on, while the remaining switches S61-S63 are turned off. By turning on only one of switches S61-S63, pre-regulator circuit 10 can change the voltage supplied to switched capacitor circuit 20 to a voltage level between voltages V2-V4.

[0167] The pre-regulator circuit 10 configured in this manner can supply charge to the switched capacitor circuit 20 via at least one of the output terminals 111 to 114 .

[0168] Furthermore, when the input voltage only needs to be converted into one regulated voltage, the pre-regulator circuit 10 only needs to include at least the switches S71 and S72 and the power inductor L71 .

[0169] [1.3.4 Circuit Structure of the First Filter Circuit 41 and the Second Filter Circuit 42]

[0170] Next, refer to Figure 3 , the circuit configurations of the first filter circuit 41 and the second filter circuit 42 of this embodiment will be described.

[0171] The first filter circuit 41 includes a parallel circuit (LC parallel circuit) of an inductor L51 and a capacitor C51 . One end of the parallel circuit is connected to a switch S56 , and the other end is connected to the power amplifier 2 .

[0172] The second filter circuit 42 includes a parallel circuit of an inductor L52 and a capacitor C52 . One end of the parallel circuit of the inductor L52 and the capacitor C52 is connected to the switch S57 , and the other end of the parallel circuit of the inductor L52 and the capacitor C52 is connected to the power amplifier 2 .

[0173] The first filter circuit 41 and the second filter circuit 42 connected in this manner are switched on / off by switches S56 and S57. Thus, the first filter circuit 41 and the second filter circuit 42 can switch on / off the band-stop filter for removing noise from a plurality of discrete voltages. For example, by controlling the opening and closing of switches S56 and S57, the following three band-stop filters (1) to (3) can be realized.

[0174] (1) By closing switch S56 and opening switch S57, the first filter circuit 41 is connected between the output switch circuit 30 and the power amplifier 2, and the second filter circuit 42 is not connected. As a result, the first filter circuit 41 functions as a band-stop filter, and the second filter circuit 42 does not function as a band-stop filter.

[0175] (2) By opening switch S56 and closing switch S57, the second filter circuit 42 is connected between the output switch circuit 30 and the power amplifier 2, and the first filter circuit 41 is disconnected. As a result, the second filter circuit 42 functions as a band-stop filter, and the first filter circuit 41 does not function as a band-stop filter.

[0176] (3) By closing the switch S56 and the switch S57, the first filter circuit 41 and the second filter circuit 42 are connected between the output switch circuit 30 and the power amplifier 2. Thus, the first filter circuit 41 and the second filter circuit 42 function as band-stop filters.

[0177] For example, the opening and closing of switches S56 and S57 can be controlled based on the channel bandwidth (i.e., modulation bandwidth) of the high-frequency signal RF. Furthermore, if the power amplifier 2 is capable of amplifying transmission signals in multiple frequency bands, the opening and closing of switches S56 and S57 can also be controlled based on the frequency band of the transmission signal amplified by the power amplifier 2. The opening and closing control of switches S56 and S57 is not limited to the above.

[0178] Figure 3 The circuit configurations of the first filter circuit 41 and the second filter circuit 42 are shown as examples and are not limited thereto. For example, the first filter circuit 41 and / or the second filter circuit 42 may also be a series circuit (LC series circuit) of an inductor and a capacitor. In this case, the LC series circuit may be connected between the path connecting the output switch circuit 30 and the power amplifier 2 and the ground line.

[0179] [1.3.5 Circuit Structure of Digital Control Circuit 60]

[0180] Next, the circuit structure of the digital control circuit 60 will be described. Figure 3 As shown, the digital control circuit 60 includes a first controller 61 and a second controller 62 .

[0181] The first controller 61 can generate control signals S1 to S4 by processing a serial data signal (DATA) based on a clock signal (CLK) supplied from the RFIC 3. Here, the serial data signal refers to a data signal transmitted bit by bit through a signal line or a circuit.

[0182] Control signal S1 is a signal for controlling the opening and closing of switches S61 to S63, S71, and S72 included in pre-regulator circuit 10. Control signal S2 is a signal for controlling the opening and closing of switches S11 to S14, S21 to S24, S31 to S34, and S41 to S44 included in switched capacitor circuit 20. Control signal S3 is a signal for controlling the opening and closing of switches S51 to S54 included in output switch circuit 30 when power amplifier 2 is in APT mode. Control signal S4 is a signal for controlling the opening and closing of switches S56 and S57 used in first filter circuit 41 and second filter circuit 42.

[0183] The clock signal used to process the serial data signal in the first controller 61 uses a signal line different from the serial data signal, but the present invention is not limited thereto. For example, the clock signal may be transmitted via the same signal line as the serial data signal.

[0184] In addition, in this embodiment, one serial data signal is used to control the pre-regulator circuit 10 , the switched capacitor circuit 20 , the output switch circuit 30 , and the switches S56 and S57 , but a plurality of serial data signals may be used.

[0185] The second controller 62 can process the digital control logic (DCL) signals (DCL1, DCL2) supplied from the RFIC 3 to generate the control signal S5. The DCL signal is an example of a parallel data signal. Here, a parallel data signal refers to a data signal that is transmitted simultaneously and in parallel through multiple signal lines or circuits.

[0186] When power amplifier 2 is in D-ET mode, RFIC 3 generates DCL signals (DCL1, DCL2) based on the envelope signal of the high-frequency signal. Therefore, when power amplifier 2 is in D-ET mode, control signal S5 is a signal for controlling the opening and closing of switches S51 to S54 included in output switch circuit 30.

[0187] Each DCL signal (DCL1, DCL2) is a single-bit signal. Voltages V1 to V4 are represented by a combination of two single-bit signals. For example, "00," "01," "10," and "11" represent V1, V2, V3, and V4, respectively. Gray code can also be used to represent voltage levels.

[0188] Furthermore, while this embodiment uses two DCL signals to control the output switch circuit 30 in D-ET mode, the number of DCL signals is not limited to this. For example, an arbitrary number of DCL signals, from one to three or more, may be used, depending on the number of voltage levels selectable by each output switch circuit 30. Furthermore, the digital control signals used to control the output switch circuit 30 are not limited to DCL signals.

[0189] [1.4 Power Amplification Method]

[0190] Next, refer to Figure 4 The power amplification method of this embodiment will be described. Figure 4 1 is a flowchart showing the power amplification method according to this embodiment.

[0191] First, it is determined whether to use the high power mode or the low power mode in the D-ET mode ( S10 ).

[0192] Here, when the high power mode is used (HPM at S10), the output switch circuit 30 selectively supplies at least one of the first subset of three or more discrete voltages to the power amplifier 2 (S20). Furthermore, whether the high power mode is used can be determined by determining which of the multiple discrete voltages generated by the switched capacitor circuit 20 is supplied to the power amplifier 2.

[0193] Next, RFIC3 predistorts the input signal of power amplifier 2 using first parameters in a first mathematical model for setting the memory effect (S30). Specifically, DPD circuit 71 uses, for example, a predetermined polynomial degree, memory depth, and DPD coefficient as first parameters in equation (2) or (3), calculates a predistorted digital IQ signal, and converts the calculated predistorted digital IQ signal into a predistorted analog IQ signal. Then, quadrature modulator 73 quadrature-modulates and up-converts the predistorted analog IQ signal supplied from DPD circuit 71 to generate a predistorted high-frequency signal RF.

[0194] Next, the power amplifier 2 amplifies the predistorted input signal (high-frequency signal RF) using a first subset of three or more discrete voltages (S40). Thus, even when the influence of the memory effect increases due to the relatively high power supply voltage Vcc supplied in the high-power mode, the nonlinear distortion caused by the memory effect can be effectively reduced.

[0195] On the other hand, when the low power mode is used (LPM in S10), the output switch circuit 30 selectively supplies at least one of the second subset of three or more discrete voltages to the power amplifier 2 (S50). In addition, whether the low power mode is used can be determined by determining which of the multiple discrete voltages generated by the switched capacitor circuit 20 is supplied to the power amplifier 2.

[0196] Next, RFIC3 uses the second parameter in the second mathematical model without the memory effect, or uses the third parameter in the first mathematical model to predistort the input signal of the power amplifier 2 (S60). Specifically, the DPD circuit 71 uses the predetermined polynomial degree and DPD coefficient as the second parameter in equation (1) to calculate the predistorted digital IQ signal. Alternatively, the DPD circuit 71 uses the polynomial degree, memory depth and DPD coefficient as the third parameter in equation (2) or (3) to calculate the predistorted digital IQ signal. At this time, the number of third parameters is less than the number of first parameters. Conversely, the number of first parameters is greater than the number of third parameters. The DPD circuit 71 converts the calculated predistorted digital IQ signal into a predistorted analog IQ signal. The orthogonal modulator 73 generates a high-frequency signal RF by performing orthogonal modulation and up-conversion on the predistorted analog IQ signal supplied from the DPD circuit 71.

[0197] Next, the power amplifier 2 amplifies the predistorted input signal (high-frequency signal RF) using a second subset of three or more discrete voltages (S70). This reduces the impact of the memory effect by supplying a relatively low power supply voltage Vcc in low-power mode, thereby reducing the computational load for the memory effect and reducing power consumption.

[0198] The corresponding relationships among the modes, mathematical models, and parameter combinations in the above power amplification method are summarized in Table 1 below.

[0199] [Table 1]

[0200]

[0201] [1.5 Effects, etc.]

[0202] As described above, the power amplification system 7 of this embodiment includes a power amplifier 2, an output switch circuit 30 configured to selectively output at least one of three or more discrete voltages to the power amplifier 2, and a DPD circuit 71 configured to predistort an input signal of the power amplifier 2. The output switch circuit 30 has a first mode for selectively outputting at least one of a first subset of the three or more discrete voltages, and a second mode for selectively outputting at least one of a second subset of the three or more discrete voltages. The average voltage of the first subset is higher than the average voltage of the second subset. In the first mode, the DPD circuit 71 predistorts the input signal of the power amplifier 2 using a first parameter in a first mathematical model for DPD. In the second mode, the DPD circuit 71 predistorts the input signal of the power amplifier 2 using a second parameter in a second mathematical model for DPD, or uses a third parameter in the first mathematical model to predistort the input signal of the power amplifier 2.

[0203] In addition, the power amplification method of this embodiment selectively supplies at least one of a first subset of three or more discrete voltages to the power amplifier 2 (S20), predistorts the first input signal of the power amplifier 2 using a first parameter in a first mathematical model for DPD (S30), amplifies the predistorted first input signal using the first subset of three or more discrete voltages (S40), selectively supplies at least one of a second subset of three or more discrete voltages to the power amplifier 2 (S50), predistorts the second input signal of the power amplifier 2 using a second parameter in a second mathematical model for DPD, or using a third parameter in the first mathematical model (S60), and amplifies the predistorted second input signal using the second subset of three or more discrete voltages (S70).

[0204] In addition, the DPD circuit 71 of the present embodiment is a DPD circuit 71 configured to pre-distort the input signal of the power amplifier 2. In a first mode in which at least one of a first subset of three or more discrete voltages is selectively supplied to the power amplifier 2, the input signal of the power amplifier 2 is pre-distorted using a first parameter in a first mathematical model for DPD. In a second mode in which at least one of a second subset of three or more discrete voltages is selectively supplied to the power amplifier 2, the input signal of the power amplifier 2 is pre-distorted using a second parameter in a second mathematical model for DPD, or a third parameter is used in the first mathematical model. The average voltage of the first subset is higher than the average voltage of the second subset.

[0205] Thus, it is possible to switch between the first and second mathematical models, or to switch the parameters of the first mathematical model, based on a subset of three or more discrete voltages supplied to power amplifier 2. In the first mode, where the average voltage is higher, the impact of the memory effect of power amplifier 2 is greater than in the second mode, where the average voltage is lower. Therefore, by pre-distorting the input signal using the first parameter in the first mathematical model, priority is given to reducing nonlinear distortion over reducing the computational load for DPD (in other words, reducing power consumption). Conversely, in the second mode, where the average voltage is lower, by pre-distorting the input signal using the second parameter in the second mathematical model, or by pre-distorting the input signal using the third parameter in the first mathematical model, priority is given to reducing the computational load for DPD. This effectively reduces nonlinear distortion while suppressing an increase in power consumption.

[0206] For example, in the power amplification system 7, the power amplification method or the DPD circuit 71 of this embodiment, the memory effect of the power amplifier 2 may be set in the first mathematical model, or the memory effect of the power amplifier 2 may not be set in the second mathematical model.

[0207] According to this, by pre-distorting the input signal using the first mathematical model, nonlinear distortion can be further reduced, and by pre-distorting the input signal using the second mathematical model, calculation load can be further reduced.

[0208] For example, in the power amplification system 7 , the power amplification method, or the DPD circuit 71 of the present embodiment, the number of first parameters may be greater than the number of third parameters.

[0209] Thus, in the first mode, where the average voltage is high, increasing the number of parameters (for example, increasing the number of DPD coefficients by increasing the memory depth) increases the number of terms used to compensate for memory effects, further reducing nonlinear distortion. On the other hand, in the second mode, where the average voltage is low, reducing the number of parameters reduces the number of terms used to compensate for memory effects, further reducing the computational load.

[0210] For example, in the power amplification system 7 or the DPD circuit 71 of the present embodiment, the first mode and the second mode may be the DET mode.

[0211] For example, in the power amplification method of this embodiment, at least one of the first subsets may be selected based on the envelope signal of the first input signal, and at least one of the second subsets may be selected based on the envelope signal of the second input signal.

[0212] With this, the power supply voltage Vcc can be varied based on the envelope signal, thereby improving power efficiency.

[0213] (Other Embodiments)

[0214] While the power amplifier system and DPD method of the present invention have been described above based on the embodiments and their variations, the power amplifier system and DPD method of the present invention are not limited to the aforementioned embodiments and their variations. Other embodiments implemented by combining arbitrary components of the aforementioned embodiments and their variations, variations resulting from various modifications conceived by those skilled in the art to the aforementioned embodiments and their variations without departing from the spirit of the present invention, and various devices incorporating the aforementioned power amplifier system are also encompassed by the present invention.

[0215] For example, in the circuit configurations of the various circuits of the above-described embodiments, other circuit elements and wiring may be inserted between the paths connecting the circuit elements and signal paths disclosed in the drawings. For example, a filter may be inserted between the DAC 72 and the orthogonal modulator 73. Furthermore, for example, a filter may be inserted between the power amplifier 2 and the antenna 5.

[0216] Furthermore, in the above embodiment, multiple discrete voltages are supplied to the output switch circuit from a switched capacitor circuit, but this is not limiting. For example, multiple voltages may be supplied from multiple DC-DC converters. Furthermore, when the voltage levels of the multiple discrete voltages are evenly spaced, using a switched capacitor circuit is preferred, as it effectively reduces the size of the tracker module.

[0217] Furthermore, in the above embodiment, four discrete voltages are supplied to the power amplifier. However, the number of discrete voltages is not limited to four. For example, as long as the plurality of discrete voltages includes at least a voltage corresponding to the maximum output power and a voltage corresponding to the output power with the highest generation frequency, the power added efficiency can be improved.

[0218] The present invention can be widely used in communication equipment such as mobile phones as a power amplification system for amplifying high-frequency signals.

[0219] Description of Reference Numerals

[0220] 1…tracker circuit, 2…power amplifier, 3…RFIC, 4…BBIC, 5…antenna, 6…communication device, 7…power amplification system, 10…pre-regulator circuit, 20…switched capacitor circuit, 30…output switching circuit, 41…first filter circuit, 42…second filter circuit, 60…digital control circuit, 61…first controller, 62…second controller, 71…DPD circuit, 72…DAC, 73…quadrature modulator.

Claims

1. A power amplification system, wherein: have: Power amplifier; an output switching circuit configured to selectively output at least one of three or more discrete voltages to the power amplifier; and A digital predistortion circuit is configured to predistort the input signal of the power amplifier. The output switch circuit has a first mode and a second mode, wherein the first mode selectively outputs at least one of a first subset of the three or more discrete voltages, and the second mode selectively outputs at least one of a second subset of the three or more discrete voltages. The average voltage of the first subset is higher than the average voltage of the second subset, The digital predistortion circuit predistorts the input signal of the power amplifier using first parameters in a first mathematical model for digital predistortion in the first mode. In the second mode, the digital predistortion circuit predistorts the input signal of the power amplifier using second parameters in a second mathematical model for digital predistortion or using third parameters in the first mathematical model.

2. The power amplification system according to claim 1, wherein: The first mathematical model includes the memory effect of the power amplifier. The memory effect of the power amplifier is not included in the second mathematical model.

3. The power amplification system according to claim 1, wherein: The number of the first parameters is greater than the number of the third parameters.

4. The power amplification system according to any one of claims 1 to 3, wherein: The first mode and the second mode are D-ET (Digital Envelope Tracking) modes.

5. A power amplification method, wherein: selectively supplying at least one of a first subset of three or more discrete voltages to a power amplifier, predistorting a first input signal of the power amplifier using first parameters in a first mathematical model for digital predistortion, amplifying the predistorted first input signal using the first subset of the three or more discrete voltages, selectively supplying at least one of a second subset of the three or more discrete voltages to the power amplifier, using a second parameter in a second mathematical model for digital predistortion, or using a third parameter in the first mathematical model, to predistort a second input signal of the power amplifier; The second input signal that has been predistorted is amplified using the second subset of the three or more discrete voltages.

6. The power amplification method according to claim 5, wherein: The average voltage of the first subset is higher than the average voltage of the second subset, The first mathematical model includes the memory effect of the power amplifier. The memory effect of the power amplifier is not included in the second mathematical model.

7. The power amplification method according to claim 5, wherein: The average voltage of the first subset is higher than the average voltage of the second subset, The number of the first parameters is greater than the number of the third parameters.

8. The power amplification method according to any one of claims 5 to 7, wherein: selecting at least one of the first subset based on the envelope signal of the first input signal, At least one of the second subsets is selected based on an envelope signal of the second input signal.

9. A digital predistortion circuit configured to predistort an input signal of a power amplifier, wherein: In a first mode of selectively supplying at least one of a first subset of three or more discrete voltages to the power amplifier, predistorting an input signal of the power amplifier using first parameters in a first mathematical model for digital predistortion, In a second mode of selectively supplying at least one of a second subset of the three or more discrete voltages to the power amplifier, predistorting an input signal of the power amplifier using a second parameter in a second mathematical model for digital predistortion or using a third parameter in the first mathematical model, The average voltage of the first subset is higher than the average voltage of the second subset.

10. The digital predistortion circuit according to claim 9, wherein: The memory effect of the power amplifier is provided in the first mathematical model, while the memory effect of the power amplifier is not provided in the second mathematical model.

11. The digital predistortion circuit according to claim 9, wherein: The number of the first parameters is greater than the number of the third parameters.

12. The digital predistortion circuit according to any one of claims 9 to 11, wherein: The first mode and the second mode are DET modes.

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