Testing method and testing device of semiconductor device, electronic equipment and medium

Abstract

The invention provides a semiconductor device testing method and device, electronic equipment and a medium, and the method comprises the steps: obtaining a current-voltage relation model of a bidirectional threshold switch in a switching-off stage, so as to obtain a change relation model of a differential resistance absolute value of the bidirectional threshold switch in the switching-off stage along with the voltage, thereby obtaining a maximum differential resistance absolute value; and taking the maximum differential resistance absolute value as a resistance threshold value of the line resistance so as to obtain the maximum line resistance which can be supported by the storage unit. Therefore, when the line resistance is smaller than or equal to the resistance threshold value range, the bidirectional threshold value switches in all the storage units can be completely turned off within specific time, and the operation consistency of the storage unit array is not affected.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a testing method, a testing device, an electronic device, and a medium for a semiconductor device. Background Art

[0002] The development of artificial intelligence and integrated storage and computing technologies has placed higher demands on data storage and computing capabilities. In the current von Neumann computing architecture, large amounts of data must be read and stored between dynamic random access memory (DRAM) and solid-state drives (SSDs). This significant performance gap between the two has led to a performance bottleneck in the current von Neumann computing architecture. Currently, the use of storage-class memory (SCM) to bridge DRAM and SSDs is being proposed to improve the current storage architecture. SCM must achieve speeds significantly faster than NAND and exhibit excellent non-volatility. Among several emerging SCM storage technologies, 3D crosspoint (3D Xpoint) memory holds the most promise, offering advantages such as large capacity, high speed, non-volatility, and excellent cycle performance. Recently, research has become active on high-capacity non-volatile memory technologies, such as phase change memory (PCM) and selector-only memory (SOM), to mitigate the weaknesses of 3D Xpoint memory.

[0003] As the array continues to grow, longer wires (such as word lines and bit lines) are needed to connect the memory cell array. These longer wires in the array introduce excessive line resistance, causing significant differences in the electrical properties of devices (i.e., memory cells) at different locations in the array, thus affecting the consistency of array operation. For example, excessive line resistance can cause corresponding devices to not fully shut down or exhibit altered electrical characteristics under the same operation.

[0004] Therefore, how to test the maximum line resistance that the array can support is crucial for array design and device electrical optimization. Summary of the Invention

[0005] Embodiments of the present application provide a semiconductor device testing method, testing apparatus, electronic equipment, and medium, which are intended to test the resistance threshold of the line resistance of a conductive line to obtain the maximum line resistance that a storage unit can support.

[0006] An embodiment of the present application provides a test for a semiconductor device, the semiconductor device comprising: the semiconductor device comprising a plurality of first conductive lines, a plurality of second conductive lines, and a plurality of storage units distributed in an array, each of the storage units being connected between a first conductive line and a second conductive line, each of the storage units having a different line resistance in a conductive path connected in series with the corresponding first conductive line and second conductive line, the storage unit comprising a bidirectional threshold switch; a test method for the semiconductor device comprising: obtaining a current-voltage relationship model of the bidirectional threshold switch to be tested in a closed phase, wherein in the closed phase, the current and voltage of the bidirectional threshold switch are negatively correlated, and the resistance of the bidirectional threshold switch changes nonlinearly; obtaining a relationship model of a change in the absolute value of the differential resistance of the bidirectional threshold switch in the closed phase with voltage based on the current-voltage relationship model; obtaining a maximum absolute value of the differential resistance of the bidirectional threshold switch in the closed phase based on the change relationship model, and using the maximum absolute value of the differential resistance as the resistance threshold of the line resistance.

[0007] In some embodiments, the method for obtaining the current-voltage relationship model of the bidirectional threshold switch to be tested in the off stage includes: applying a first bias voltage to both sides of the bidirectional threshold switch to put the bidirectional threshold switch in the on stage; after applying the first bias voltage, applying a second bias voltage to both sides of the bidirectional threshold switch to put the bidirectional threshold switch from the on stage to the off stage; obtaining the current corresponding to the second bias voltage in the off stage to obtain the current-voltage relationship model.

[0008] In some embodiments, the method of applying a first bias voltage to both sides of the bidirectional threshold switch includes: applying the first bias voltage to both sides of the bidirectional threshold switch, wherein the first bias voltage is greater than the threshold voltage of the bidirectional threshold switch, so that the bidirectional threshold switch enters the conduction stage; and reducing the first bias voltage to a holding voltage so that the bidirectional threshold switch maintains the conduction stage.

[0009] In some embodiments, the method of applying a second bias voltage to both sides of the bidirectional threshold switch includes: applying a second bias voltage to both sides of the bidirectional threshold switch, wherein the second bias voltage increases from the holding voltage so that the bidirectional threshold switch enters the closing stage; wherein, in the closing stage, the current of the bidirectional threshold switch decreases, and the current of the bidirectional threshold switch changes nonlinearly with the increase of the second bias voltage.

[0010] In some embodiments, the method for obtaining a relationship model of the absolute value of the differential resistance of the bidirectional threshold switch in the closed stage as a inverse function of the voltage based on the current-voltage relationship model includes: obtaining the instantaneous resistance corresponding to each voltage in the current-voltage relationship model, wherein the instantaneous resistance is a negative value; and obtaining the absolute value of the differential resistance based on the instantaneous resistance.

[0011] In some embodiments, the shutdown phase includes a turn-off phase and a discharge phase, and the second bias voltage includes a cut-off voltage and a turn-off voltage; the method of applying the second bias voltage to both sides of the bidirectional threshold switch includes: applying a second bias voltage to both sides of the bidirectional threshold switch, the second bias voltage increasing from the holding voltage to the cut-off voltage, so that the bidirectional threshold switch enters the turn-off phase, and in the turn-off phase, the absolute value of the differential resistance of the bidirectional threshold switch first increases and then decreases; after the cut-off voltage, increasing the second bias voltage until reaching the discharge voltage, so that the bidirectional threshold switch enters the discharge phase from the turn-off phase, and in the discharge phase, the differential resistance of the bidirectional threshold switch remains unchanged.

[0012] In some embodiments, the method of obtaining the current corresponding to the second bias voltage in the closing stage to obtain the current-voltage relationship model includes: obtaining the current corresponding to the second bias voltage in the turn-off stage to obtain a first relationship model in which the current changes with voltage, as the current-voltage relationship model; the method of obtaining the maximum differential resistance absolute value of the bidirectional threshold switch in the closing stage according to the change relationship model includes: obtaining a second relationship model in which the absolute value of the differential resistance in the turn-off stage changes with voltage according to the first relationship model; and obtaining the maximum differential resistance absolute value according to the peak value of the second relationship model.

[0013] In some embodiments, the method for obtaining the current-voltage relationship model of the bidirectional threshold switch to be tested in the closed stage includes: forming a test circuit, the test circuit including the bidirectional threshold switch to be tested, and a resistance element coupled to the bidirectional threshold switch; obtaining the initial current-voltage relationship model of the test circuit when the bidirectional threshold switch is in the closed stage; and obtaining the current-voltage relationship model of the bidirectional threshold switch in the closed stage based on the initial current-voltage relationship model and the resistance value of the resistance element.

[0014] An embodiment of the present application also provides a testing device for a semiconductor device, wherein the semiconductor device includes multiple first conductive lines, multiple second conductive lines, and multiple storage units distributed in an array, each of the storage units is connected between one of the first conductive lines and one of the second conductive lines, and each of the storage units has a different line resistance in a conductive path connected in series with the corresponding first conductive line and second conductive line, and the storage unit includes a bidirectional threshold switch; the testing device for the semiconductor device includes: a testing module for obtaining a current-voltage relationship model of the bidirectional threshold switch to be tested in a closed stage, wherein in the closed stage, the current and voltage of the bidirectional threshold switch are negatively correlated, and the resistance of the bidirectional threshold switch changes nonlinearly; a first acquisition module for obtaining a relationship model of the absolute value of the differential resistance of the bidirectional threshold switch in the closed stage as a inverse function of the voltage based on the current-voltage relationship model; and a second acquisition module for obtaining the maximum absolute value of the differential resistance of the bidirectional threshold switch in the closed stage based on the change relationship model, and using the maximum absolute value of the differential resistance as the resistance threshold of the line resistance.

[0015] In some embodiments, the first acquisition module includes: a first acquisition unit, used to obtain the instantaneous resistance corresponding to each voltage in the current-voltage relationship model, where the instantaneous resistance is a negative value; and a second acquisition unit, used to obtain the absolute value of the differential resistance based on the instantaneous resistance.

[0016] An embodiment of the present application further provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and running on the processor, wherein the processor implements the steps of the test method in any of the above embodiments when executing the computer program.

[0017] An embodiment of the present application further provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the steps of the testing method in any of the above embodiments are implemented.

[0018] In the semiconductor device testing method of the embodiment of the present application, a current-voltage relationship model of a bidirectional threshold switch in the off phase is obtained to obtain a relationship model of the absolute value of the differential resistance of the bidirectional threshold switch in the off phase with voltage, thereby obtaining the maximum absolute value of the differential resistance. This maximum absolute value of the differential resistance is used as the resistance threshold of the line resistance. Excessive line resistance causes the current of the corresponding bidirectional threshold switch to remain at a minimum constant current value during the off phase, resulting in the bidirectional threshold switch not being able to fully shut down or requiring a change in electrical operation to shut down. The bidirectional threshold switch resistance changes nonlinearly during the off phase, and the shrinkage of the defect cluster during the off phase causes the bidirectional threshold switch to have a maximum absolute value of differential resistance, i.e., a maximum resistance value. This maximum resistance value can reduce the current. When the resistance threshold of the line resistance is equal to the maximum resistance value, this maximum resistance value can just compensate for the minimum constant current value caused by the excessive line resistance, thereby reducing this minimum constant current value to zero within a specific time, causing the bidirectional threshold switch to fully shut down. Therefore, when the line resistance is within a range less than or equal to the resistance threshold, the bidirectional threshold switches in all memory cells can be fully shut down within a specific time without affecting the operational consistency of the memory cell array.

[0019] Other features and advantages of the present application will be described in detail in the subsequent detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] To more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present application. Those skilled in the art can also derive other drawings based on these drawings without inventive effort.

[0021] Figure 1 is a relationship model between line resistance and electrical characteristics of a bidirectional threshold switch provided in some embodiments of the present application;

[0022] Figure 2 is a schematic diagram of the three-dimensional structure of a semiconductor device provided in some embodiments of the present application;

[0023] Figure 3 yes Figure 2 A schematic diagram of the top view structure of the semiconductor device;

[0024] Figure 4 is a flowchart of a semiconductor device testing method provided by some embodiments of the present application;

[0025] Figure 5 This is a relationship model of current versus voltage during testing of a semiconductor device provided by some embodiments of the present application;

[0026] Figure 6 yes Figure 5 Current-voltage relationship model of bidirectional threshold switch in the off stage;

[0027] Figure 7 is based on Figure 6 A relationship model of the absolute value of the differential resistance of the bidirectional threshold switch in the off phase versus the voltage obtained;

[0028] Figure 8 is a flow chart of a method for obtaining a current-voltage relationship model of the bidirectional threshold switch to be tested in a closed phase, provided in some embodiments of the present application;

[0029] Figure 9 is a schematic structural diagram of a test circuit provided in some embodiments of the present application;

[0030] Figure 10 This is a relationship model of current and voltage changes in the test circuit provided in some embodiments of the present application during the test process;

[0031] Figure 11 yes Figure 10 Current-voltage relationship model of bidirectional threshold switch in the off stage;

[0032] Figure 12 This is a schematic structural diagram of a semiconductor device testing device provided in some embodiments of the present application. DETAILED DESCRIPTION

[0033] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0034] Currently, the requirement for array line resistance (the range of line resistance that can be supported while maintaining array operational consistency) can be determined using a large amount of electrical data, such as threshold voltage, operating current, and error rates at different array positions. This judgment method incorporates many factors, such as leakage, which interferes with our judgment of the line resistance range.

[0035] In one embodiment, the relationship between the holding voltage (and / or holding current) and the line resistance of the bidirectional threshold switch can be obtained through a large number of electrical tests, and the point where the holding voltage (or holding current) suddenly changes is used as the maximum line resistance (i.e., resistance threshold) that the array can support.

[0036] See also Figure 1 , Figure 1This is a relationship model between line resistance and electrical characteristics of a bidirectional threshold switch provided in some embodiments of the present application.

[0037] As can be seen, when the line resistance is very small, for example, less than or equal to 20 kilohms, the holding voltage and holding current are very low. However, when the line resistance exceeds 20 kilohms, the holding voltage and holding current suddenly change. In other words, when the line resistance is too large, the device's electrical characteristics (holding characteristics) will change, affecting the consistency of array operation. However, this test method is difficult to implement in real-world testing due to the large amount of data.

[0038] Based on this, an embodiment of the present application provides a method for testing a semiconductor device, wherein the semiconductor device includes a plurality of first conductive lines, a plurality of second conductive lines, and a plurality of storage cells distributed in an array, wherein each storage cell is connected between a first conductive line and a second conductive line, and each storage cell has a different line resistance in a conductive path connected in series with the corresponding first conductive line and second conductive line, and the storage cell includes a bidirectional threshold switch. The method for testing the semiconductor device includes: obtaining a current-voltage relationship model of the bidirectional threshold switch to be tested in a closed phase, wherein the current and voltage of the bidirectional threshold switch are negatively correlated in the closed phase, and the resistance of the bidirectional threshold switch changes nonlinearly; obtaining a relationship model of the absolute value of the differential resistance of the bidirectional threshold switch in the closed phase as a function of voltage based on the current-voltage relationship model; obtaining a maximum absolute value of the differential resistance of the bidirectional threshold switch in the closed phase based on the change relationship model, and using the maximum absolute value of the differential resistance as the resistance threshold of the line resistance.

[0039] In the semiconductor device testing method of the present embodiment, a current-voltage relationship model of a bidirectional threshold switch in the off phase is obtained to obtain a relationship model of the absolute value of the differential resistance of the bidirectional threshold switch in the off phase with voltage, thereby obtaining the maximum absolute value of the differential resistance. This maximum absolute value of the differential resistance is then used as the resistance threshold of the line resistance. Excessive line resistance can cause the current of the corresponding bidirectional threshold switch to remain at a minimum constant current value during the off phase, resulting in the bidirectional threshold switch not being able to fully shut down or requiring a change in electrical operation to shut down. The bidirectional threshold switch resistance changes nonlinearly during the off phase, and the shrinkage of the defect cluster during the off phase causes the bidirectional threshold switch to have a maximum absolute value of differential resistance, i.e., a maximum resistance value. This maximum resistance value can reduce the current. When the resistance threshold of the line resistance is equal to the maximum resistance value, this maximum resistance value can just compensate for the minimum constant current value caused by the large line resistance, thereby reducing this minimum constant current value to zero within a specific time, causing the bidirectional threshold switch to fully shut down. Therefore, when the line resistance is within a range less than or equal to the resistance threshold, the bidirectional threshold switches in all memory cells can be fully shut down within a specific time without affecting the operational consistency of the memory cell array.

[0040] The following describes the semiconductor device testing method provided by the embodiment of the present application with reference to the accompanying drawings.

[0041] See also Figure 2 and Figure 3 , Figure 2 is a schematic diagram of the three-dimensional structure of a semiconductor device provided in some embodiments of the present application, Figure 3 yes Figure 2 Schematic diagram of the top view structure of the semiconductor device.

[0042] The semiconductor device includes a plurality of first conductive lines L1, a plurality of second conductive lines L2, and a plurality of memory cells MC arranged in an array. Each memory cell MC is connected between one of the first conductive lines L1 and one of the second conductive lines L2. The conductive paths connecting the memory cells MC and the corresponding first and second conductive lines L1 and L2 in series have different line resistances. This line resistance is the total resistance of the first and second conductive lines L1 and L2 in the conductive path, and is related to the total length of the first and second conductive lines L1 and L2 in the conductive path.

[0043] In some embodiments, the first conductive line L1 may be a bit line BL, and the second conductive line L2 may be a word line WL. The semiconductor device comprises, from bottom to top (along a first direction Z), a bit line BL, a memory cell MC, and a word line WL. The memory cell MC is located between the bit line BL and the word line WL, and each memory cell MC is located at the intersection of a bit line BL and a word line WL. From bottom to top, the memory cell MC comprises a first electrode BE, a bidirectional threshold switch OTS, and a second electrode TE. The first direction Z represents the stacking direction of the film layers, the second direction X represents the extension direction of the bit line BL, and the third direction Y represents the extension direction of the word line WL. The first direction Z, the second direction X, and the third direction Y may be perpendicular to each other.

[0044] In some embodiments, the material of the bidirectional threshold switch OTS may include a chalcogenide, the chalcogenide including at least one of a compound of arsenic (As), selenium (Se) and germanium (Ge), a compound of AsSeGe and silicon (Si), a compound of AsSeGeSi and indium (In), and a compound of AsSeGe and indium (In).

[0045] It should be noted that Figure 2 Only memory is selected for testing using the semiconductor device. The semiconductor device in this application may also be other types of memory, such as phase change memory, etc., and this application does not limit this.

[0046] like Figure 3 As shown, the semiconductor device further includes a word line contact WLCT and a bit line contact BLCT, wherein the word line contact WLCT is connected to the word line WL, and the bit line contact BLCT is connected to the bit line BL. Figure 3 The diagram primarily shows the distribution of word lines WL, bit lines BL, word line contacts WLCT, and bit line contacts BLCT. During the operation of a memory cell MC, current can sequentially pass through a word line driver (not shown), word line contact WLCT, word line WL, memory cell MC, bit line BL, bit line contact BLCT, and bit line driver (not shown). It can be seen that memory cells MC at different locations have different distances from the word line contacts WLCT and bit line contacts BLCT. Therefore, memory cells MC at farther locations require longer word lines WL and / or bit lines BL to drive them. Consequently, memory cells MC at different locations have different line resistances in the conductive paths connected in series with the bit lines BL and word lines WL. It is understandable that the farther the distance between a memory cell MC and the word line contacts WLCT and bit line contacts BLCT, the greater the line resistance in the conductive path. Therefore, by measuring the line resistance threshold using the test method provided in the embodiments of the present application, the maximum line resistance supported in the array can be obtained, thereby determining the range of line resistance.

[0047] Experimental research has found that when the line resistance is low, the total differential resistance of the device drops to zero, completely shutting down the OTS device. This is because low line resistance helps quickly shut off current flow, preventing it from being dispersed into other high-resistance paths, reducing leakage and achieving rapid shutdown. When the line resistance is too high, the resistance of the dominant current path increases, but the leakage current path may remain relatively stable, causing the current in the bidirectional threshold switch to remain at a minimum constant current value during the shutdown process. This can prevent the bidirectional threshold switch from fully shutting off, or require a change in electrical operation to shut it off.

[0048] See also Figure 4 and Figure 5 , Figure 4 is a flow chart of a semiconductor device testing method provided in some embodiments of the present application. Figure 5 This is a relationship model of the change in current and voltage of a semiconductor device during testing provided by some embodiments of the present application. The testing method includes the following steps S1 to S3.

[0049] Step S1: obtaining a current-voltage relationship model of the bidirectional threshold switch to be tested in a closed phase. In the closed phase, the current and voltage of the bidirectional threshold switch are negatively correlated, and the resistance of the bidirectional threshold switch changes nonlinearly.

[0050] It is understood that the bidirectional threshold switch to be tested is Figure 1 The bidirectional threshold switch OTS in the embodiment of the present invention can reflect the line resistance requirements of the memory cell MC array through the electrical test data of the bidirectional threshold switch.

[0051] In some embodiments, a method for obtaining a current-voltage relationship model of the bidirectional threshold switch to be tested in the off stage may include: applying a first bias voltage to both sides of the bidirectional threshold switch to put the bidirectional threshold switch in the on stage; after applying the first bias voltage, applying a second bias voltage to both sides of the bidirectional threshold switch to put the bidirectional threshold switch from the on stage to the off stage; and obtaining the current corresponding to the second bias voltage in the off stage to obtain the current-voltage relationship model.

[0052] The two sides of the bidirectional threshold switch refer to the two sides in the thickness direction thereof, that is, the two sides where the first electrode BE and the second electrode TE in the memory cell MC are connected to the bidirectional threshold switch.

[0053] The method of applying a first bias voltage to both sides of the bidirectional threshold switch may include: applying the first bias voltage to both sides of the bidirectional threshold switch, wherein the first bias voltage is greater than the threshold voltage of the bidirectional threshold switch, so that the bidirectional threshold switch enters the conduction stage; and reducing the first bias voltage to a holding voltage so that the bidirectional threshold switch maintains the conduction stage.

[0054] like Figure 5 As shown, when the first bias voltage reaches the threshold voltage Vth of the bidirectional threshold switch (e.g., 4.8V), the resistance of the bidirectional threshold switch is in a low-resistance state, the current flowing through the bidirectional threshold switch increases, and the bidirectional threshold switch enters the on-phase. As the first bias voltage decreases (referred to as the flyback process), the current first increases and then suddenly decreases, while the bidirectional threshold switch remains in the on-phase. When the first bias voltage decreases to the holding voltage Vhold (e.g., 2.5V), the current decreases to the holding current Ihold. Therefore, the on-phase is the period when the first bias voltage decreases from the threshold voltage Vth to Vhold.

[0055] The method of applying a second bias voltage to both sides of the bidirectional threshold switch may include: applying a second bias voltage to both sides of the bidirectional threshold switch, wherein the second bias voltage increases from the holding voltage so that the bidirectional threshold switch enters the closing stage; wherein, in the closing stage, the current of the bidirectional threshold switch decreases, and the current of the bidirectional threshold switch changes nonlinearly with the increase of the second bias voltage.

[0056] In some embodiments, a direction of the second bias voltage is consistent with a direction of the first bias voltage.

[0057] like Figure 5 As shown, as the second bias voltage gradually increases from the holding voltage Vhold, the current gradually decreases (i.e., the current of the bidirectional threshold switch is negatively correlated with the voltage). The period from the holding voltage Vhold onward (when the current decreases from the holding current Ihold to 0) is the off phase. Specifically, the current changes nonlinearly with the increase of the second bias voltage, and therefore, the resistance of the bidirectional threshold switch changes nonlinearly during the off phase.

[0058] In some embodiments, the bidirectional threshold switch is already in the on-stage, and a second bias voltage may be directly applied to both sides of the bidirectional threshold switch to cause the bidirectional threshold switch to enter the off-stage from the on-stage.

[0059] By making the bidirectional threshold switch enter the off stage through the above voltage operation, the second bias voltage and the corresponding current in the off stage can be obtained, thereby obtaining a current-voltage relationship model of the bidirectional threshold switch in the off stage.

[0060] See also Figure 6 , Figure 6 yes Figure 5 Current-voltage relationship model of the bidirectional threshold switch in the off stage.

[0061] In some embodiments, the shutdown phase includes a turn-off phase and a discharge phase, and the second bias voltage includes a cut-off voltage and a turn-off voltage.

[0062] The turn-off stage refers to the stage when the device transitions from the on state (low resistance state) to the off state (high resistance state). In this stage, the current gradually decreases from the holding current to the cut-off current.

[0063] The discharge phase occurs when the device has fully transitioned from the on state to the off state. The current gradually decreases from the cutoff current to zero, leaving the device in a high-resistance state and virtually no longer conducting current. The discharge phase can also be considered the process of dissipating residual charge or energy in the circuit. The current gradually decreases until it stops completely, ensuring a stable off-state. Current changes during this phase are typically minimal because the device is already in a high-resistance state, primarily to eliminate any residual leakage current.

[0064] The method of applying a second bias voltage to both sides of the bidirectional threshold switch may include: applying a second bias voltage to both sides of the bidirectional threshold switch, wherein the second bias voltage increases from the holding voltage to the cut-off voltage, causing the bidirectional threshold switch to enter the turn-off phase, wherein the absolute value of the differential resistance of the bidirectional threshold switch first increases and then decreases during the turn-off phase; and after the cut-off voltage, increasing the second bias voltage until reaching a discharge voltage, causing the bidirectional threshold switch to enter the discharge phase from the turn-off phase, wherein the differential resistance of the bidirectional threshold switch remains unchanged during the discharge phase.

[0065] like Figure 6 As shown, the stage in which the second bias voltage increases from the holding voltage Vhold to the cut-off voltage Vcut_off (e.g., 2.65V) is the turn-off stage, and the stage in which the second bias voltage increases from the cut-off voltage Vcut_off to the discharge voltage Vdisgarge (e.g., 3.1V) is the discharge stage. In the turn-off stage, since the current decreases with the increase of voltage (the current decreases from the holding current Ihold to the discharge current Icut_off), the differential resistance is negative, and the differential resistance changes nonlinearly, so the turn-off stage can be called the nonlinear resistance change stage. In the discharge stage, the differential resistance remains unchanged, so the current changes linearly with the current. After a relaxation time, the voltage increases from the cut-off voltage Vcut_off to the discharge voltage Vdisgarge, and the current decreases from the discharge current Icut_off to 0, and the bidirectional threshold switch is completely turned off.

[0066] In some embodiments, the method of obtaining the current corresponding to the second bias voltage in the shutdown phase to obtain the current-voltage relationship model includes: obtaining the current corresponding to the second bias voltage in the shutdown phase to obtain a first relationship model of current variation with voltage, as the current-voltage relationship model.

[0067] Since the maximum absolute value of the differential resistance of the bidirectional threshold switch is in the off stage, the first relationship model in the off stage can be used as the current-voltage relationship model of the bidirectional threshold switch to obtain the maximum absolute value of the differential resistance according to the current-voltage model.

[0068] Step S2: According to the current-voltage relationship model, a relationship model of the absolute value of the differential resistance of the bidirectional threshold switch in the closed stage versus the voltage is obtained.

[0069] See also Figure 7 , Figure 7 is based on Figure 6 The obtained relationship model of the absolute value of the differential resistance of the bidirectional threshold switch in the off stage as a inverse of the voltage is obtained.

[0070] A method for obtaining a relationship model of the absolute value of the differential resistance of the bidirectional threshold switch in the closed phase as a inverse function of the voltage according to the current-voltage relationship model includes: obtaining the instantaneous resistance corresponding to each voltage in the current-voltage relationship model, wherein the instantaneous resistance is a negative value; and obtaining the absolute value of the differential resistance according to the instantaneous resistance.

[0071] In some embodiments, the instantaneous resistance, that is, the differential resistance, can be obtained according to the current-voltage relationship model using formula (1).

[0072] Rdif=δV / δI (1).

[0073] Step S3: according to the change relationship model, obtaining the maximum absolute value of the differential resistance of the bidirectional threshold switch in the closed stage, and using the maximum absolute value of the differential resistance as the resistance threshold of the line resistance.

[0074] The method for obtaining the maximum absolute value of the differential resistance of the bidirectional threshold switch in the closing stage according to the change relationship model includes: obtaining a second relationship model in which the absolute value of the differential resistance changes with the voltage in the turn-off stage according to the first relationship model (or the current-voltage relationship model); and obtaining the maximum absolute value of the differential resistance according to the peak value of the second relationship model.

[0075] It can be understood that the minimum constant current caused by the line resistance is the discharge current Icut_off. In the off phase, the defect cluster in the bidirectional threshold switch will undergo a transformation. The shrinkage of the defect cluster will cause the conductive path to decrease, thereby increasing the resistance and making the absolute value of the differential resistance reach a maximum. In other words, the absolute value of the differential resistance reaches its maximum value usually when the defect cluster is completely shrunk and the conductive path is the least. If the absolute value of the maximum differential resistance can compensate for this minimum constant current, the current can be reduced to 0, that is, the OTS can be completely turned off. Since this minimum constant current is caused by the line resistance, the absolute value of the maximum differential resistance can compensate for this minimum constant current, that is, when the absolute value of the maximum differential resistance is equal to the line resistance. When the line resistance is greater than the absolute value of the maximum differential resistance, the differential resistance of the bidirectional threshold switch will not be able to compensate for the influence of the line resistance, resulting in a sudden change in the holding voltage and current of the device and affecting the device characteristics.

[0076] like Figure 7 As shown, as the voltage increases, the absolute value of the differential resistance |Rdif| is fitted to obtain a curve showing the absolute value of the differential resistance. The overall trend of the absolute value of the differential resistance |Rdif| is to first increase and then decrease, so the peak of the second relationship model is the maximum absolute value of the differential resistance |Rdif|. For example, if the maximum absolute value of the differential resistance |Rdif| is 25 kilo-ohms, the resistance threshold of the line resistance can be determined to be 25 kilo-ohms. Therefore, the maximum line resistance supported by the memory cell MC array is in the range of 0 to 25 kilo-ohms. In other words, the line resistance in the conductive path of the memory cell MC farthest from the word line contact WLCT and the bit line contact BLCT cannot exceed 25 kilo-ohms, or in other words, the maximum line resistance tolerance of the bidirectional threshold switch OTS (or memory cell MC) is 25 kilo-ohms. This maintains the electrical characteristics of the memory cell MC and, consequently, the operational consistency of the memory cell MC array. Furthermore, measuring the array's tolerance to line resistance is beneficial for array design (e.g., size) and device electrical performance optimization.

[0077] This test method eliminates the need for extensive electrical data measurements to determine the line resistance threshold. Instead, the semiconductor device's line resistance requirements can be calculated using a current-voltage relationship model (IV curve). This simplifies the test process and eliminates the influence of other factors, improving measurement accuracy. Furthermore, this method uses the intrinsic differential resistance characteristics of the bidirectional threshold switch (OTS) (the transition characteristics during the off phase) to determine the array line resistance range. Therefore, the results obtained using this method are more representative and better reflect the correlation between the electrical characteristics of the bidirectional threshold switch (OTS) and the line resistance.

[0078] See also Figures 8 to 10 , Figure 8is a flow chart of a method for obtaining a current-voltage relationship model of the bidirectional threshold switch to be tested in the closed phase, provided in some embodiments of the present application. Figure 9 is a schematic diagram of the structure of the test circuit provided in some embodiments of the present application, Figure 10 This is a relationship model of the current and voltage changes of the test circuit provided in some embodiments of the present application during the test process.

[0079] The method for obtaining the current-voltage relationship model of the bidirectional threshold switch OTS to be tested in the off phase in step S1 may include the following steps S11 to S13.

[0080] Step S11 : forming a test circuit, wherein the test circuit includes the bidirectional threshold switch OTS to be tested and a resistance element R coupled to the bidirectional threshold switch OTS.

[0081] The structure of the test circuit is as follows Figure 9 As shown, the bidirectional threshold switch OTS to be tested is connected in series with the resistor element R. By applying a bias voltage to both ends of the test circuit, the current value can be measured, thereby obtaining Figure 10 The gray curve in the figure is the relationship model between the current flow and voltage change of the test circuit.

[0082] It is understandable that the bidirectional threshold switch OTS to be tested is also Figure 1 The bidirectional threshold switch OTS of the memory cell MC in the semiconductor device is measured, so the bidirectional threshold switch OTS to be tested depends on the material of the bidirectional threshold switch OTS of the memory cell MC in the semiconductor device. Since different semiconductor devices can use different bidirectional threshold switch OTS materials, Figure 9 The material of the bidirectional threshold switch OTS to be tested can be Figure 5 The materials of the bidirectional threshold switch OTS to be tested are different.

[0083] Step S12: obtaining an initial current-voltage relationship model of the test circuit when the bidirectional threshold switch OTS is in the off stage.

[0084] like Figure 10As shown, the gray curve represents the relationship model of the current change with the voltage of the test circuit during the test process. When the bias voltage at both ends of the test circuit (equivalent to the first bias voltage in the above embodiment) reaches the threshold voltage Vth, the test circuit (or the bidirectional threshold switch OTS) enters the conduction stage, the bidirectional threshold switch OTS is in a low resistance state, and the current suddenly increases. As the bias voltage decreases (called the retrace process), the current gradually decreases, but still maintains the conduction stage. When the bias voltage is reduced to the holding voltage Vhold, the current is reduced to the holding current Ihold. Therefore, the conduction stage is the stage between the bias voltage from the threshold voltage Vth to the holding voltage Vhold (i.e., the retrace process). When the bias voltage is the holding voltage Vhold, the current suddenly decreases, the bidirectional threshold switch OTS changes from a low resistance state to a high resistance state, and the bidirectional threshold switch OTS enters the off stage. Therefore, based on the relationship model of the current change with the voltage of the test circuit during the test process, the initial current-voltage relationship model of the test circuit when the bidirectional threshold switch OTS is in the off stage can be obtained. In other words, the initial current-voltage relationship model is Figure 10 The part of the relationship model in the closing phase (Ihold to 0).

[0085] Step S13: obtaining a current-voltage relationship model of the bidirectional threshold switch OTS in the off phase according to the initial current-voltage relationship model and the resistance value of the resistor R.

[0086] In some embodiments, the bias voltage on both sides of the bidirectional threshold switch OTS can be calculated according to formula (2), and then the current-voltage relationship model corresponding to the bidirectional threshold switch OTS and the initial current-voltage relationship model can be obtained based on the bias voltage and current on both sides of the bidirectional threshold switch OTS.

[0087] VOTS=VOTS+RI*R (2).

[0088] in, Figure 10 The black curve in FIG represents the relationship model of the current and voltage variation of the bidirectional threshold switch OTS, which is obtained by the above formula (2) and the relationship model of the current and voltage variation of the test circuit (gray curve).

[0089] It can be seen that Figure 10 The relationship model of the current and voltage variation of the bidirectional threshold switch OTS in Figure 5 The trend of the relationship model of the current and voltage variation of the bidirectional threshold switch OTS is consistent. Figure 10 The current-voltage relationship model of the bidirectional threshold switch OTS in the off stage is Figure 5 The changing trend of the current-voltage relationship model of the bidirectional threshold switch OTS in the off stage is consistent, that is, starting from the holding voltage Vhold, the current decreases as the voltage increases.

[0090] See also Figure 11 , Figure 11 yes Figure 10 The current-voltage relationship model of the bidirectional threshold switch in the off stage. The bidirectional threshold switch OTS also undergoes a turn-off stage (Vhold / Ihold to Vcut_off / Icut_off) and a discharge stage (Vcut_off / Icut_off to Vdischarge / 0) in the off stage. Moreover, the current and voltage change nonlinearly in the turn-off stage, so the differential resistance also changes nonlinearly. Figure 11 According to the current-voltage relationship model in the embodiment, the maximum absolute value of the differential resistance |Rdif| of the bidirectional threshold switch OTS in the off phase is obtained through the above steps S2 and S3, and the maximum absolute value of the differential resistance |Rdif| is used as the resistance threshold of the line resistance.

[0091] It should be noted that Figure 11 The current-voltage relationship model in Figure 6 The current-voltage relationship model in the Figure 11 The bidirectional threshold switch OTS tested in Figure 6 The materials of the bidirectional threshold switches OTS tested in the experiment are different.

[0092] Based on the semiconductor device testing method provided in the above embodiment, the embodiment of the present application further provides a semiconductor device testing device, which is described in detail below with reference to the accompanying drawings.

[0093] See also Figure 12 , Figure 12 This is a schematic structural diagram of a semiconductor device testing device provided in some embodiments of the present application.

[0094] The semiconductor device testing device 100 includes a testing module 10 , a first acquisition module 20 , and a second acquisition module 30 . The first acquisition module 20 is connected to the testing module 10 , and the second acquisition module 30 is connected to the testing module 10 .

[0095] The test module 10 is used to obtain a current-voltage relationship model of the bidirectional threshold switch to be tested in the off stage. In the off stage, the current and voltage of the bidirectional threshold switch are negatively correlated, and the resistance of the bidirectional threshold switch changes nonlinearly.

[0096] The first acquisition module 20 is configured to acquire a relationship model of a change in the absolute value of the differential resistance of the bidirectional threshold switch in the closing phase with respect to the voltage according to the current-voltage relationship model.

[0097] The second acquisition module 30 is configured to acquire a maximum absolute value of differential resistance of the bidirectional threshold switch in the off stage according to the change relationship model, and use the maximum absolute value of differential resistance as a resistance threshold of the line resistance.

[0098] In some embodiments, the first acquisition module 20 includes a first acquisition unit 21 and a second acquisition unit 22, wherein the second acquisition unit 22 is connected to the first acquisition unit 21. The first acquisition unit 21 is configured to acquire the instantaneous resistance corresponding to each voltage in the current-voltage relationship model, where the instantaneous resistance is a negative value. The second acquisition unit 22 is configured to acquire the absolute value of the differential resistance based on the instantaneous resistance.

[0099] Based on the semiconductor device testing method provided in the above embodiments, an embodiment of the present application also provides an electronic device, which includes a memory, a processor, and a computer program stored in the memory and running on the processor. When the processor executes the computer program, the steps of the testing method in any of the above embodiments are implemented.

[0100] The memory may include read-only memory and random access memory, and provides instructions and data to the processor. A portion of the memory may also include NVRAM. The memory stores an operating system and operating instructions, executable modules, or data structures, or subsets or extended sets thereof. The operating instructions may include various operating instructions for implementing various operations. The operating system may include various system programs for implementing various basic services and processing hardware-based tasks.

[0101] The number of processors can be one or more. In some embodiments, the processor and memory can be connected via a bus or other means. The processor controls the operation of the terminal device and the processor can also be called a CPU.

[0102] The test methods disclosed in the above embodiments of the present application can be applied to or implemented by a processor. The processor can be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method can be completed by hardware integrated logic circuits in the processor or by software instructions. The above processor can be a general-purpose processor, a DSP, an ASIC, an FPGA, or other programmable logic device, a discrete gate or transistor logic device, or a discrete hardware component. The various methods, steps, and logic block diagrams disclosed in the embodiments of the present application can be implemented or executed. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of the present application can be directly implemented and executed by a hardware decoding processor, or by a combination of hardware and software modules in the decoding processor. The software module can be located in a storage medium well-known in the art, such as random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, etc. The storage medium is located in the memory, and the processor reads the information in the memory and, in conjunction with its hardware, completes the steps of the above method.

[0103] An embodiment of the present application further provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the steps of the testing method in any of the above embodiments are implemented.

[0104] It should be noted that the computer-readable storage medium mentioned above in this application can be a computer-readable signal medium or a computer-readable storage medium or any combination of the above. The computer-readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or component, or any combination of the above. More specific examples of computer-readable storage media can include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM) or flash memory, an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In this application, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, device or device. In this application, a computer-readable signal medium can include a data signal propagated in baseband or as part of a carrier wave, which carries computer-readable program code. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium may also be any computer-readable storage medium other than a computer-readable storage medium that can send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, apparatus, or device. The program code contained on a computer-readable storage medium may be transmitted using any suitable medium, including but not limited to wires, optical cables, radio frequency (RF), etc., or any suitable combination thereof.

[0105] The computer-readable storage medium may be included in the electronic device, or may exist independently without being incorporated into the electronic device.

[0106] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0107] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0108] The embodiments, implementation methods and related technical features of the present application can be combined and replaced with each other without conflict.

[0109] The above are merely preferred embodiments of the present application and do not constitute any form of limitation to the present application. However, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. A method for testing a semiconductor device, characterized in that: The semiconductor device includes a plurality of first conductive lines, a plurality of second conductive lines, and a plurality of memory cells distributed in an array, each of the memory cells being connected between one of the first conductive lines and one of the second conductive lines, each of the memory cells having a different line resistance in a conductive path connected in series with the corresponding first conductive line and the corresponding second conductive line, and the memory cells including bidirectional threshold switches. The semiconductor device testing method includes: Obtaining a current-voltage relationship model of the bidirectional threshold switch to be tested in a closed phase, wherein in the closed phase, the current and voltage of the bidirectional threshold switch are negatively correlated, and the resistance of the bidirectional threshold switch changes nonlinearly; According to the current-voltage relationship model, a relationship model of a change in the absolute value of the differential resistance of the bidirectional threshold switch in the closed phase with respect to the voltage is obtained; According to the change relationship model, the maximum absolute value of the differential resistance of the bidirectional threshold switch in the closed stage is obtained, and the maximum absolute value of the differential resistance is used as the resistance threshold of the line resistance.

2. The method for testing a semiconductor device according to claim 1, wherein: The method for obtaining a current-voltage relationship model of the bidirectional threshold switch to be tested in a closed phase includes: Applying a first bias voltage to both sides of the bidirectional threshold switch to put the bidirectional threshold switch into a conduction stage; After applying the first bias voltage, applying a second bias voltage to both sides of the bidirectional threshold switch to make the bidirectional threshold switch enter the off stage from the on stage; A current corresponding to the second bias voltage in the off phase is obtained to obtain the current-voltage relationship model.

3. The method for testing a semiconductor device according to claim 2, wherein: The method of applying a first bias voltage to both sides of the bidirectional threshold switch includes: Applying the first bias voltage to both sides of the bidirectional threshold switch, where the first bias voltage is greater than the threshold voltage of the bidirectional threshold switch, so that the bidirectional threshold switch enters the conduction stage; The first bias voltage is reduced to a holding voltage, so that the bidirectional threshold switch remains in the on-state.

4. The method for testing a semiconductor device according to claim 3, wherein: The method of applying a second bias voltage to both sides of the bidirectional threshold switch includes: Applying a second bias voltage to both sides of the bidirectional threshold switch, wherein the second bias voltage increases from the holding voltage, so that the bidirectional threshold switch enters the closing stage; In the closing phase, the current of the bidirectional threshold switch decreases, and the current of the bidirectional threshold switch changes nonlinearly with the increase of the second bias voltage.

5. The semiconductor device testing method according to any one of claims 1 to 4, characterized in that: The method for obtaining a relationship model of a change in the absolute value of the differential resistance of the bidirectional threshold switch in the off phase with voltage based on the current-voltage relationship model includes: Obtaining an instantaneous resistance corresponding to each voltage in the current-voltage relationship model, where the instantaneous resistance is a negative value; The absolute value of the differential resistance is obtained according to the instantaneous resistance.

6. The method for testing a semiconductor device according to claim 3, wherein: The closing phase includes a shut-off phase and a discharge phase, and the second bias voltage includes a cut-off voltage and a shut-off voltage; The method of applying a second bias voltage to both sides of the bidirectional threshold switch includes: applying a second bias voltage to both sides of the bidirectional threshold switch, wherein the second bias voltage increases from the holding voltage to a cut-off voltage, causing the bidirectional threshold switch to enter the off phase, wherein the absolute value of the differential resistance of the bidirectional threshold switch first increases and then decreases during the off phase; After the cut-off voltage, the second bias voltage is increased until it reaches a discharge voltage, so that the bidirectional threshold switch enters the discharge phase from the turn-off phase. In the discharge phase, the differential resistance of the bidirectional threshold switch remains unchanged.

7. The method for testing a semiconductor device according to claim 6, wherein: The method of obtaining the current corresponding to the second bias voltage in the off phase to obtain the current-voltage relationship model includes: Acquiring the current corresponding to the second bias voltage in the turn-off phase to obtain a first relationship model of current and voltage variation as the current-voltage relationship model; The method for obtaining the maximum absolute value of the differential resistance of the bidirectional threshold switch in the off stage according to the change relationship model includes: According to the first relationship model, a second relationship model is obtained in which the absolute value of the differential resistance changes with the voltage in the shutdown phase; The maximum differential resistance absolute value is obtained according to a peak value of the second relationship model.

8. The method for testing a semiconductor device according to claim 1, wherein: The method for obtaining a current-voltage relationship model of the bidirectional threshold switch to be tested in a closed phase includes: forming a test circuit, the test circuit comprising the bidirectional threshold switch to be tested and a resistance element coupled to the bidirectional threshold switch; Obtaining an initial current-voltage relationship model of the test circuit when the bidirectional threshold switch is in a closed stage; A current-voltage relationship model of the bidirectional threshold switch in the closing phase is obtained according to the initial current-voltage relationship model and the resistance value of the resistor element.

9. A semiconductor device testing device, characterized in that: The semiconductor device includes a plurality of first conductive lines, a plurality of second conductive lines, and a plurality of memory cells distributed in an array, each of the memory cells being connected between one of the first conductive lines and one of the second conductive lines, each of the memory cells having a different line resistance in a conductive path connected in series with the corresponding first conductive line and the corresponding second conductive line, and the memory cells including bidirectional threshold switches; and a test device for the semiconductor device including: a testing module, configured to obtain a current-voltage relationship model of the bidirectional threshold switch to be tested in a closed phase, wherein in the closed phase, the current and voltage of the bidirectional threshold switch are negatively correlated, and the resistance of the bidirectional threshold switch changes nonlinearly; A first acquisition module is configured to acquire a relationship model of a difference in absolute value of the differential resistance of the bidirectional threshold switch in the closed phase with respect to voltage according to the current-voltage relationship model; The second acquisition module is configured to acquire a maximum absolute value of differential resistance of the bidirectional threshold switch in the closed phase according to the change relationship model, and use the maximum absolute value of differential resistance as a resistance threshold of the line resistance.

10. The semiconductor device testing device according to claim 9, wherein: The first acquisition module includes: A first acquiring unit is configured to acquire an instantaneous resistance corresponding to each voltage in the current-voltage relationship model, wherein the instantaneous resistance is a negative value; A second acquiring unit is configured to acquire an absolute value of the differential resistance according to the instantaneous resistance.

11. An electronic device comprising a memory, a processor, and a computer program stored in the memory and running on the processor, characterized in that: When the processor executes the computer program, the steps of the testing method according to any one of claims 1 to 8 are implemented.

12. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the testing method according to any one of claims 1 to 8 are implemented.

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