Band gap device and starting circuit thereof

Abstract

The invention provides a band gap device and a starting circuit thereof. The starting circuit comprises a first transistor, a delay circuit, a second transistor, a switching circuit and a starting switch. The control ends of the first transistor and the second transistor are controlled by the internal bias voltage of the band gap circuit. The delay circuit is coupled to the first transistor. The switching circuit is coupled to the second transistor. The switch circuit is controlled by the delay circuit. The control end of the starting switch is coupled to the second transistor and the switching circuit. At a power-on instant of the bandgap circuit, the start-up switch is turned on to provide a start-up bias to an internal start-up node of the bandgap circuit. After the band-gap circuit is started, the internal bias voltage of the band-gap circuit cuts off the starting switch, the first transistor and the second transistor, so that the starting circuit does not consume current.

Description

Technical Field

[0001] The present invention relates to an electronic device, and more particularly to a bandgap device and a start-up circuit thereof. Background Art

[0002] With the development of electronic circuit technology, electronic devices are required to have low power consumption and low latency functions. When an electronic device is idle, multiple circuits in the electronic device (such as bandgap circuits) enter a power saving mode to reduce standby power consumption. When the idle period ends, all circuits in the electronic device (such as bandgap circuits) are expected to start up quickly to enter normal working conditions. A bandgap circuit is a circuit used to generate a stable reference voltage. It can output a highly stable, low-noise reference voltage and is not affected by temperature changes. Therefore, bandgap circuits have been widely used in many precision electronic devices, such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and sensor measurement systems. The startup time of the bandgap circuit often affects the startup speed of the electronic device. Summary of the Invention

[0003] The present invention is directed to a bandgap device and a start-up circuit thereof, so as to start the bandgap circuit.

[0004] In an embodiment of the present invention, the startup circuit is used to start a bandgap circuit. The startup circuit includes a first transistor, a delay circuit, a second transistor, a switch circuit, and a first startup switch. A first terminal of the first transistor is coupled to a first voltage. A control terminal of the first transistor is controlled by a first internal bias voltage of the bandgap circuit. A first terminal of the delay circuit is coupled to a second terminal of the first transistor. A second terminal of the delay circuit is coupled to a second voltage. A first terminal of the second transistor is coupled to a third voltage. A control terminal of the second transistor is controlled by the second internal bias voltage of the bandgap circuit. A first terminal of the switch circuit is coupled to a second terminal of the second transistor. A second terminal of the switch circuit is coupled to a fourth voltage. A control terminal of the switch circuit is controlled by an output terminal of the delay circuit. A first terminal of the first startup switch is coupled to a fifth voltage. A second terminal of the first startup switch is coupled to a first internal startup node of the bandgap circuit. A control terminal of the first startup switch is coupled to the second terminal of the second transistor and the first terminal of the switch circuit.

[0005] In an embodiment according to the present invention, the bandgap device includes a bandgap circuit and a startup circuit. The bandgap circuit is configured to provide a bandgap voltage. The startup circuit is coupled to the bandgap circuit. The startup circuit is configured to start the bandgap circuit. The startup circuit includes a first transistor, a delay circuit, a second transistor, a switch circuit, and a first startup switch. A first terminal of the first transistor is coupled to a first voltage. A control terminal of the first transistor is controlled by a first internal bias voltage of the bandgap circuit. A first terminal of the delay circuit is coupled to a second terminal of the first transistor. A second terminal of the delay circuit is coupled to a second voltage. A first terminal of the second transistor is coupled to a third voltage. A control terminal of the second transistor is controlled by the second internal bias voltage of the bandgap circuit. A first terminal of the switch circuit is coupled to a second terminal of the second transistor. A second terminal of the switch circuit is coupled to a fourth voltage. A control terminal of the switch circuit is controlled by an output terminal of the delay circuit. A first terminal of the first startup switch is coupled to a fifth voltage. A second terminal of the first startup switch is coupled to a first internal startup node of the bandgap circuit. A control terminal of the first startup switch is coupled to the second terminal of the second transistor and the first terminal of the switch circuit.

[0006] Based on the above, at the moment the bandgap circuit is powered on, the second transistor and the switch circuit can turn on the startup switch to provide a startup bias voltage (bias current or bias voltage) to the internal startup node of the bandgap circuit, allowing the bandgap circuit to start quickly. After the bandgap circuit completes startup, the internal bias voltage of the bandgap circuit can turn off the startup switch, the first transistor, and the second transistor. Therefore, the startup circuit does not consume current after the bandgap circuit completes startup. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 FIG. 1 is a circuit block diagram of a bandgap device according to an embodiment of the present invention.

[0008] Figure 2 FIG. 4 is a circuit block diagram of a bandgap device according to another embodiment of the present invention.

[0009] Figure 3 FIG. 1 is a circuit block diagram of a bandgap circuit and a startup circuit according to an embodiment of the present invention.

[0010] Figure 4 FIG. 1 is a circuit block diagram of a bandgap circuit and a startup circuit according to another embodiment of the present invention.

[0011] Description of Reference Numerals

[0012] 100, 200: Bandgap devices

[0013] 311, 411: Delay circuit

[0014] 312, 412: Switching circuit

[0015] AMP3, AMP4: amplifier circuit

[0016] B31, B32, MN31, MN32, MN33, MN34, MN41, MN42, MN47, MN48, MN49, MN410, MP31, MP32, MP37, MP38, MP39, MP310, MP311, MP41, MP42, MP43, MP44, MP45: Transistors

[0017] BGC1, BGC2, BGC3, BGC4: Bandgap circuits

[0018] C31, C41: capacitors

[0019] GNDA: reference voltage

[0020] Ibg, Ibias: startup bias current

[0021] MN43, MP33, MP34: Start switch

[0022] MN46, MP36: switching transistors

[0023] R31, R41: current limiting resistors

[0024] R32, R33, R34, R42, R43, R44: resistors

[0025] SBC3, SBC4: Self-bias circuit

[0026] STR1, STR2, STR3, STR4: Startup circuit

[0027] SW2, MN45, MP35: output switch

[0028] VBG1, VBG2: bandgap reference voltage

[0029] Vb3: internal bias voltage

[0030] Vbias3, Vbias4: bias voltage

[0031] VCCA: supply voltage

[0032] VLP2: Control signal

[0033] VLP3, VLP4: output voltage

[0034] Vout: startup bias voltage

[0035] Vstart3, Vstart4: Start signal

[0036] Vstop3, Vstop4: start stop signal DETAILED DESCRIPTION

[0037] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0038] The term "coupled (or connected)" used in the entire text of this application specification (including the claims) may refer to any direct or indirect means of connection. For example, if the text describes a first device coupled (or connected) to a second device, it should be interpreted that the first device can be directly connected to the second device, or the first device can be indirectly connected to the second device through other devices or some connection means. The terms "first", "second", etc. mentioned in the entire text of this application specification (including the claims) are used to name the components (element) or to distinguish different embodiments or scopes, and are not used to limit the upper or lower limit of the number of components, nor to limit the order of components. In addition, wherever possible, components / members / steps with the same numbers in the drawings and embodiments represent the same or similar parts. Components / members / steps with the same numbers or the same terms in different embodiments can refer to the relevant descriptions of each other.

[0039] Figure 1 FIG. 1 is a circuit block diagram of a bandgap device 100 according to an embodiment of the present invention. Figure 1 The illustrated bandgap device 100 includes a bandgap circuit BGC1 and a start-up circuit STR1. Bandgap circuit BGC1 is configured to provide a bandgap voltage VBG1. Bandgap circuit BGC1 is a circuit for generating a stable reference voltage. Bandgap circuit BGC1 can output a highly stable, low-noise bandgap reference voltage VBG1 that is unaffected by temperature fluctuations. This embodiment does not limit the specific implementation of bandgap circuit BGC1. For example, based on actual design, bandgap circuit BGC1 may include an ultra-low power self-bias bandgap circuit, a well-known bandgap circuit, or other bandgap circuits.

[0040] The startup circuit STR1 is coupled to the bandgap circuit BGC1. If the system has a low-power consumption function, when the system is idle, multiple circuits in the system (such as the bandgap circuit BGC1) can enter a power-saving mode to reduce standby power consumption. When the idle period ends, all circuits in the system (such as the bandgap circuit BGC1) are expected to quickly start up and enter normal operation. The startup circuit STR1 can start the bandgap circuit BGC1. At the moment the bandgap circuit is powered on, the startup circuit STR1 can immediately start the bandgap circuit BGC1. After the bandgap circuit completes startup, the startup circuit STR1 can be disabled, so that the startup circuit does not consume current after the bandgap circuit completes startup. Specific implementation examples of the startup circuit STR1 will be described in multiple embodiments later.

[0041] Figure 2 FIG. 2 is a circuit block diagram of a bandgap device 200 according to another embodiment of the present invention. Figure 2 The bandgap device 200 shown includes a bandgap circuit BGC2 , a startup circuit STR2 , and an output switch SW2 . Figure 2 The bandgap device 200, the bandgap circuit BGC2 and the startup circuit STR2 can refer to Figure 1 The relevant descriptions of the bandgap device 100, the bandgap circuit BGC1 and the startup circuit STR1 are not repeated here. Figure 2 In the illustrated embodiment, startup circuit STR2 can control output switch SW2 via control signal VLP2. During the startup transient following the power-on transient, output switch STR2 is turned off to prevent overshoot of bandgap circuit BGC2 during the startup process. After the startup transient, when the startup is complete, output switch SW2 is turned on, enabling bandgap circuit BGC2 to output a highly stable, low-noise bandgap reference voltage VBG2. Specific implementation examples of startup circuit STR2 will be described in various embodiments later in this article.

[0042] Figure 3 FIG. 1 is a circuit block diagram of a bandgap circuit BGC3 and a start-up circuit STR3 according to an embodiment of the present invention. Figure 3 The bandgap circuit BGC3 and the startup circuit STR3 shown can be used as Figure 2 The bandgap circuit BGC2 and the start-up circuit STR2 are one of the many implementation examples shown, or as Figure 1 The illustrated embodiment shows one of many implementation examples of the bandgap circuit BGC1 and the startup circuit STR1. Figure 3 The bandgap circuit BGC3 and the startup circuit STR3 shown can refer to Figure 2 The bandgap circuit BGC2 and the startup circuit STR2 (or Figure 1The relevant descriptions of the bandgap circuit BGC1 and the startup circuit STR1 are given and can be deduced by analogy.

[0043] exist Figure 3 In the illustrated embodiment, the startup circuit STR3 includes a delay circuit 311 , a switch circuit 312 , a transistor MP31 , a transistor MP32 , a startup switch MP33 , a startup switch MP34 , and an output switch MP35 . Figure 3 The output switch MP35 shown can be used as Figure 2 One of many implementation examples of the output switch SW2 is shown. Figure 3 The transistor MP31, the transistor MP32, the start switch MP33, the start switch MP34, or the output switch MP35 may include a metal-oxide-semiconductor (MOS) transistor or other types of transistors. For example, any of the transistor MP31, the transistor MP32, the start switch MP33, the start switch MP34, and the output switch MP35 may be a p-type metal-oxide semiconductor (PMOS) transistor.

[0044] The first terminal (e.g., source) of transistor MP31 is coupled to a first voltage (e.g., power supply voltage VCCA). The actual level of power supply voltage VCCA can be determined according to actual design. The control terminal (e.g., gate) of transistor MP31 is controlled by a first internal bias voltage (e.g., bias voltage Vbias3) of bandgap circuit BGC3. The first terminal of delay circuit 311 is coupled to the second terminal (e.g., drain) of transistor MP31. The second terminal of delay circuit 311 is coupled to a second voltage (e.g., reference voltage GNDA). The actual level of reference voltage GNDA can be determined according to actual design, such as 0V or other voltage levels. Figure 3 In the illustrated embodiment, the delay circuit 311 includes a current-limiting resistor R31 and a capacitor C31. A first terminal of the current-limiting resistor R31 is coupled to a second terminal of the transistor MP31. A second terminal of the current-limiting resistor R31 is coupled to a control terminal of the switch circuit 312 to provide a start-stop signal Vstop3. A first terminal of the capacitor C31 is coupled to a second terminal of the current-limiting resistor R31. A second terminal of the capacitor C31 is coupled to a second voltage (e.g., a reference voltage GNDA).

[0045] A first terminal (e.g., source) of transistor MP32 is coupled to a third voltage (e.g., power supply voltage VCCA). A control terminal (e.g., gate) of transistor MP32 is controlled by a second internal bias voltage (e.g., bias voltage Vbias3) of bandgap circuit BGC3. A first terminal of switch circuit 312 is coupled to a second terminal (e.g., drain) of transistor MP32. A second terminal of switch circuit 312 is coupled to a fourth voltage (e.g., reference voltage GNDA). A control terminal of switch circuit 312 is controlled by a start / stop signal Vstop3 at the output terminal of delay circuit 311. Figure 3 In the illustrated embodiment, the switch circuit 312 includes a switch transistor MP36 and a resistor R32 . Figure 3 The switching transistor MP36 shown can include a MOS transistor or other types of transistors. For example, the switching transistor MP36 can be a PMOS transistor. A first terminal (e.g., source) of the switching transistor MP36 is coupled to the second terminal of the transistor MP32. A control terminal (e.g., gate) of the switching transistor MP36 is controlled by the start / stop signal Vstop3 at the output of the delay circuit 311. A first terminal of the resistor R32 is coupled to a second terminal (e.g., drain) of the switching transistor MP36. A second terminal of the resistor R32 is coupled to a fourth voltage (e.g., reference voltage GNDA).

[0046] A first terminal of the startup switch MP33 is coupled to the power supply voltage VCCA. A second terminal of the startup switch MP33 is coupled to an internal startup node of the bandgap circuit BGC3 to provide a startup bias current Ibg during startup. A control terminal of the startup switch MP33 is coupled to the second terminal of the transistor MP32 and the first terminal of the switch circuit 312 to receive a startup start signal Vstart3. A first terminal of the startup switch MP34 is coupled to the power supply voltage VCCA. A second terminal of the startup switch MP34 is coupled to another internal startup node of the bandgap circuit BGC3 to provide a startup bias current Ibias during startup. A control terminal of the startup switch MP34 is coupled to the second terminal of the transistor MP32 and the first terminal of the switch circuit 312 to receive the startup start signal Vstart3. A first terminal of the output switch MP35 is coupled to the output terminal of the bandgap circuit BGC3. A control terminal of the output switch MP35 is controlled by the output voltage VLP3 of the switch circuit 312.

[0047] exist Figure 3In the illustrated embodiment, bandgap circuit BGC3 includes amplifier circuit AMP3, self-bias circuit SBC3, transistor MP37, resistor R33, transistor B31, transistor MP38, resistor R34, and transistor B32. A first terminal (e.g., source) of transistor MP37 is coupled to a sixth voltage (e.g., power supply voltage VCCA). A second terminal (e.g., drain) of transistor MP37 is coupled to a first input terminal of amplifier circuit AMP3. A control terminal (e.g., gate) of transistor MP37 is coupled to an output terminal of amplifier circuit AMP3. A first terminal of resistor R33 is coupled to a second terminal of transistor MP37. A first terminal (e.g., emitter) of transistor B31 is coupled to a second terminal of resistor R33. A second terminal (e.g., collector) of transistor B31 is coupled to a seventh voltage (e.g., reference voltage GNDA). A control terminal (e.g., base) of transistor B31 is coupled to an eighth voltage (e.g., reference voltage GNDA).

[0048] The internal bias voltage used to control transistors MP31 and MP32 is the output voltage of the output terminal of the amplifier circuit AMP3 ( Figure 3 The bias voltage Vbias3 is shown. Figure 3 In the illustrated embodiment, the amplifier circuit AMP3 includes a transistor MP39 , a transistor MP310 , a transistor MN31 , a transistor MN32 , and a transistor MN33 . Figure 3The transistors MP39, MP310, MN31, MN32, or MN33 shown may include MOS transistors or other types of transistors. For example, any of transistors MP39 and MP310 may be PMOS transistors, while any of transistors MN31, MN32, and MN33 may be n-type metal oxide semiconductor (NMOS) transistors. A first terminal (e.g., source) of transistor MP39 is coupled to a twelfth voltage (e.g., power supply voltage VCCA). A control terminal (e.g., gate) of transistor MP39 is coupled to a second terminal (e.g., drain) of transistor MP39. A first terminal (e.g., drain) of transistor MN31 is coupled to a second terminal of transistor MP39. A control terminal (e.g., gate) of transistor MN31 is coupled to a first input terminal of amplifier circuit AMP3. A first terminal (e.g., source) of transistor MP310 is coupled to a thirteenth voltage (e.g., power supply voltage VCCA). A second terminal (e.g., drain) of transistor MP310 is coupled to an output terminal of amplifier circuit AMP3. The control terminal (e.g., gate) of transistor MP310 is coupled to the second terminal of transistor MP39. The first terminal (e.g., drain) of transistor MN32 is coupled to the second terminal of transistor MP310. The control terminal (e.g., gate) of transistor MN32 is coupled to the second input terminal of amplifier circuit AMP3. The first terminal (e.g., drain) of transistor MN33 is coupled to the second terminal (e.g., source) of transistor MN31 and the second terminal (e.g., source) of transistor MN32. The second terminal (e.g., source) of transistor MN33 is coupled to a fourteenth voltage (e.g., reference voltage GNDA). The control terminal (e.g., gate) of transistor MN33 is controlled by an internal bias voltage ( Figure 3 The bias voltage Vb3 is shown).

[0049] A first terminal (e.g., source) of transistor MP38 is coupled to a ninth voltage (e.g., power supply voltage VCCA). A second terminal (e.g., drain) of transistor MP38 is coupled to the output terminal of bandgap circuit BGC3 to provide bandgap voltage VBG. A control terminal (e.g., gate) of transistor MP38 is coupled to the output terminal of amplifier circuit AMP3. A first terminal of resistor R34 is coupled to the second terminal of transistor MP38. A second terminal of resistor R34 is coupled to the second input terminal of amplifier circuit AMP3. An internal startup node, to which a second terminal of startup switch MP34 is coupled, is coupled to the first terminal of resistor R34 and the second terminal of transistor MP38. A first terminal (e.g., emitter) of transistor B32 is coupled to the second terminal of resistor R34. A second terminal (e.g., collector) of transistor B32 is coupled to a tenth voltage (e.g., reference voltage GNDA). A control terminal (e.g., base) of transistor B32 is coupled to an eleventh voltage (e.g., reference voltage GNDA). An input terminal of self-bias circuit SBC3 is coupled to the output terminal of amplifier circuit AMP3. An output terminal of the self-bias circuit SBC3 is coupled to a bias terminal of the amplifier circuit AMP3 to provide an internal bias voltage Vb3 .

[0050] exist Figure 3 In the illustrated embodiment, the self-bias circuit SBC3 includes a transistor MP311 and a transistor MN34 . Figure 3 The transistor MP311 or MN34 shown may include a MOS transistor or another type of transistor. For example, the transistor MP311 may be a PMOS transistor, and the transistor MN34 may be an NMOS transistor. A first terminal (e.g., source) of the transistor MP311 is coupled to a twelfth voltage (e.g., power supply voltage VCCA). A second terminal (e.g., drain) of the transistor MP311 is coupled to the output terminal of the self-bias circuit SBC3. A control terminal (e.g., gate) of the transistor MP311 is coupled to the input terminal of the self-bias circuit SBC3. A first terminal (e.g., drain) of the transistor MN34 is coupled to the second terminal of the transistor MP311. A second terminal (e.g., source) of the transistor MN34 is coupled to a thirteenth voltage (e.g., reference voltage GNDA). A control terminal (e.g., gate) of the transistor MN34 is coupled to the first terminal of the transistor MN34. The internal startup node to which the second terminal of the startup switch MP33 is coupled is coupled to the second terminal of the transistor MP311 and the first terminal of the transistor MN34.

[0051] At the power-up instant of bandgap circuit BGC3 (when power supply voltage VCCA goes from a low level to a high level), transistors MP31 and MP32 are turned off, and start-stop signal Vstop3 is initially at a low level. Consequently, switch circuit 312 is turned on, causing start-start signal Vstart3 to be at a low level. This in turn turns start switches MP33 and MP34 on, providing a start-up bias voltage (start-up bias currents Ibg and Ibias) to the internal start node of bandgap circuit BGC3.

[0052] At the startup instant after the power-on instant, switching transistor MP36 (switch circuit 312), transistor MP31, and transistor MP32 are turned on. As self-bias circuit SBC3 activates, the bias voltage Vbias3 decreases, gradually turning on transistors MP31 and MP32. Turning on transistor MP32 causes startup start signal Vstart3 and the output voltage VLP3 of switch circuit 312 to increase, turning off startup switches MP33, MP34, and output switch MP35. The turned-off startup switches MP33 and MP34 stop providing startup bias (startup bias currents Ibg and Ibias) to the internal startup node of bandgap circuit BGC3, thereby preventing interference with the normal operation of bandgap circuit BGC3. The turned-off output switch MP35 prevents overshoot of the output of bandgap circuit BGC3 during startup.

[0053] Transistor MP31 charges capacitor C31 through current-limiting resistor R31, causing the level of start-stop signal Vstop3 to gradually increase. The level of start-stop signal Vstop3 eventually rises to a level close to power supply voltage VCCA, turning off switching transistor MP36. Because switching transistor MP36 is off, transistor MP32 can pull up the level of start-start signal Vstart3 to a level close to power supply voltage VCCA, and resistor R32 can pull down the output voltage VLP3 of switch circuit 312 to a level close to reference voltage GNDA. At the startup completion time after the startup instant, switch circuit 312, start switch MP33, and start switch MP34 are turned off. Because bandgap circuit BGC3 has completed startup, transistors MP31 and MP32 are turned off. The low-level output voltage VLP3 turns on output switch MP35, thereby preventing interference with the normal output of bandgap circuit BGC3.

[0054] In summary, at the moment bandgap circuit BGC3 is powered on, transistor MP32 and switch circuit 312 can turn on startup switches MP33 and MP34 to provide a startup bias voltage (startup bias currents Ibg and Ibias) to the internal startup node of bandgap circuit BGC3, enabling rapid startup of bandgap circuit BGC3. After bandgap circuit BGC3 completes startup, internal bias voltage Vbias3 of bandgap circuit BGC3 can turn off transistors MP31 and MP32, and startup switches MP33 and MP34 can remain off. Therefore, startup circuit STR3 consumes no current after bandgap circuit BGC3 completes startup.

[0055] Figure 4 FIG. 1 is a circuit block diagram of a bandgap circuit BGC4 and a start-up circuit STR4 according to another embodiment of the present invention. Figure 4 The bandgap circuit BGC4 and the startup circuit STR4 shown can be used as Figure 2 The bandgap circuit BGC2 and the start-up circuit STR2 are one of the many implementation examples shown, or as Figure 1 The illustrated embodiment shows one of many implementation examples of the bandgap circuit BGC1 and the startup circuit STR1. Figure 4 The bandgap circuit BGC4 and the startup circuit STR4 shown can refer to Figure 2 The bandgap circuit BGC2 and the startup circuit STR2 (or Figure 1 The relevant descriptions of the bandgap circuit BGC1 and the startup circuit STR1 are given and can be deduced by analogy.

[0056] exist Figure 4 In the illustrated embodiment, the startup circuit STR4 includes a delay circuit 411 , a switch circuit 412 , a transistor MN41 , a transistor MN42 , a startup switch MN43 , and an output switch MN45 . Figure 4 The output switch MN45 shown can be used as Figure 2 One of many implementation examples of the output switch SW2 is shown. Figure 4 The transistor MN41, the transistor MN42, the start switch MN43 or the output switch MN45 may include MOS transistors or other types of transistors. For example, any of the transistor MN41, the transistor MN42, the start switch MN43 and the output switch MN45 may be an NMOS transistor.

[0057] A first terminal (e.g., source) of transistor MN41 is coupled to a first voltage (e.g., reference voltage GNDA). A control terminal (e.g., gate) of transistor MN41 is controlled by a first internal bias voltage (e.g., bias voltage Vbias4) of bandgap circuit BGC4. A first terminal of delay circuit 411 is coupled to a second terminal (e.g., drain) of transistor MN41. A second terminal of delay circuit 411 is coupled to a second voltage (e.g., power supply voltage VCCA). Figure 4 In the illustrated embodiment, the delay circuit 411 includes a current-limiting resistor R41 and a capacitor C41. A first terminal of the current-limiting resistor R41 is coupled to a second terminal of the transistor MN41. A second terminal of the current-limiting resistor R41 is coupled to a control terminal of the switch circuit 412 to provide a start-stop signal Vstop4. A first terminal of the capacitor C41 is coupled to a second terminal of the current-limiting resistor R41. A second terminal of the capacitor C41 is coupled to a second voltage (e.g., a power supply voltage VCCA).

[0058] A first terminal (e.g., source) of transistor MN42 is coupled to a third voltage (e.g., reference voltage GNDA). A control terminal (e.g., gate) of transistor MN42 is controlled by a second internal bias voltage (e.g., bias voltage Vbias4) of bandgap circuit BGC4. A first terminal of switch circuit 412 is coupled to a second terminal (e.g., drain) of transistor MN42. A second terminal of switch circuit 412 is coupled to a fourth voltage (e.g., power supply voltage VCCA). A control terminal of switch circuit 412 is controlled by a start / stop signal Vstop4 at the output terminal of delay circuit 411. Figure 4 In the illustrated embodiment, the switch circuit 412 includes a switch transistor MN46 and a resistor R42 . Figure 4 The illustrated switching transistor MN46 may include a MOS transistor or other types of transistors. For example, the switching transistor MN46 may be an NMOS transistor. A first terminal (e.g., source) of the switching transistor MN46 is coupled to a second terminal of the transistor MN42. A control terminal (e.g., gate) of the switching transistor MN46 is controlled by a start / stop signal Vstop4 at the output of the delay circuit 411. A first terminal of the resistor R42 is coupled to a second terminal (e.g., drain) of the switching transistor MN46. A second terminal of the resistor R42 is coupled to a fourth voltage (e.g., power supply voltage VCCA).

[0059] A first terminal of the start-up switch MN43 is coupled to a reference voltage GNDA. A second terminal of the start-up switch MN43 is coupled to an internal start-up node of the bandgap circuit BGC4 to provide a start-up bias voltage Vout during startup. A control terminal of the start-up switch MN43 is coupled to the second terminal of the transistor MN42 and the first terminal of the switch circuit 412 to receive a startup start signal Vstart4. A first terminal of the output switch MN45 is coupled to the output terminal of the bandgap circuit BGC4. A control terminal of the output switch MN45 is controlled by the output voltage VLP4 of the switch circuit 412.

[0060] exist Figure 4 In the illustrated embodiment, bandgap circuit BGC4 includes amplifier circuit AMP4, self-bias circuit SBC4, transistor MP41, resistor R43, transistor B41, transistor MP42, resistor R44, and transistor B42. A first terminal (e.g., source) of transistor MP41 is coupled to a sixth voltage (e.g., power supply voltage VCCA). A second terminal (e.g., drain) of transistor MP41 is coupled to a first input terminal of amplifier circuit AMP4. A control terminal (e.g., gate) of transistor MP41 is coupled to an output terminal of amplifier circuit AMP4. An internal start node, to which a second terminal of start switch MN43 is coupled, is coupled to the control terminal of transistor MP41. A first terminal of resistor R43 is coupled to a second terminal of transistor MP41. A first terminal (e.g., emitter) of transistor B41 is coupled to a second terminal of resistor R43. A second terminal (e.g., collector) of transistor B41 is coupled to a seventh voltage (e.g., reference voltage GNDA). A control terminal (e.g., base) of transistor B41 is coupled to an eighth voltage (e.g., reference voltage GNDA).

[0061] exist Figure 4 In the illustrated embodiment, the amplifier circuit AMP4 includes a transistor MP43 , a transistor MP44 , a transistor MN47 , a transistor MN48 , and a transistor MN49 . Figure 4The transistors MP43, MP44, MN47, MN48, or MN49 shown may include MOS transistors or other types of transistors. For example, any of transistors MP43 and MP44 may be a PMOS transistor, while any of transistors MN47, MN48, and MN49 may be an NMOS transistor. A first terminal (e.g., source) of transistor MP43 is coupled to a twelfth voltage (e.g., power supply voltage VCCA). A control terminal (e.g., gate) of transistor MP43 is coupled to a second terminal (e.g., drain) of transistor MP43. A first terminal (e.g., drain) of transistor MN47 is coupled to a second terminal of transistor MP43. A control terminal (e.g., gate) of transistor MN47 is coupled to a first input terminal of amplifier circuit AMP4. A first terminal (e.g., source) of transistor MP44 is coupled to a thirteenth voltage (e.g., power supply voltage VCCA). A second terminal (e.g., drain) of transistor MP44 is coupled to an output terminal of amplifier circuit AMP4. A control terminal (e.g., gate) of transistor MP44 is coupled to a second terminal of transistor MP43. A first terminal (e.g., drain) of transistor MN48 is coupled to a second terminal of transistor MP44. A control terminal (e.g., gate) of transistor MN48 is coupled to a second input terminal of amplifier circuit AMP4. A first terminal (e.g., drain) of transistor MN49 is coupled to a second terminal (e.g., source) of transistor MN47 and a second terminal (e.g., source) of transistor MN48. A second terminal (e.g., source) of transistor MN49 is coupled to a fourteenth voltage (e.g., reference voltage GNDA). A control terminal (e.g., gate) of transistor MN49 is controlled by an internal bias voltage ( Figure 4 The bias voltage Vbias4 is shown).

[0062] A first terminal (e.g., source) of transistor MP42 is coupled to a ninth voltage (e.g., power supply voltage VCCA). A second terminal (e.g., drain) of transistor MP42 is coupled to the output terminal of bandgap circuit BGC3 to provide bandgap voltage VBG. A control terminal (e.g., gate) of transistor MP42 is coupled to the output terminal of amplifier circuit AMP4. An internal start node, to which a second terminal of start switch MN43 is coupled, is coupled to the control terminal of transistor MP42. A first terminal of resistor R44 is coupled to the second terminal of transistor MP42. A second terminal of resistor R44 is coupled to the second input terminal of amplifier circuit AMP4. A first terminal (e.g., emitter) of transistor B42 is coupled to the second terminal of resistor R34. A second terminal (e.g., collector) of transistor B42 is coupled to a tenth voltage (e.g., reference voltage GNDA). A control terminal (e.g., base) of transistor B42 is coupled to an eleventh voltage (e.g., reference voltage GNDA). An input terminal of self-bias circuit SBC4 is coupled to the output terminal of amplifier circuit AMP4. The internal start node to which the second terminal of the start switch MN43 is coupled is coupled to the input terminal of the self-bias circuit SBC4. The output terminal of the self-bias circuit SBC4 is coupled to the bias terminal of the amplifier circuit AMP4 to provide an internal bias voltage Vbias4. The internal bias voltage used to control the transistors MN41 and MN42 is the internal bias voltage (Vbias4) at the output terminal of the self-bias circuit SBC4. Figure 4 The bias voltage Vbias4 is shown).

[0063] exist Figure 4 In the illustrated embodiment, the self-bias circuit SBC4 includes a transistor MP45 and a transistor MN410 . Figure 4 The transistor MP45 or MN410 shown may include a MOS transistor or another type of transistor. For example, the transistor MP45 may be a PMOS transistor, while the transistor MN410 may be an NMOS transistor. A first terminal (e.g., source) of the transistor MP45 is coupled to a twelfth voltage (e.g., power supply voltage VCCA). A second terminal (e.g., drain) of the transistor MP45 is coupled to the output terminal of the self-bias circuit SBC4. A control terminal (e.g., gate) of the transistor MP45 is coupled to the input terminal of the self-bias circuit SBC4. A first terminal (e.g., drain) of the transistor MN410 is coupled to a second terminal of the transistor MP45. A second terminal (e.g., source) of the transistor MN410 is coupled to a thirteenth voltage (e.g., reference voltage GNDA). A control terminal (e.g., gate) of the transistor MN410 is coupled to a first terminal of the transistor MN410.

[0064] At the power-on instant of bandgap circuit BGC4 (the instant when power supply voltage VCCA goes from a low level to a high level), transistors MN41 and MN42 are turned off, and the start-stop signal Vstop4 is initially at a high level. Consequently, switch circuit 412 is turned on, causing start-start signal Vstart4 to go high, which in turn turns on start switch MN43, providing a start-up bias voltage (start-up bias voltage Vout) to the internal start node of bandgap circuit BGC4. Consequently, bandgap circuit BGC4 and self-bias circuit SBC4 can be activated. At the startup instant after the power-on instant, switch transistor MN46 (switch circuit 412), transistor MN41, and transistor MN42 are turned on. As self-bias circuit SBC4 activates, the level of bias voltage Vbias4 rises, gradually turning on transistors MN41 and MN42. Turning on transistor MN42 causes start-start signal Vstart4 and output voltage VLP4 of switch circuit 412 to drop, turning off start switch MN43 and output switch MN45. The turned-off startup switch MN43 stops providing the startup bias voltage (startup bias voltage Vout) to the internal startup node of the bandgap circuit BGC4, thereby preventing normal operation of the bandgap circuit BGC4. The turned-off output switch MN45 blocks any overshoot in the output of the bandgap circuit BGC4 during startup.

[0065] Transistor MN41 discharges capacitor C41 through current-limiting resistor R41, gradually decreasing the level of start-stop signal Vstop4. The level of start-stop signal Vstop4 eventually drops to a level close to reference voltage GNDA, turning off switching transistor MN46. Because switching transistor MN46 is off, transistor MN42 can pull down the level of start-start signal Vstart4 to a level close to reference voltage GNDA, and resistor R42 can pull up the output voltage VLP4 of switch circuit 412 to a level close to power supply voltage VCCA. At the startup completion time after the startup instant, switch circuit 412 and start switch MN43 are turned off. Because bandgap circuit BGC4 has completed startup, transistors MN41 and MN42 are turned off. The low-level output voltage VLP4 turns on output switch MN45, thereby preventing interference with the normal output of bandgap circuit BGC4.

[0066] In summary, at the moment bandgap circuit BGC4 is powered on, transistor MN42 and switch circuit 412 can turn on startup switch MN43 to provide a startup bias voltage (startup bias voltage Vout) to the internal startup node of bandgap circuit BGC4, enabling rapid startup of bandgap circuit BGC4. After bandgap circuit BGC4 completes startup, internal bias voltage Vbias4 of bandgap circuit BGC4 can turn off transistors MN41 and MN42, and startup switch MN43 can remain off. Therefore, startup circuit STR4 consumes no current after bandgap circuit BGC4 completes startup.

[0067] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A startup circuit for starting a bandgap circuit, characterized in that: The startup circuit comprises: a first transistor, wherein a first terminal of the first transistor is coupled to a first voltage, and a control terminal of the first transistor is controlled by a first internal bias voltage of the bandgap circuit; a delay circuit, wherein a first terminal of the delay circuit is coupled to the second terminal of the first transistor, and a second terminal of the delay circuit is coupled to a second voltage; a second transistor, wherein a first terminal of the second transistor is coupled to a third voltage, and a control terminal of the second transistor is controlled by a second internal bias voltage of the bandgap circuit; a switch circuit, wherein a first terminal of the switch circuit is coupled to the second terminal of the second transistor, a second terminal of the switch circuit is coupled to a fourth voltage, and a control terminal of the switch circuit is controlled by the output terminal of the delay circuit; and a first startup switch, wherein a first terminal of the first startup switch is coupled to a fifth voltage, a second terminal of the first startup switch is coupled to a first internal startup node of the bandgap circuit, and a control terminal of the first startup switch is coupled to the second terminal of the second transistor and the first terminal of the switch circuit.

2. The starting circuit according to claim 1, characterized in that: At a power-on instant of the bandgap circuit, the first transistor and the second transistor are turned off, and the switch circuit and the first startup switch are turned on to provide a startup bias voltage to the first internal startup node of the bandgap circuit; At a startup instant after the power-on instant, the first transistor, the second transistor, and the switch circuit are turned on, and the first startup switch is turned off to stop providing the startup bias voltage to the first internal startup node of the bandgap circuit; as well as At a startup completion time after the startup instant time, the switch circuit and the first startup switch are turned off, and the bandgap circuit completes startup so that the first transistor and the second transistor are turned off.

3. The starting circuit according to claim 1, wherein: The startup circuit further includes: An output switch, wherein a first terminal of the output switch is coupled to the output terminal of the bandgap circuit, and a control terminal of the output switch is controlled by an output voltage of the switch circuit.

4. The starting circuit according to claim 3, characterized in that: At a startup instant after a power-on instant, the output switch is turned off to block an overshoot output of the bandgap circuit; and At the startup completion time after the startup instant time, the output switch is turned on.

5. The starting circuit according to claim 1, wherein: The startup circuit further includes: a second startup switch, wherein a first terminal of the second startup switch is coupled to a sixth voltage, a second terminal of the second startup switch is coupled to a second internal startup node of the bandgap circuit, and a control terminal of the second startup switch is coupled to the second terminal of the second transistor and the first terminal of the switch circuit.

6. The starting circuit according to claim 5, characterized in that: At a power-on instant of the bandgap circuit, the second startup switch is turned on to provide a startup bias voltage to the second internal startup node of the bandgap circuit; At a startup instant after the power-on instant, the second startup switch is turned off to stop providing the startup bias voltage to the second internal startup node of the bandgap circuit; as well as At the startup completion time after the startup instant time, the second startup switch is turned off.

7. The starting circuit according to claim 1, characterized in that: The delay circuit comprises: a current limiting resistor, wherein a first end of the current limiting resistor is coupled to the second end of the first transistor, and a second end of the current limiting resistor is coupled to the control end of the switch circuit; and A capacitor, wherein a first terminal of the capacitor is coupled to the second terminal of the current limiting resistor, and a second terminal of the capacitor is coupled to the second voltage.

8. The starting circuit according to claim 1, wherein: The switching circuit comprises: a switch transistor, wherein a first terminal of the switch transistor is coupled to the second terminal of the second transistor, and a control terminal of the switch transistor is controlled by the output terminal of the delay circuit; and A resistor, wherein a first terminal of the resistor is coupled to the second terminal of the switch transistor, and a second terminal of the resistor is coupled to the fourth voltage.

9. A bandgap device, characterized in that The bandgap device comprises: a bandgap circuit for providing a bandgap voltage; and a startup circuit, coupled to the bandgap circuit, for starting the bandgap circuit, wherein the startup circuit comprises: a first transistor, wherein a first terminal of the first transistor is coupled to a first voltage, and a control terminal of the first transistor is controlled by a first internal bias voltage of the bandgap circuit; a delay circuit, wherein a first terminal of the delay circuit is coupled to the second terminal of the first transistor, and a second terminal of the delay circuit is coupled to a second voltage; a second transistor, wherein a first terminal of the second transistor is coupled to a third voltage, and a control terminal of the second transistor is controlled by a second internal bias voltage of the bandgap circuit; a switch circuit, wherein a first terminal of the switch circuit is coupled to the second terminal of the second transistor, a second terminal of the switch circuit is coupled to a fourth voltage, and a control terminal of the switch circuit is controlled by the output terminal of the delay circuit; and a first startup switch, wherein a first terminal of the first startup switch is coupled to a fifth voltage, a second terminal of the first startup switch is coupled to a first internal startup node of the bandgap circuit, and a control terminal of the first startup switch is coupled to the second terminal of the second transistor and the first terminal of the switch circuit.

10. The bandgap device according to claim 9, wherein: At a power-on instant of the bandgap circuit, the first transistor and the second transistor are turned off, and the switch circuit and the first startup switch are turned on to provide a startup bias voltage to the first internal startup node of the bandgap circuit; At a startup instant after the power-on instant, the first transistor, the second transistor, and the switch circuit are turned on, and the first startup switch is turned off to stop providing the startup bias voltage to the first internal startup node of the bandgap circuit; as well as At a startup completion time after the startup instant time, the switch circuit and the first startup switch are turned off, and the bandgap circuit completes startup so that the first transistor and the second transistor are turned off.

11. The bandgap device according to claim 9, wherein The startup circuit further includes: An output switch, wherein a first terminal of the output switch is coupled to the output terminal of the bandgap circuit, and a control terminal of the output switch is controlled by an output voltage of the switch circuit.

12. The bandgap device according to claim 11, wherein At a startup instant after a power-on instant, the output switch is turned off to block an overshoot output of the bandgap circuit; and At the startup completion time after the startup instant time, the output switch is turned on.

13. The bandgap device according to claim 9, wherein The startup circuit further includes: a second startup switch, wherein a first terminal of the second startup switch is coupled to a sixth voltage, a second terminal of the second startup switch is coupled to a second internal startup node of the bandgap circuit, and a control terminal of the second startup switch is coupled to the second terminal of the second transistor and the first terminal of the switch circuit.

14. The bandgap device according to claim 13, wherein: At a power-on instant of the bandgap circuit, the second startup switch is turned on to provide a startup bias voltage to the second internal startup node of the bandgap circuit; At a startup instant after the power-on instant, the second startup switch is turned off to stop providing the startup bias voltage to the second internal startup node of the bandgap circuit; as well as At the startup completion time after the startup instant time, the second startup switch is turned off.

15. The bandgap device according to claim 9, wherein The delay circuit comprises: a current limiting resistor, wherein a first end of the current limiting resistor is coupled to the second end of the first transistor, and a second end of the current limiting resistor is coupled to the control end of the switch circuit; and A capacitor, wherein a first terminal of the capacitor is coupled to the second terminal of the current limiting resistor, and a second terminal of the capacitor is coupled to the second voltage.

16. The bandgap device according to claim 9, wherein The switching circuit comprises: a switch transistor, wherein a first terminal of the switch transistor is coupled to the second terminal of the second transistor, and a control terminal of the switch transistor is controlled by the output terminal of the delay circuit; and A resistor, wherein a first terminal of the resistor is coupled to the second terminal of the switch transistor, and a second terminal of the resistor is coupled to the fourth voltage.

17. The bandgap device according to claim 9, wherein The bandgap circuit comprises: Amplifier circuit; a third transistor, wherein a first terminal of the third transistor is coupled to a sixth voltage, a second terminal of the third transistor is coupled to the first input terminal of the amplifier circuit, and a control terminal of the third transistor is coupled to the output terminal of the amplifier circuit; a first resistor, wherein a first terminal of the first resistor is coupled to the second terminal of the third transistor; a fourth transistor, wherein a first terminal of the fourth transistor is coupled to the second terminal of the first resistor, a second terminal of the fourth transistor is coupled to a seventh voltage, and a control terminal of the fourth transistor is coupled to an eighth voltage; a fifth transistor, wherein a first terminal of the fifth transistor is coupled to a ninth voltage, a second terminal of the fifth transistor is coupled to an output terminal of the bandgap circuit to provide the bandgap voltage, and a control terminal of the fifth transistor is coupled to the output terminal of the amplifier circuit; a second resistor, wherein a first terminal of the second resistor is coupled to the second terminal of the fifth transistor, and a second terminal of the second resistor is coupled to the second input terminal of the amplifier circuit; and a sixth transistor, wherein a first terminal of the sixth transistor is coupled to the second terminal of the second resistor, a second terminal of the sixth transistor is coupled to a tenth voltage, and a control terminal of the sixth transistor is coupled to an eleventh voltage.

18. The bandgap device according to claim 17, wherein The amplifying circuit comprises: a seventh transistor, wherein a first terminal of the seventh transistor is coupled to a twelfth voltage, and a control terminal of the seventh transistor is coupled to a second terminal of the seventh transistor; an eighth transistor, wherein a first terminal of the eighth transistor is coupled to the second terminal of the seventh transistor, and a control terminal of the eighth transistor is coupled to the first input terminal of the amplifier circuit; a ninth transistor, wherein a first terminal of the ninth transistor is coupled to a thirteenth voltage, a second terminal of the ninth transistor is coupled to the output terminal of the amplifier circuit, and a control terminal of the ninth transistor is coupled to the second terminal of the seventh transistor; a tenth transistor, wherein a first terminal of the tenth transistor is coupled to the second terminal of the ninth transistor, and a control terminal of the tenth transistor is coupled to the second input terminal of the amplifier circuit; and an eleventh transistor, wherein a first terminal of the eleventh transistor is coupled to the second terminal of the eighth transistor and the second terminal of the tenth transistor, a second terminal of the eleventh transistor is coupled to a fourteenth voltage, and a control terminal of the eleventh transistor is controlled by a third internal bias voltage.

19. The bandgap device according to claim 17, wherein The bandgap circuit further includes: The self-bias circuit comprises a self-bias circuit, wherein an input terminal of the self-bias circuit is coupled to the output terminal of the amplifier circuit, and an output terminal of the self-bias circuit is coupled to a bias terminal of the amplifier circuit to provide a third internal bias voltage.

20. The bandgap device according to claim 19, wherein The self-bias circuit comprises: a seventh transistor, wherein a first terminal of the seventh transistor is coupled to a twelfth voltage, a second terminal of the seventh transistor is coupled to the output terminal of the self-bias circuit, and a control terminal of the seventh transistor is coupled to the input terminal of the self-bias circuit; and an eighth transistor, wherein a first terminal of the eighth transistor is coupled to the second terminal of the seventh transistor, a second terminal of the eighth transistor is coupled to a thirteenth voltage, and a control terminal of the eighth transistor is coupled to the first terminal of the eighth transistor.

21. The bandgap device according to claim 20, wherein The first internal bias voltage and the second internal bias voltage are output voltages of the output terminal of the amplifier circuit, and the first internal start-up node is coupled to the second terminal of the seventh transistor and the first terminal of the eighth transistor.

22. The bandgap device according to claim 19, wherein The first internal bias voltage and the second internal bias voltage are the third internal bias voltage of the output terminal of the self-bias circuit, and the first internal start node is coupled to the control terminal of the third transistor and the control terminal of the fifth transistor.

23. The bandgap device according to claim 17, wherein The first internal bias voltage and the second internal bias voltage are output voltages of the output terminal of the amplifier circuit, and the first internal start-up node is coupled to the first terminal of the second resistor and the second terminal of the fifth transistor.

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