Reset monitoring system and method, electronic equipment and storage medium

Abstract

The invention discloses a reset monitoring system and method, electronic equipment and a storage medium, and belongs to the field of integrated circuits. The reset monitoring system comprises a processor used for issuing a reset control instruction and processing alarm information, wherein the reset control instruction comprises timing duration of a timer and reset information of each functional module; the reset control module is used for receiving and verifying a reset control instruction issued by the processor, sending the timing duration of the timer and reset information to the reset monitoring module under the condition that the reset control instruction passes verification, and sending the reset information to each functional module; the function module is used for resetting according to the received resetting information and outputting a resetting state to the resetting monitoring module; and the reset monitoring module is used for starting a timer and monitoring the reset state of each functional module under the condition that the reset control instruction sent by the reset control module is received, and reporting alarm information to the processor under the condition that the reset information is inconsistent with the reset state.

Description

Technical Field

[0001] The present application belongs to the field of integrated circuits, and specifically relates to a reset monitoring system, method, electronic device and storage medium. Background Art

[0002] In the chip, reset control is an essential module. Its function is to ensure that the chip starts working from a certain initial state. The wrong reset value may cause the chip to work abnormally, which in turn affects the entire system. At the same time, there are also failures where the module should be reset but is not reset, affecting the safe operation of the entire system.

[0003] In the related art, reset monitoring mostly uses a timeout counting method. This method is simple, but the monitoring method is not comprehensive and the fault diagnosis coverage is low. Summary of the Invention

[0004] The present application aims to provide a reset monitoring system, method, electronic device and storage medium, which at least solve the problems of incomplete reset monitoring and low fault diagnosis coverage in related technologies.

[0005] In the first aspect, an embodiment of the present application proposes a reset monitoring system, including: a processor, for issuing reset control instructions and processing alarm information, the reset control instructions including the timing duration of a timer and reset information of each functional module; a reset control module, for receiving and verifying the reset control instructions issued by the processor, and when the reset control instructions are verified, sending the timing duration of the timer and the reset information to the reset monitoring module, and sending the reset information to each functional module; a functional module, for resetting according to the received reset information, and outputting the reset status to the reset monitoring module; a reset monitoring module, for starting the timer and monitoring the reset status of each functional module when receiving the reset control instruction sent by the reset control module, and reporting alarm information to the processor when the reset information and the reset status are inconsistent.

[0006] In a second aspect, an embodiment of the present application provides an electronic device, comprising the reset monitoring system as described in the first aspect.

[0007] In the third aspect, an embodiment of the present application provides a reset monitoring method, comprising: upon receiving a reset control instruction issued by a processor, verifying the reset control instruction, wherein the reset control instruction includes the timing duration of a timer and reset information of each functional module; if the reset control instruction passes the verification, sending the reset information to each functional module, and starting a timer to monitor the reset status of each functional module; and reporting an alarm message to the processor when the reset information and the reset status are inconsistent.

[0008] In a fourth aspect, an embodiment of the present application provides a storage medium storing a program or instruction, which, when executed by a processor, implements the steps of the reset monitoring method described in the third aspect.

[0009] In a fifth aspect, an embodiment of the present application provides a program product, which is stored in a storage medium and is executed by at least one processor to implement the steps of the reset monitoring method as described in the third aspect.

[0010] In an embodiment of the present application, the reset monitoring system includes a processor, a reset control module, a functional module and a reset monitoring module, wherein the processor is used to issue reset control instructions and process alarm information, the reset control instructions include the timing duration of the timer and the reset information of each functional module, the reset control module is used to receive and verify the reset control instructions issued by the processor, and when the reset control instruction is verified, the timing duration of the timer and the reset information are sent to the reset monitoring module, and the reset information is sent to each functional module, the functional module is used to reset according to the received reset information, and output the reset status to the reset monitoring module, the reset monitoring module is used to start the timer and monitor the reset status of each functional module when receiving the reset control instruction sent by the reset control module, and report the alarm information to the processor when the reset information and the reset status are inconsistent. The embodiment of the present application verifies the reset control instruction issued by the processor through the reset control module, and issues the reset control instruction to the reset monitoring module and each functional module if the verification passes, thereby ensuring that the received reset information is correct and improving the success rate of the reset. In addition, the reset monitoring module can determine the reset status of each functional module by comparing the reset information with the reset status of each functional module, thereby avoiding the reset of functional modules that do not need to be reset, and improving the fault diagnosis coverage. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a structural diagram of a reset monitoring system provided by an embodiment of the present application; Figure 2 This is a structural block diagram of a reset monitoring system provided by an embodiment of the present application; Figure 3 1 is a flow chart of a reset monitoring method provided by an embodiment of the present application; Figure 4 This is a schematic diagram of a complete reset monitoring process provided by an embodiment of the present application; Figure 5 This is a schematic diagram of the monitoring process in the case of configuration update provided by an embodiment of the present application. DETAILED DESCRIPTION

[0012] The embodiments of the present application will be described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application and are not to be construed as limiting the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present application.

[0013] The terms "first" and "second" in the specification and claims of this application may explicitly or implicitly refer to one or more of the features. Throughout the description of this application, unless otherwise specified, "plurality" means two or more. Furthermore, "and / or" in the specification and claims refers to at least one of the connected entities, and the character " / " generally indicates an "or" relationship between the connected entities.

[0014] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0015] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; and internal connections between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0016] As system-on-chip (SOC) designs trend toward large-scale integration, this poses significant challenges to the stable operation of each functional module within the SOC chip, the real-time monitoring of reset status, and chip area. In related technologies, the operating status of the central processing unit (CPU) is monitored via an external watchdog, while the reset status of many functional modules is not monitored. To improve fault diagnosis coverage, configuration reset information readback is typically used instead of reset status readback. In addition, the reset state is monitored. On the one hand, a cyclic redundancy check (CRC) is used to protect the reset value of each register of each functional module. Although this method can provide high coverage, it is unrealistic and wastes area. The reason is that there are a large number of customized intellectual property (IP) functional modules in the SOC that cannot be modified independently. At the same time, each has a CRC engine, which wastes area and increases power consumption. On the other hand, the monitoring module uses a timer for each reset state, which also increases the area and power consumption. Finally, the relevant technology only monitors whether the reset is complete, but does not cover the failure modes of not being reset when it should be reset or resetting when it should not be reset, thereby reducing the fault diagnosis coverage.

[0017] This application provides a reset monitoring system, method, electronic device, and storage medium. A reset control module verifies the legitimacy of latched reset configuration information and reports the verification results in real time, reducing misconfigurations caused by random hardware failures, improving diagnostic coverage, reducing the frequency of CPU periodic readbacks, and improving CPU utilization. Furthermore, by enabling the reset monitoring module's monitoring, marking the reset configuration information change, and changing bit information, and using only a single timer, the system achieves real-time monitoring of the reset status of multiple functional modules, significantly reducing area and power consumption, improving CPU utilization, and achieving high diagnostic coverage for multiple failure modes.

[0018] The following combination Figures 1 to 5 The reset monitoring system, method, electronic device, and storage medium provided by the embodiments of the present application are described in detail through specific embodiments and their application scenarios. The reset monitoring system can be applied to products such as vehicle-mounted central gateway chips and vehicle-mounted intelligent cockpit chips. It can also be applied to SOC chips with functional safety requirements in industrial, vehicle-mounted, rail transit, and medical applications. The actual application shall prevail and this embodiment does not limit it.

[0019] like Figure 1 As shown in FIG, a structural diagram of a reset monitoring system provided by an embodiment of the present application is provided. Figure 1As shown, the reset monitoring system may include a processor, a reset control module, a functional module, and a reset monitoring module. The processor is configured to issue reset control instructions and process alarm information, wherein the reset control instructions include the timer timing duration and reset information of each functional module; the reset control module is configured to receive and verify the reset control instructions issued by the processor, and if the reset control instructions are verified, the timer timing duration and reset information are sent to the reset monitoring module, and the reset information is sent to each functional module; the functional module is configured to reset according to the received reset information and output the reset status to the reset monitoring module; the reset monitoring module is configured to start the timer and monitor the reset status of each functional module upon receiving the reset control instruction sent by the reset control module, and report alarm information to the processor if the reset information and reset status are inconsistent.

[0020] The processor can be implemented as a high-performance CPU or a general-purpose CPU. The processor and the reset control module can be connected through a bus system, such as Figure 2 As shown, the system bus provides a data transmission path between the processor, storage unit, peripheral subsystems, and Direct Memory Access (DMA) system. It can be implemented using a high-performance Network on Chip (NOC) bus topology, and the communication protocol can adopt high-performance bus protocols such as AMBA's Advanced eXtensible Interface (AXI) and AMBA's Advanced High Performance Bus (AHB). In one example, the system bus can be verified. By verifying the validity of the configuration bus and reporting the verification results in real time, misconfigurations caused by bus interference are reduced, diagnostic coverage is improved, the frequency of CPU periodic readbacks is reduced, and CPU utilization is improved.

[0021] The timer is used to monitor the reset status of each functional module. The reset information can be an instruction for the functional module to reset or not reset. For example, the reset information can be represented by a character string, such as 101110010, where 1 can represent reset and 0 can represent not reset. Each functional module can perform corresponding reset or non-reset operations based on the reset information.

[0022] The reset control module is responsible for receiving reset control instructions issued by the CPU, verifying the legality of the instructions, latching reset information based on legal instructions, and then synchronizing the reset information according to different clock domains and outputting it to the functional modules and reset monitoring module. Reset control instructions can include read and write control signals, address signals, write data signals, etc., and the verification method can be parity check (Parity Check) or other verification methods such as Error Checking and Correcting (ECC). At the same time, it can latch configuration information such as legally passed resets and add a check bit to the latched information. The reset information is then synchronized according to different clock domains and output to the functional modules and reset monitoring module. Information that fails verification is notified to the CPU as an alarm for processing.

[0023] The functional module is responsible for implementing the business functions of the SOC and outputting the reset state. The number of functional modules can be one, two or more, such as the low-latency Controller Area Network (CAN) / Local Interconnect Network (LIN), Inter-Integrated Circuit (I2C), DMA, Random Access Memory (RAM), Double Data Rate Synchronous Dynamic Random Access Memory (DDR), high-speed serial computer expansion bus standard (Peripheral Component Interconnect Express, PCIE) and other Internet Protocol (IP) functional modules and corresponding reset states.

[0024] The reset monitoring module monitors the reset status based on the monitoring enable and related information. This means it starts a timer based on the monitoring enable and monitors the reset status of each functional module. If the reset information and reset status are inconsistent, an alarm is generated and reported to the CPU for processing. Compared to related techniques that only monitor whether the functional module has been fully reset, covering failure modes such as resetting when it should not have been, this application improves fault diagnosis coverage by comparing reset information and reset status.

[0025] In an embodiment of the present application, the reset monitoring system includes a processor, a reset control module, a functional module and a reset monitoring module, wherein the processor is used to issue reset control instructions and process alarm information, the reset control instructions include the timing duration of the timer and the reset information of each functional module, the reset control module is used to receive and verify the reset control instructions issued by the processor, and when the reset control instruction is verified, the timing duration of the timer and the reset information are sent to the reset monitoring module, and the reset information is sent to each functional module, the functional module is used to reset according to the received reset information, and output the reset status to the reset monitoring module, the reset monitoring module is used to start the timer and monitor the reset status of each functional module when receiving the reset control instruction sent by the reset control module, and report the alarm information to the processor when the reset information and the reset status are inconsistent. The embodiment of the present application verifies the reset control instruction issued by the processor through the reset control module, and issues the reset control instruction to the reset monitoring module and each functional module if the verification passes, thereby ensuring that the received reset information is correct and improving the success rate of the reset. In addition, the reset monitoring module can determine the reset status of each functional module by comparing the reset information with the reset status of each functional module, thereby avoiding the reset of functional modules that do not need to be reset, and improving the fault diagnosis coverage.

[0026] In one possible implementation of the present application, the reset monitoring module includes a timer, and the timer is used to monitor each functional module. That is, the present application uses only one timer to monitor all functional modules. Compared to the related art, which configures each functional module with a timer, and the timers are all started and stopped together, the present application can reduce CPU operations, reduce resource waste across the entire system, and reduce the timer's power consumption and the area occupied by the entire system chip.

[0027] In a possible implementation of the present application, when the reset monitoring module receives a configuration update mark, the reset monitoring module generates a mask code based on the configuration update mark, and the mask code is used to mask the function modules with configuration updates, and the configuration update mark is a mark generated when the reset control module receives a new reset control instruction issued by the processor. That is, when the present application receives a new reset control instruction issued by the processor in a monitoring cycle, the function module corresponding to the bit with the configuration update mark can be masked and not monitored to avoid false alarms caused by the reset information that has changed. After the timer expires, that is, after the monitoring cycle ends, all function modules are monitored together based on the configuration update mark. By shielding the function modules with the configuration update mark and continuing to monitor other function modules whose reset information has not changed, the present application can monitor all function modules with only one timer. Reducing the timer can reduce the CPU operations and improve the computing efficiency of the entire system.

[0028] In this embodiment, by resetting the monitoring enable of the monitoring module, resetting the configuration information change mark, changing the bit information and a timer, real-time monitoring of the reset status of multiple functional modules is completed, which greatly reduces the area and power consumption, improves the CPU utilization, and achieves high diagnostic coverage of multiple failure modes.

[0029] In one possible implementation of the present application, when the reset control instruction passes verification, the reset control module generates verification information based on the reset information, adds the verification information to the reset information, and latches the reset information with the verification information added. This embodiment can latch configuration information such as the legally passed reset together with the check bit for subsequent verification to prevent changes in the latched information. The reset information is then synchronized according to different clock domains and output to the functional modules and reset monitoring module. Information about verification failure is notified to the CPU in the form of an alarm for processing.

[0030] In one possible implementation of the present application, the reset control module verifies the latched reset information with added verification information and reports an alarm to the processor if the verification fails. In other words, the reset control module can perform real-time verification of the latched reset information and report an alarm based on the verification result, thereby reducing misconfigurations caused by random hardware failures, improving diagnostic coverage, reducing the frequency of CPU periodic readbacks, and improving CPU utilization.

[0031] The present application also provides an electronic device that can include the reset monitoring system provided by any of the above embodiments and can achieve the same technical effects as the above reset monitoring system. To avoid repetition, it will not be described here.

[0032] like Figure 3 As shown in FIG, a flow chart of a reset monitoring method provided by an embodiment of the present application is provided. The reset control module and the reset monitoring module form a whole as the main body. Figure 3 As shown, the reset monitoring method may include the contents shown in steps 301 to 303.

[0033] S301 : Upon receiving a reset control instruction sent by a processor, verify the reset control instruction, where the reset control instruction includes a timing duration of a timer and reset information of each functional module.

[0034] In this embodiment, the reset control module is responsible for receiving the reset control instruction issued by the CPU and verifying the legality of the instruction. The reset control instruction may include read and write control signals, address signals, write data signals, etc. The verification method may be parity check or other verification methods such as ECC.

[0035] Among them, the timer is used to monitor the reset status of each functional module. The reset information can be an instruction for the functional module to reset or not to reset. For example, the reset information can be represented by a character string, such as 101110010, where 1 can represent reset and 0 can represent non-reset. Each functional module can perform corresponding reset or non-reset operations based on the reset information.

[0036] S302: When the reset control instruction verification passes, reset information is sent to each functional module, and a timer is started to monitor the reset status of each functional module.

[0037] In this embodiment, when the reset control instruction verification is passed, the reset control module synchronizes the reset information according to different clock domains and outputs it to the functional module and the reset monitoring module. The reset monitoring module can monitor the reset status according to the monitoring enable and related information, that is, start the timer according to the monitoring enable and monitor the reset status of each functional module.

[0038] S303: Report alarm information to the processor when the reset information and the reset status are inconsistent.

[0039] That is, when the reset information and the reset status are inconsistent, the reset monitoring module generates an alarm message and reports it to the CPU for processing.

[0040] In an embodiment of the present application, first, upon receiving a reset control instruction issued by a processor, the reset control instruction is verified, the reset control instruction including the timing duration of the timer and the reset information of each functional module, and then, if the reset control instruction passes the verification, the reset information is sent to each functional module, and the timer is started to monitor the reset status of each functional module, and finally, if the reset information and the reset status are inconsistent, an alarm message is reported to the processor. The embodiment of the present application first verifies the reset control instruction issued by the processor, and if the verification passes, sends the reset control instruction to each functional module, which can ensure that the received reset information is correct, improve the success rate of the reset, and can determine the reset status of each functional module by comparing the reset information with the reset status of each functional module, avoid the reset of functional modules that do not need to be reset, and improve the fault diagnosis coverage.

[0041] In a possible implementation manner of the present application, starting a timer to monitor the reset status of each functional module may include: monitoring the reset status of each functional module by using a timer.

[0042] The embodiment of the present application uses only one timer to monitor all functional modules. Compared with the related art in which each functional module is configured with a timer, and the timers are started and stopped together, the present application can reduce CPU operations, reduce resource waste of the entire system, reduce the power consumption of the timer and the area occupied by the entire system chip.

[0043] In a possible implementation of the present application, the reset monitoring method may further include: generating a configuration update mark when a new reset control instruction issued by the processor is received; generating a mask code according to the configuration update mark, the mask code being used to mask the function module of the configuration update.

[0044] In an embodiment of the present application, when a new reset control instruction is received from the processor during a monitoring cycle, the functional module corresponding to the bit with the configuration update mark can be shielded and not monitored to avoid false alarms caused by reset information that has changed. After the timer expires, that is, after the monitoring cycle ends, all functional modules are monitored together based on the configuration update mark. By shielding the functional module with the configuration update mark and continuing to monitor other functional modules whose reset information has not changed, the present application can monitor all functional modules with only one timer. Reducing the number of timers can reduce CPU operations and improve the computing efficiency of the entire system.

[0045] In a possible implementation of the present application, when the reset control instruction verification passes, the reset monitoring method may further include: generating verification information based on the reset information; adding the verification information to the reset information, and latching the reset information with the verification information added.

[0046] This embodiment can latch configuration information such as reset that has passed legally together with the check bit for subsequent verification to avoid changes in the latched information. The reset information is then synchronized according to different clock domains and output to the functional module and reset monitoring module, and the verification failure information is notified to the CPU in the form of an alarm for processing.

[0047] In a possible implementation of the present application, after latching the reset information with added verification information, the reset monitoring method may further include: verifying the latched reset information with added verification information; and reporting alarm information to the processor if the verification fails.

[0048] This embodiment can perform real-time verification on the latched reset information and report alarm information based on the verification result, thereby reducing misconfiguration caused by random hardware failures, improving diagnostic coverage, reducing the frequency of CPU periodic readbacks, and improving CPU utilization.

[0049] Figure 4 This is a schematic diagram of a complete reset monitoring process provided by the embodiment of the present application. Figure 4 As shown, the process of the reset monitoring method is as follows: Step 1: Configure the CPU monitoring timer duration parameters.

[0050] Step 2: Set the CPU configuration reset monitoring enable state to on.

[0051] Step 3: The CPU configures the reset information of each functional module and sends it to the reset control module through the bus. The reset control module performs a validity check.

[0052] Step 4: The reset control module latches the legal reset information, generates an information update valid signal, and updates the monitoring module and functional module unit with the latched reset information; at the same time, the reset control module also performs real-time legal verification of its own reset information. If there is any inconsistency, an alarm message will be reported.

[0053] Step 5: The functional module completes the reset according to the reset information and outputs the reset status to the reset monitoring module for monitoring.

[0054] Step 6: After receiving the update valid signal, the reset monitoring module starts the state machine for timing. When the timing time is up, it compares the reset information with the reset status output by each functional module. If they are inconsistent, an alarm is reported.

[0055] like Figure 5 As shown in the figure, during the timing process, when the monitoring module receives a configuration update mark, it starts the timing and jumps to the timing completion waiting state. At this time, based on the configured bit information, a mask code is generated to mask the functional module corresponding to the changed reset information, suspending monitoring of the functional module to avoid misjudgment. The functional modules corresponding to other unchanged reset information continue to be monitored in real time. If the reset status and reset information are inconsistent, an alarm message is reported. When the reset monitoring module timer expires, the mask code is changed to a fully unmasked state, that is, all reset states are monitored in real time. If the reset status and reset information are inconsistent, an alarm message is reported.

[0056] The embodiment of the present application can automatically monitor the reset status in real time and report an alarm, reducing CPU intervention, improving CPU utilization, improving fault diagnosis coverage, reducing area, and reducing power consumption.

[0057] The present application also provides a storage medium storing a program or instruction. When executed by a processor, the program or instruction implements the various processes of the reset monitoring method provided in any of the above-described embodiments. The same technical effects can be achieved, and to avoid repetition, they are not further described here.

[0058] The processor is the processor in the electronic device described in the above embodiment. The storage medium includes a computer storage medium, such as a computer read-only memory (ROM), random access memory (RAM), a magnetic disk, or an optical disk.

[0059] An embodiment of the present application further provides a chip, which includes a processor and a communication interface, wherein the communication interface is coupled to the processor, and the processor is used to run programs or instructions to implement the various processes of the above-mentioned reset monitoring method embodiment, and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0060] It should be understood that the chip mentioned in the embodiments of the present application can also be called a system-level chip, a system chip, a chip system or a system-on-chip chip, etc.

[0061] An embodiment of the present application further provides a computer program / program product, which is stored in a storage medium. The computer program / program product is executed by at least one processor to implement the various processes of the above-mentioned reset monitoring method embodiment and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0062] An embodiment of the present application further provides a processing device, which is configured to execute the various processes of the above-mentioned reset monitoring method embodiment and can achieve the same technical effect. To avoid repetition, it will not be described here.

[0063] It should be noted that, in this article, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the statement "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device comprising the element. In addition, it should be noted that the scope of the methods and devices in the embodiments of the present application is not limited to performing functions in the order shown or discussed, and may also include performing functions in a substantially simultaneous manner or in the opposite order according to the functions involved. For example, the described method may be performed in an order different from that described, and various steps may also be added, omitted, or combined. In addition, the features described with reference to certain examples may be combined in other examples.

[0064] Through the description of the above embodiments, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus the necessary general hardware platform. Of course, they can also be implemented by hardware, but in many cases the former is a better embodiment. Based on this understanding, the technical solution of this application, or the part that contributes to the existing technology, can be embodied in the form of a computer software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for enabling a terminal (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in each embodiment of this application.

[0065] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of this application, ordinary technicians in this field can also make many forms without departing from the purpose of this application and the scope of protection of the claims, all of which are within the protection of this application.

Claims

1. A reset monitoring system, characterized in that: include: A processor, configured to issue a reset control instruction and process alarm information, wherein the reset control instruction includes a timer duration and reset information of each functional module; a reset control module, configured to receive and verify the reset control instruction issued by the processor, and if the reset control instruction passes verification, send the timer duration and the reset information to the reset monitoring module, and send the reset information to each functional module; A functional module, configured to perform a reset according to the received reset information and output a reset status to the reset monitoring module; The reset monitoring module is used to start the timer and monitor the reset status of each functional module when receiving the reset control instruction sent by the reset control module, and report alarm information to the processor when the reset information and the reset status are inconsistent.

2. The system according to claim 1, wherein: The reset monitoring module includes a timer, and monitors each functional module through the timer.

3. The system according to claim 2, characterized in that When the reset monitoring module receives a configuration update mark, the reset monitoring module generates a mask code based on the configuration update mark, and the mask code is used to mask the functional module of the configuration update. The configuration update mark is a mark generated when the reset control module receives a new reset control instruction issued by the processor.

4. The system according to claim 1, wherein: When the reset control instruction passes verification, the reset control module generates verification information based on the reset information, adds the verification information to the reset information, and latches the reset information with the verification information added.

5. The system according to claim 4, characterized in that The reset control module verifies the latched reset information with the added verification information, and reports alarm information to the processor if the verification fails.

6. An electronic device, characterized in that: The reset monitoring system comprises the reset monitoring system according to any one of claims 1 to 5.

7. A reset monitoring method, characterized in that: include: Upon receiving a reset control instruction issued by the processor, verifying the reset control instruction, wherein the reset control instruction includes a timing duration of a timer and reset information of each functional module; If the reset control instruction is verified to be passed, the reset information is sent to each functional module, and a timer is started to monitor the reset status of each functional module; When the reset information and the reset state are inconsistent, alarm information is reported to the processor.

8. The method according to claim 7, characterized in that The startup timer monitors the reset status of each of the functional modules, including: The reset state of each of the functional modules is monitored by a timer.

9. The method according to claim 8, characterized in that The method further comprises: generating a configuration update flag upon receiving a new reset control instruction issued by the processor; A masking code is generated according to the configuration update mark, and the masking code is used to mask the function module of the configuration update.

10. The method according to claim 7, characterized in that When the reset control instruction passes verification, the method includes: generating verification information based on the reset information; The verification information is added to the reset information, and the reset information to which the verification information is added is latched.

11. The method according to claim 10, characterized in that After latching the reset information to which the verification information is added, the method includes: Verifying the latched reset information of the added verification information; If the verification fails, an alarm message is reported to the processor.

12. A storage medium, characterized in that: The storage medium stores a program or instruction, and when the program or instruction is executed by the processor, the steps of the reset monitoring method according to any one of claims 7 to 11 are implemented.

13. A program product, characterized in that The program product is stored in a storage medium, and is executed by at least one processor to implement the steps of the reset monitoring method according to any one of claims 7 to 11.

Images