Frequency-locked loop and microcontroller

Abstract

The invention provides a frequency-locked loop and a microcontroller, and the frequency-locked loop comprises a variable current module which is suitable for generating a variable current changing with a first voltage under the effect of the first voltage from the outside; the switched capacitor module is connected in series with the variable current module and is suitable for being matched with the variable current to provide variable voltage; the reference voltage module is suitable for providing reference voltage; the amplifier outputs an amplified signal based on the variable voltage and the reference voltage; the voltage-controlled oscillator is suitable for outputting a square wave signal according to the amplified signal; the non-overlapping clock generation module is suitable for generating a first clock signal and a second clock signal which are not overlapped with each other under the action of the square wave signal; under the condition that the variable voltage is smaller than the reference voltage, the amplification signal output by the amplifier is reduced, the frequency of the square wave signal output by the voltage-controlled oscillator is reduced, and the equivalent impedance of the switched capacitor module is increased along with the reduction of the frequencies of the first clock signal and the second clock signal, so that the variable voltage is equal to the reference voltage.

Description

Technical Field

[0001] The present disclosure relates to the field of electronic information technology, and in particular to a frequency locked loop and a microcontroller. Background Art

[0002] In embedded systems, there are many applications where the MCU (Microcontroller Unit) needs to adjust the clock frequency, such as for MCU power consumption management, performance optimization, power efficiency, communication rate matching, etc.

[0003] With the widespread application of MCUs in mobile devices, the Internet of Things, sensor networks and other fields, the requirements for clock circuits have exceeded traditional standards.

[0004] First, low power consumption is a key criterion in MCU design, especially for battery-powered mobile devices and sensor nodes. However, traditional clock circuits face bottlenecks in power optimization and cannot provide sufficiently low-power clock generation solutions. To meet the MCU's requirements for long-term operation and battery life, clock circuits must adopt advanced power optimization techniques, such as discontinuous operation mode and clock gating, to achieve low-power clock generation and transmission.

[0005] Secondly, there is an increasing demand for a wide range of clock frequencies. Different application scenarios may require the MCU to run at different operating frequencies to balance performance and power consumption. The traditional method of frequency adjustment is to use different RC arrays to lock the corresponding frequency, but this method consumes a lot of space and increases production costs. Summary of the Invention

[0006] In view of the above technical problems, the present disclosure provides a frequency-locked loop, which can sense the change of the first voltage to change the frequency of the square wave signal and can balance performance and power consumption at different operating frequencies.

[0007] As one aspect of the present disclosure, a frequency-locked loop (FLL) is provided, comprising a variable current module, a switched capacitor module, a reference voltage module, an amplifier, a voltage-controlled oscillator, and a non-overlapping clock generation module. The variable current module is configured to generate a variable current that varies with a first external voltage under the influence of the first voltage. The switched capacitor module is connected in series with the variable current module and is configured to cooperate with the variable current module to provide the variable voltage. The reference voltage module is configured to provide a reference voltage, and the amplifier outputs an amplified signal based on the variable voltage and the reference voltage. The voltage-controlled oscillator is configured to output a square wave signal based on the amplified signal. The non-overlapping clock generation module is configured to generate the two non-overlapping first and second clock signals under the influence of the square wave signal. When the variable voltage is less than the reference voltage, the amplifier is configured to reduce the output amplified signal, the voltage-controlled oscillator is configured to reduce the frequency of the output square wave signal, and the equivalent impedance of the switched capacitor module increases as the frequencies of the first and second clock signals decrease, thereby making the variable voltage equal to the reference voltage.

[0008] According to an embodiment of the present disclosure, the variable current module includes a first differential amplifier, a first resistor, a second resistor, a third resistor, and a fourth resistor. The two ends of the first resistor are respectively connected to the first output terminal and the first positive phase input terminal of the first differential amplifier, the two ends of the second resistor are respectively connected to the first output terminal and the first negative phase input terminal of the first differential amplifier, one end of the third resistor is connected to the first negative phase input terminal, and the other end is connected to the ground signal. One end of the fourth resistor is connected to the first voltage, and the other end is connected to the first positive phase input terminal and outputs the variable current. The ratio of the first resistor to the second resistor is equal to the ratio of the third resistor to the fourth resistor, so that the variable current changes linearly with the first voltage.

[0009] According to an embodiment of the present disclosure, the switch capacitor module includes a first capacitor, a first switch, a second switch, and a second capacitor. The first capacitor is connected in series with the variable current module, the first switch is connected in series between the first capacitor and the variable current module, the second switch is connected in parallel with the first capacitor, and the second capacitor is connected in parallel with the first capacitor and the first switch. The first switch and the second switch are respectively turned on or off by the first clock signal and the second clock signal, generating an equivalent impedance related to the frequency of the first clock signal and the second clock signal, so that the switch capacitor circuit provides a variable voltage to the amplifier under the action of the variable current.

[0010] According to an embodiment of the present disclosure, the reference voltage module includes a reference current module and a fifth resistor. The reference current module matches the variable current module and is adapted to provide a reference current. The fifth resistor is connected in series with the reference current module to provide the reference voltage to the amplifier under the action of the reference current.

[0011] According to an embodiment of the present disclosure, the reference current module includes a second differential amplifier, a sixth resistor, a seventh resistor, an eighth resistor, and a ninth resistor. The two ends of the sixth resistor are respectively connected to the second output terminal and the second positive phase input terminal of the second differential amplifier, the two ends of the seventh resistor are respectively connected to the second output terminal and the second negative phase input terminal of the second differential amplifier, one end of the eighth resistor is connected to the second negative phase input terminal, and the other end is connected to the ground signal. One end of the ninth resistor is connected to the second external voltage, and the other end is connected to the second positive phase input terminal and outputs the reference current.

[0012] According to an embodiment of the present disclosure, the frequency-locked loop further includes a cutoff module connected in parallel with the fifth resistor, and the cutoff module includes a third switch and a fourth switch. The fourth switch is connected in series with the third switch, wherein the third switch and the fourth switch are respectively opened or closed in response to the first clock signal and the second clock signal to cut off the tail current of the reference current module.

[0013] According to an embodiment of the present disclosure, the frequency locked loop further includes a third capacitor, which matches the second capacitor and is connected in parallel with the fifth resistor.

[0014] According to an embodiment of the present disclosure, the frequency locked loop further includes a filter. The filter is connected in series between the amplifier and the voltage controlled oscillator and is adapted to filter out ripples generated by the switch capacitor module.

[0015] According to an embodiment of the present disclosure, the amplifier is a chopper amplifier or a differential amplifier.

[0016] As another aspect of the embodiments of the present disclosure, a microcontroller is provided, comprising any of the above-mentioned frequency-locked loops, a power supply, and a voltage module. The power supply is adapted to provide a first voltage to the variable current module, so that the variable current module cooperates with the switch capacitor module to provide the variable voltage under the action of the first voltage. The voltage module is adapted to provide a second voltage to the reference voltage module, so that the reference voltage module provides the reference voltage under the action of the second voltage. When the first voltage provided by the power supply decreases, the frequency of the square wave signal output by the frequency-locked loop decreases along with the first voltage.

[0017] According to an embodiment of the present disclosure, a frequency-locked loop (FLL) generates a variable current that varies with a first external voltage, and cooperates with a switched capacitor module to generate a variable voltage. An amplifier amplifies the difference between the variable voltage and the reference voltage based on the variable voltage and a reference voltage provided by a reference voltage module, outputting an amplified signal. A voltage-controlled oscillator outputs a square wave signal based on the amplified signal output by the amplifier. In response to the square wave signal, a non-overlapping clock generator generates two non-overlapping first and second clock signals with the same frequency as the square wave signal. Consequently, when the voltage at the amplifier input decreases due to a decrease in the variable current or a decrease in the equivalent impedance of the switched capacitor circuit, the voltage of the amplified signal output by the amplifier also decreases. At this point, the frequency of the square wave signal output by the voltage-controlled oscillator decreases and is fed back to the switched capacitor module, increasing the equivalent impedance of the switched capacitor module until the voltages at the positive and negative terminals of the amplifier are equal, stabilizing the frequency of the output square wave signal. This ensures that the frequency of the output square wave signal varies with changes in the first voltage, adapting to different operating scenarios and balancing performance and power consumption at different operating frequencies. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 A circuit diagram of a frequency locked loop according to an embodiment of the present disclosure is schematically shown;

[0019] Figure 2 A circuit diagram of a frequency locked loop according to another embodiment of the present disclosure is schematically shown;

[0020] Figure 3 Schematically shows a current-voltage curve diagram of a variable current module according to an embodiment of the present disclosure;

[0021] Figure 4 A graph schematically showing the ratio of the variable current to the reference current and the frequency of the square wave signal according to an embodiment of the present disclosure; and

[0022] Figure 5 A circuit diagram of a frequency locked loop according to another embodiment of the present disclosure is schematically shown.

[0023] Description of reference numerals:

[0024] 1-Variable voltage module;

[0025] 11- variable current module;

[0026] 12- switched capacitor module;

[0027] 2-reference voltage module;

[0028] 21-reference current module;

[0029] 3-Amplifier;

[0030] 4-Voltage Controlled Oscillator;

[0031] 5- non-overlapping clock generation module;

[0032] 6-Filter;

[0033] 7-frequency division components. DETAILED DESCRIPTION

[0034] In order to make the objectives, technical solutions and advantages of the present disclosure more clearly understood, the present disclosure is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0035] Figure 1 The circuit diagram of a frequency locked loop according to an embodiment of the present disclosure is schematically shown.

[0036] As one aspect of the present disclosure, a frequency locked loop is provided, such as Figure 1 As shown, the frequency-locked loop includes a variable current module 11, a switched capacitor module 12, a reference voltage module 2, an amplifier 3, a voltage-controlled oscillator 4, and a non-overlapping clock generation module (NOC1) 5. The variable current module 11 is adapted to generate a variable current Ic that varies with the first voltage Vc under the action of an external first voltage Vc. The switched capacitor module 12 is connected in series with the variable current module 11 and is adapted to cooperate with the variable current Ic to provide a variable voltage V + The reference voltage module 2 is suitable for providing a reference voltage V - , amplifier 3 is based on the variable voltage V + and reference voltage V - , outputs the amplified signal. The voltage controlled oscillator 4 is adapted to output a square wave signal according to the amplified signal. The non-overlapping clock generating module 5 is adapted to generate two non-overlapping first clock signals CK1 and second clock signals CK2 under the action of the square wave signal. + Less than the reference voltage V - In this case, the amplifier 3 is configured to output an amplified signal that is reduced, and the voltage-controlled oscillator 4 is configured to output a square wave signal with a frequency F out The equivalent impedance of the switch capacitor module 12 increases as the frequency of the first clock signal CK1 and the second clock signal CK2 decreases, thereby making the variable voltage V + With the reference voltage V - equal.

[0037] According to an embodiment of the present disclosure, a frequency-locked loop (FLL) generates a variable current that varies with a first external voltage, and cooperates with a switched capacitor module to generate a variable voltage. An amplifier amplifies the difference between the variable voltage and the reference voltage based on the variable voltage and a reference voltage provided by a reference voltage module, outputting an amplified signal. A voltage-controlled oscillator outputs a square wave signal based on the amplified signal output by the amplifier. In response to the square wave signal, a non-overlapping clock generator generates two non-overlapping first and second clock signals with the same frequency as the square wave signal. Consequently, when the voltage at the amplifier input decreases due to a decrease in the variable current or a decrease in the equivalent impedance of the switched capacitor circuit, the voltage of the amplified signal output by the amplifier also decreases. At this point, the frequency of the square wave signal output by the voltage-controlled oscillator decreases and is fed back to the switched capacitor module, increasing the equivalent impedance of the switched capacitor module until the voltages at the positive and negative terminals of the amplifier are equal, stabilizing the frequency of the output square wave signal. This ensures that the frequency of the output square wave signal varies with changes in the first voltage, adapting to different operating scenarios and balancing performance and power consumption at different operating frequencies.

[0038] According to the frequency locked loop of the embodiment of the present disclosure, the frequency F of the square wave signal is realized by sensing the change of the first voltage Vc. out The wide adjustment range saves a lot of area compared to traditional resistor-capacitor (RC) arrays. This wide adjustment range provides greater flexibility for various application scenarios and can adapt to the requirements of different workloads and environmental conditions.

[0039] According to an embodiment of the present disclosure, the variable current module 11 may be connected to the positive phase input terminal of the amplifier 3 , and the reference voltage module 2 may be connected to the negative phase input terminal of the amplifier 3 .

[0040] According to the frequency locked loop provided by the embodiment of the present disclosure, a combination of an amplifier 3 and a voltage controlled oscillator 4 is used to realize a variable voltage V + With the reference voltage V - The comparison and square wave signal generation.

[0041] According to an embodiment of the present disclosure, the amplifier 3 may be a chopper amplifier or a differential amplifier.

[0042] According to an embodiment of the present disclosure, the frequencies of the two non-overlapping first clock signals CK1 and the second clock signal CK2 generated by the non-overlapping clock generation module 5 can be the same as the frequency F of the square wave signal. out consistent.

[0043] According to an embodiment of the present disclosure, the variable voltage module 1 includes a variable current module 11 and a switched capacitor module 12 .

[0044] Figure 2A circuit diagram of a frequency locked loop according to another embodiment of the present disclosure is schematically shown.

[0045] According to the embodiments of the present disclosure, Figure 2 As shown, the variable current module 11 includes a first differential amplifier, a first resistor R1, a second resistor R2, a third resistor R3 and a fourth resistor R4. The two ends of the first resistor R1 are respectively connected to the first output terminal and the first positive phase input terminal of the first differential amplifier, the two ends of the second resistor are respectively connected to the first output terminal and the first negative phase input terminal of the first differential amplifier, one end of the third resistor R3 is connected to the first negative phase input terminal, and the other end is connected to the ground signal. One end of the fourth resistor R4 is connected to the first voltage, and the other end is connected to the first positive phase input terminal and outputs a variable current. Among them, the ratio of the first resistor R1 to the second resistor R2 is equal to the ratio of the third resistor R3 to the fourth resistor R4, so that the variable current I C Following the first voltage V C Linear change.

[0046] According to the embodiments of the present disclosure, Figure 2 As shown, for an ideal amplifier, in the variable current module, the current I1 flowing through the resistor R2 is:

[0047]

[0048] The current I2 flowing through resistor R4 is:

[0049]

[0050] The current I3 flowing through resistor R1 is:

[0051]

[0052] Output current I of the variable current module C for:

[0053] I C =I2+I3 (4)

[0054] In formulas (1)-(4), e1 is the electromotive force at point e1, e2 is the electromotive force at point e2, R1 represents the resistance value of resistor R1, R2 represents the resistance value of resistor R2, R3 represents the resistance value of resistor R3, R4 represents the resistance value of resistor R4, V1 represents the first input voltage value of the first input terminal of the variable current module, V C Represents the first voltage V at the second input terminal of the variable current module C V3 represents the output voltage value of the output end of the amplifier.

[0055] Since the frequency of the square wave signal output by the frequency locked loop is F outIn the locked state, the electromotive force at point e1 is equal to the electromotive force at point e2, that is, e1 = e2. Therefore, the voltage drop across resistor R2 is equal to the voltage drop across resistor R1. Therefore, we can get:

[0056]

[0057] According to formula (1), e2 can be expressed as:

[0058] e2=I1R3+V1 (6)

[0059] Therefore, we can get:

[0060]

[0061] like,

[0062]

[0063] The variable current Ic is proportional to the voltage difference (Vc-V1). In other words, the variable current Ic is proportional to the voltage difference between the second input terminal and the first input terminal of the variable current module 11.

[0064] In the embodiment of the present disclosure, the first input terminal of the variable current module 11 is connected to the ground signal, that is, V1=0, then the variable current Ic is related to the first voltage V C Directly proportional.

[0065] Figure 3 The current-voltage curve diagram of the variable current module according to the embodiment of the present disclosure is schematically shown.

[0066] like Figure 3 As shown, the horizontal axis represents the first voltage V C (V), the vertical axis represents the variable current Ic(n). It can be seen from the figure that the variable current Ic is related to the first voltage V C Into a linear relationship.

[0067] According to the embodiments of the present disclosure, Figure 1 and Figure 2 As shown, the reference voltage module 2 includes a reference current module 21 and a fifth resistor R5. The reference current module 21 matches the variable current module 11 and is suitable for providing a reference current I ref The fifth resistor R5 is connected in series with the reference current module 21 to ref Provides a reference voltage V for the amplifier - .

[0068] According to the embodiments of the present disclosure, Figure 1 and Figure 2As shown, the reference current module 21 includes a second differential amplifier, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, and a ninth resistor R9. The two ends of the sixth resistor R6 are respectively connected to the second output terminal and the second positive phase input terminal of the second differential amplifier, the two ends of the seventh resistor R7 are respectively connected to the second output terminal and the second negative phase input terminal of the second differential amplifier, one end of the eighth resistor R8 is connected to the second negative phase input terminal, and the other end is connected to the ground signal. One end of the ninth resistor R9 is connected to the external second voltage, and the other end is connected to the second positive phase input terminal and outputs the reference current I ref .

[0069] According to an embodiment of the present disclosure, the reference current module 21 and the variable current module 11 adopt the same circuit structure to make the circuit structure of the frequency locked loop symmetrical.

[0070] According to an embodiment of the present disclosure, the reference current I ref It can be expressed as:

[0071]

[0072] At this time, the voltage at the negative input of the amplifier, that is, the reference voltage V _ for:

[0073] V - =I ref ×R5 (10)

[0074] Among them, V ref represents the voltage value of the second voltage input to the reference voltage module, and R5 represents the resistance value of the fifth resistor R5.

[0075] According to the embodiments of the present disclosure, Figure 1 and Figure 2 As shown, the switched capacitor module 12 includes a first capacitor Cp1, a first switch K1, a second switch K2, and a second capacitor Cp1. The first capacitor C is connected in series with the variable current module 11, the first switch K1 is connected in series between the first capacitor C and the variable current module 11, the second switch K2 is connected in parallel with the first capacitor C, and the second capacitor Cp1 is connected in parallel with the first capacitor C and the first switch K1. The first switch K1 and the second switch K2 are respectively turned on or off by the first clock signal CK1 and the second clock signal CK2, generating an equivalent impedance related to the frequency of the first clock signal CK1 and the second clock signal CK2, so that the switched capacitor module 12 is in a state where the variable current I C The amplifier is provided with a variable voltage V + .

[0076] In an exemplary embodiment, the clock frequencies of the first clock signal CK1 and the second clock signal CK2 can be the same as the frequency F of the square wave signal output by the frequency locked loop.out The same, the equivalent impedance of the switch capacitor module R X for:

[0077]

[0078] Where, C represents the capacitance of the first capacitor C, F out is the frequency of the square wave signal output by the frequency-locked loop.

[0079] Then, the voltage at the non-inverting input of the amplifier, that is, the variable voltage V + for:

[0080]

[0081] Where, C represents the capacitance of the first capacitor C, F out is the frequency of the square wave signal output by the frequency-locked loop, and Ic represents the current value of the variable current.

[0082] The frequency of the square wave signal output by the frequency-locked loop is F out for:

[0083]

[0084] Wherein, C represents the capacitance of the first capacitor C, R5 represents the resistance of the fifth resistor R5, Ic represents the current value of the variable current, I ref Indicates the current value of the reference current.

[0085] From formula (13), we can see that at the second voltage V ref Constant, variable current I c When the frequency of the square wave signal output by the frequency locked loop changes, the frequency F out Synchronous changes. When the frequency-locked loop needs to reduce voltage and frequency, the frequency F out The first voltage V C Synchronous changes.

[0086] Figure 4 A graph schematically shows the ratio of the variable current to the reference current and the frequency of the square wave signal according to an embodiment of the present disclosure.

[0087] like Figure 4 As shown, the horizontal axis represents the variable current I c With the reference current I ref The ratio of the vertical axis represents the frequency F of the square wave signal out (MHz). Figure 4 It can be seen that the frequency F of the square wave signal out With variable current I c With the reference current I ref The ratio is linearly related.

[0088] According to the frequency locked loop of the embodiment of the present disclosure, the variable current module 11 is combined with the frequency lock, and the first voltage V is sensed by the variable current module. C The change of the square wave signal output by the frequency locked loop is adjusted to adjust the frequency F out By setting the variable current module 11, the ratio of the first resistor R1 to the second resistor R2 is set to be equal to the ratio of the third resistor R3 to the fourth resistor R4, so that the variable current can follow the first voltage V C It changes linearly to achieve variable current I c The precise control makes the frequency of the square wave signal output by the frequency-locked loop more flexible and adjustable.

[0089] The frequency-locked loop (FLL) of the disclosed embodiments overcomes the limitations of traditional frequency adjustment methods and achieves a wider range of frequency adjustment capabilities. By combining the high adjustability of the variable current module with the frequency locking mechanism of the FLL, it provides adaptability to a variety of operating frequencies, enabling the FLL to maintain stable performance in different application scenarios.

[0090] According to the embodiments of the present disclosure, Figure 1 and Figure 2 As shown, the frequency-locked loop also includes a cutoff module 5. The cutoff module 5 is connected in parallel with the fifth resistor R5 and includes a third switch K3 and a fourth switch K4, with the fourth switch K4 connected in series with the third switch K3. The third switch K3 and the fourth switch K4 are opened or closed in response to the first clock signal CK1 and the second clock signal CK2, respectively, to cut off the tail current of the reference current module 11.

[0091] According to an embodiment of the present disclosure, the frequency locked loop further includes a third capacitor Cp2 matched with the second capacitor Cp1 , and the third capacitor Cp2 is connected in parallel with the fifth resistor R5 .

[0092] According to the embodiment of the present disclosure, by providing the cut-off module 5 and the third capacitor Cp2 , in cooperation with the fifth resistor R5 , and symmetrically matching the switch capacitor module 12 , the stability of the frequency-locked loop circuit is improved.

[0093] According to an embodiment of the present disclosure, the frequency locked loop further includes a filter 6 connected in series between the amplifier 3 and the voltage controlled oscillator 4 , adapted to filter out ripples generated by the switch capacitor module 12 .

[0094] According to an embodiment of the present disclosure, the filter includes a low-pass filter (LPF).

[0095] According to an embodiment of the present disclosure, the ripple generated by the switched capacitor module 12 may affect the accuracy of the output square wave signal. The low-pass filter at the rear end of the amplifier 3 filters out the ripple to improve the frequency stability of the square wave signal.

[0096] During the implementation of this disclosure, it was discovered that chopping technology could be introduced to address amplifier offset voltage issues and improve oscillator frequency stability. Chopping technology is a method that eliminates static errors by periodically switching the amplifier's gain or bias. Applying chopping technology to amplifiers can effectively suppress offset voltage and improve output signal accuracy. However, every technology has its downsides. While chopping technology offers numerous advantages for amplifiers and oscillators, its use also carries with it some potential problems. The most obvious issue is ripple generated at the control input of the voltage-controlled oscillator (VCO). This ripple is caused by the interaction between the chopping signal and the VCO's voltage control characteristics. When this ripple occurs, it increases the VCO's output jitter, thereby affecting the performance of the entire system. Typically, this problem can be addressed by increasing the chopping frequency or increasing the load capacitance. However, the former may result in greater offset voltage drift and poorer accuracy at lower frequencies, while the latter involves a trade-off between capacitor area and jitter performance.

[0097] Figure 5 A circuit diagram of a frequency locked loop according to another embodiment of the present disclosure is schematically shown.

[0098] According to the embodiments of the present disclosure, Figure 5 As shown, amplifier 3 is a chopper amplifier and filter 6 is a switched capacitor filter. The frequency locked loop also includes a frequency division component and a load capacitor C L The frequency dividing component is adapted to provide two non-overlapping third and fourth clock signals with lower frequencies than the square wave signal under the action of the square wave signal, wherein the third and fourth clock signals serve as the chopping frequencies of the chopper amplifier. L One end is connected to the output end of the chopper amplifier, and the other end is connected to the ground signal, which is suitable for suppressing the output ripple of the chopper amplifier.

[0099] According to the embodiments of the present disclosure, Figure 5 As shown, the switched capacitor filter includes a fifth switch K5, a first filter capacitor C1, a sixth switch K6, and a second filter capacitor C2. One end of the fifth switch K5 is connected to the output of the chopper amplifier, one end of the first filter capacitor C1 is connected to the other end of the fifth switch K5, and the other end of the first filter capacitor C1 is connected to the ground signal. The sixth switch K6 is connected in series between the fifth switch K5 and the voltage-controlled oscillator, one end of the second filter capacitor C2 is connected to the other end of the sixth switch K6, and the other end of the second filter capacitor C2 is connected to the ground signal. The fifth switch K5 and the sixth switch K6 are turned on or off in response to the first clock signal CK1 and the second clock signal CK2, respectively.

[0100] According to the frequency locked loop of the embodiment of the present disclosure, the ripple is suppressed by using a switched capacitor filter, thereby reducing the size of the load capacitor. The switched filter consists of two filter capacitors (C1 and C2) and two switches (K5 and K6) driven by sampling signals (first clock signal CK1 and second clock signal CK2). In each chopping cycle of the switched capacitor filter, the load capacitor C L The voltage on the switched capacitor is sampled to suppress ripple. The poles of the switched capacitor filter are determined by the frequency of the sampling signal (the first clock signal CK1 and the second clock signal CK2) and the ratio of the two filter capacitors, which can accurately suppress ripple.

[0101] According to the embodiments of the present disclosure, Figure 5 As shown, the frequency division component includes a clock generator (Clock Generator), a frequency divider (Div), and a non-overlapping clock generator (NOC2). The clock generator (Clock Generator) generates a fifth clock signal in response to a square wave signal. The frequency divider (Div) is adapted to divide the fifth clock signal into a sixth clock signal. The non-overlapping clock generator (NOC2) generates two non-overlapping third and fourth clock signals in response to the sixth clock signal. The third and fourth clock signals serve as the chopping frequencies of the chopper amplifier.

[0102] According to an embodiment of the present disclosure, a frequency dividing component is provided to obtain a third clock signal and a fourth clock signal having a frequency lower than that of the square wave signal. The third clock signal and the fourth clock signal are used as chopping frequencies, thereby reducing the loss of amplifier gain.

[0103] In the process of implementing the present disclosure, it was found that RC (resistance-capacitance) relaxation oscillators have the advantages of small size and good frequency stability, and are often used as on-chip clock sources. However, the oscillation frequency of the RC relaxation oscillator depends on the RC time constant and comparator delay, which are very sensitive to process, temperature and voltage changes. The first-order temperature coefficient (TC) of the RC time constant can be compensated by using a series of positive and negative TC resistors to implement the oscillator's resistor array. Nevertheless, the comparator delay is still susceptible to temperature changes, which will reduce the frequency stability of the device.

[0104] Frequency-locked loops (FLLs) use ultra-low-power operational amplifiers (OPA) instead of the high-power, high-speed comparators used in RC relaxation oscillators, reducing power consumption. Digital FLLs are widely adopted because they offer higher frequency stability and accuracy, adapt to diverse application requirements, and are easily integrated into digital signal processors (DSPs) or other digital systems.

[0105] However, digital frequency-locked loops are complex to implement, especially when processing high-speed digital signals. They require more computing resources and complex digital algorithms. Furthermore, compared to analog FLLs, digital FLLs typically consume more power and are more expensive.

[0106] As another aspect of an embodiment of the present disclosure, a microcontroller is provided, comprising any of the above-described frequency-locked loops, a power supply, and a voltage module. The power supply is adapted to provide a first voltage to a variable current module, so that the variable current module, under the action of the first voltage, cooperates with the switched capacitor module to provide a variable voltage. The voltage module is adapted to provide a second voltage to a reference voltage module, so that the reference voltage module, under the action of the second voltage, provides a reference voltage. When the first voltage provided by the power supply decreases, the frequency of the square wave signal output by the frequency-locked loop decreases accordingly.

[0107] According to the microcontroller of the embodiment of the present disclosure, by using the power supply of the microcontroller as the first voltage of the variable current module, the frequency of the square wave signal output by the frequency-locked loop can change with the change of the power supply voltage of the microcontroller, thereby providing greater flexibility for the microcontroller to operate in various application scenarios and enabling the microcontroller to adapt to the requirements of different workloads and environmental conditions.

[0108] The specific embodiments described above further illustrate the purpose, technical solutions and beneficial effects of the present disclosure. It should be understood that the above are only specific embodiments of the present disclosure and are not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure should be included in the scope of protection of the present disclosure.

Claims

1. A frequency-locked loop, characterized in that: include: A variable current module, adapted to generate a variable current that varies with a first voltage supplied from an external source under the action of the first voltage; A switched capacitor module, connected in series with the variable current module, adapted to cooperate with the variable current to provide the variable voltage; A reference voltage module, suitable for providing a reference voltage; an amplifier, configured to output an amplified signal based on the variable voltage and the reference voltage; a voltage-controlled oscillator, adapted to output a square wave signal according to the amplified signal; as well as a non-overlapping clock generating module, adapted to generate the two non-overlapping first clock signals and second clock signals under the action of the square wave signal; In which, when the variable voltage is less than the reference voltage, the amplifier is configured to reduce the output amplified signal, the voltage-controlled oscillator is configured to reduce the frequency of the output square wave signal, and the equivalent impedance of the switched capacitor module increases as the frequencies of the first clock signal and the second clock signal decrease, thereby making the variable voltage equal to the reference voltage.

2. The frequency-locked loop according to claim 1, wherein: The variable current module includes: a first differential amplifier; a first resistor, two ends of which are respectively connected to the first output terminal and the first non-inverting input terminal of the first differential amplifier; a second resistor, two ends of which are respectively connected to the first output terminal and the first negative phase input terminal of the first differential amplifier; a third resistor, one end of which is connected to the first negative phase input terminal, and the other end of which is connected to the ground signal; and a fourth resistor, one end of which is connected to the first voltage, and the other end of which is connected to the first non-inverting input terminal and outputs the variable current; The ratio of the first resistor to the second resistor is equal to the ratio of the third resistor to the fourth resistor, so that the variable current changes linearly with the first voltage.

3. The frequency locked loop according to claim 1, wherein: The switch capacitor module includes: A first capacitor connected in series with the variable current module; a first switch connected in series between the first capacitor and the variable current module; a second switch connected in parallel with the first capacitor; and a second capacitor connected in parallel with the first capacitor and the first switch; The first switch and the second switch are respectively turned on or off under the action of the first clock signal and the second clock signal, generating an equivalent impedance related to the frequency of the first clock signal and the second clock signal, so that the switched capacitor circuit provides a variable voltage to the amplifier under the action of the variable current.

4. The frequency locked loop according to claim 1, wherein: The reference voltage module includes: a reference current module, matched with the variable current module, the reference current module being adapted to provide a reference current; and a fifth resistor connected in series with the reference current module to provide the reference voltage for the amplifier under the action of the reference current.

5. The frequency locked loop according to claim 4, characterized in that: The reference current module includes: a second differential amplifier; a sixth resistor, two ends of which are respectively connected to the second output terminal and the second non-inverting input terminal of the second differential amplifier; a seventh resistor, two ends of which are respectively connected to the second output terminal and the second negative phase input terminal of the second differential amplifier; an eighth resistor, one end of which is connected to the second negative phase input terminal, and the other end of which is connected to a ground signal; and A ninth resistor has one end connected to the external second voltage and the other end connected to the second non-inverting input terminal and outputs the reference current.

6. The frequency locked loop according to claim 5, characterized in that: Also includes: a cut-off module connected in parallel with the fifth resistor, the cut-off module comprising: a third switch; and a fourth switch connected in series with the third switch; The third switch and the fourth switch are respectively turned on or off under the action of the first clock signal and the second clock signal to cut off the tail current of the reference current module.

7. The frequency-locked loop according to claim 5, wherein: Also includes: A third capacitor is matched with the second capacitor, and the third capacitor is connected in parallel with the fifth resistor.

8. The frequency locked loop according to claim 1, wherein: Also includes: The filter is connected in series between the amplifier and the voltage-controlled oscillator and is suitable for filtering out the ripple generated by the switch capacitor module.

9. The frequency locked loop according to claim 1, wherein: The amplifier is a chopper amplifier or a differential amplifier.

10. A microcontroller, characterized in that: include: The frequency locked loop according to any one of claims 1 to 9; a power supply, adapted to provide a first voltage to the variable current module, so that the variable current module cooperates with the switch capacitor module to provide the variable voltage under the action of the first voltage; as well as a voltage module, adapted to provide a second voltage to the reference voltage module, so that the reference voltage module provides the reference voltage under the action of the second voltage; Wherein, when the first voltage provided by the power supply decreases, the frequency of the square wave signal output by the frequency-locked loop decreases along with the first voltage.

Images