Fin-type field effect transistor integrated with low-barrier diode and manufacturing method of fin-type field effect transistor

Abstract

The invention discloses a fin field effect transistor integrated with a low-barrier diode and a manufacturing method of the fin field effect transistor, and relates to the field of power semiconductor device manufacturing. The first type drift region is formed on the substrate; a second type well layer formed in the drift region; a source region formed in the well layer; the first groove extends downwards from the upper surface of the source region and penetrates through the well layer; the protection region is formed on the side wall and the bottom of the first groove; the gate oxide layer covers the inner surface of the first groove; the gate electrode is filled in the first groove; the second groove extends downwards from the upper surface of the source region to the drift region; and the source electrode is filled in the second groove. According to the fin field effect transistor integrated with the low-barrier diode and the manufacturing method of the fin field effect transistor, the low-barrier diode is integrated in a power FINFET device to serve as a follow current path, the switching loss and the degradation risk of the device can be reduced, and the reliability of the device is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of power semiconductor device manufacturing, and in particular to a fin field effect transistor with an integrated low-barrier diode and a manufacturing method thereof. Background Art

[0002] The switching device of a power converter controls the on / off switching of input electrical energy, switching the circuit on and off according to different control signals. Common power switches include transistors, MOSFETs, and IGBTs. In the vast majority of power converter applications, the switching device requires a freewheeling diode to provide a path for reverse freewheeling current. Currently, there are three methods for achieving freewheeling: the first is to use a switching device and a freewheeling diode in parallel in the circuit to achieve freewheeling, but this method is costly and has large parasitic parameters. The second method, taking the power MOSFET as an example, is to achieve freewheeling through the device's own parasitic anti-parallel PN junction diode. However, this parasitic diode has long reverse recovery time and large reverse recovery charge, which can easily cause bipolar degradation of the device. The third method is to directly integrate a diode as a freewheeling path during the design of the power device.

[0003] For example, there is a Chinese patent with the announcement number CN119835982B, which involves a structure of a trench gate power MOSFET and a method for manufacturing a trench gate power MOSFET. It requires parallel connection with a freewheeling diode in the circuit or through its own parasitic diode to achieve freewheeling, which has the problems of high cost, large parasitic parameters, or easy to cause bipolar degradation of the device. Summary of the Invention

[0004] In order to improve circuit stability, the present invention proposes a fin field-effect transistor with an integrated low-barrier diode and a manufacturing method thereof. By integrating a low-barrier diode inside the power FINFET device as a freewheeling path, the switching loss and degradation risk of the device can be reduced, thereby improving the device reliability.

[0005] In order to achieve the above-mentioned objectives, the present invention adopts the following technical solutions: a fin field-effect transistor with an integrated low-barrier diode, comprising: a first-type substrate; a first-type drift region formed on the substrate; a second-type well layer formed in the drift region; a source region formed in the well layer; a first trench extending downward from the upper surface of the source region and penetrating the well layer; a protection zone formed on the sidewalls and bottom of the first trench; a gate oxide layer covering the inner surface of the first trench; a gate electrode filled in the first trench; a second trench extending downward from the upper surface of the source region to the drift region; and a source filled in the second trench.

[0006] In this technical solution, by sinking the source into the second trench and making ohmic contact and / or Schottky contact with the second trench to form a diode structure, the bipolar degradation of the device caused by the parasitic anti-parallel PN junction diode of the device is avoided.

[0007] Preferably, the substrate is heavily doped, and the drift region includes a lightly doped first-type epitaxial layer formed on the substrate and a medium-doped first-type current diffusion layer located on the epitaxial layer.

[0008] Preferably, the source region includes a first-type first source region and a second-type second source region, the first source region and the second source region jointly cover the entire upper surface of the well region, and the depth of the first source region does not exceed the well layer.

[0009] Preferably, the protection zone includes a sidewall protection zone and a bottom protection zone, and the impurity concentration of the sidewall protection zone is greater than the impurity concentration of the current diffusion layer and less than the impurity concentration of the first source region.

[0010] Preferably, a distance between two adjacent first trenches in the first direction is 50 nm to 100 nm.

[0011] Preferably, the first trench extends from the upper surface of the first source region to the current diffusion layer or penetrates the current diffusion layer, and the first trench does not contact the second source region.

[0012] Preferably, the second trench in contact with the drift region has a step-like shape.

[0013] Preferably, the second trench extends to the current diffusion layer.

[0014] Preferably, the first type of conductivity is N-type, and the second type of conductivity is P-type; or the first type of conductivity is P-type, and the second type of conductivity is N-type.

[0015] The present invention also adopts the following technical solution: a method for manufacturing a fin field effect transistor with an integrated low-barrier diode, which realizes the above-mentioned fin field effect transistor with an integrated low-barrier diode, including the following steps: S1, forming a first-type substrate and a first-type drift region; S2, forming a second-type well layer; S3, forming a first-type first source region; S4, forming a second-type second source region; S5, forming a first trench; S6, forming a second-type sidewall protection region; S7, forming a second-type bottom protection region connected to the sidewall protection region; S8, forming a gate oxide layer and a gate electrode in the first trench; S9, forming a second trench; S10, forming a source in the second trench.

[0016] The beneficial effects of the present invention are: 1) Reduce the device's on-resistance and conduction loss through the FINFET structure; 2) Improve device reliability and reduce device switching losses by integrating low-barrier diodes inside the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1FIG. 1 is a top view of the fin field effect transistor according to the first embodiment of the present invention without three electrodes.

[0018] Figure 2 yes Figure 1 Cross-section view at B-B'.

[0019] Figure 3 yes Figure 1 Cross-sectional view at C-C'.

[0020] Figure 4 It is a schematic diagram of step S1 of embodiment 2 of the present invention.

[0021] Figure 5 It is a schematic diagram of step S2 of embodiment 2 of the present invention.

[0022] Figure 6 It is a top view of the wafer during step S3 of embodiment 2 of the present invention.

[0023] Figure 7 It is a cross-sectional view of the wafer at line AA' during step S3 of embodiment 2 of the present invention.

[0024] Figure 8 It is a cross-sectional view of the wafer at line BB' during step S3 of embodiment 2 of the present invention.

[0025] Figure 9 It is a top view of the wafer during step S4 of embodiment 2 of the present invention.

[0026] Figure 10 yes Figure 9 A-A' cross-section.

[0027] Figure 11 yes Figure 9 Cross-section view at B-B'.

[0028] Figure 12 It is a top view of the wafer during step S5 of embodiment 2 of the present invention.

[0029] Figure 13 yes Figure 12 A-A' cross-section.

[0030] Figure 14 yes Figure 12 Cross-section view at B-B'.

[0031] Figure 15 yes Figure 12 Cross-sectional view at C-C'.

[0032] Figure 16 It is a top view of the wafer during step S6 of embodiment 2 of the present invention.

[0033] Figure 17 yes Figure 16 A-A' cross-section.

[0034] Figure 18 yes Figure 16 Cross-section view at B-B'.

[0035] Figure 19 yes Figure 16 Cross-sectional view at C-C'.

[0036] Figure 20 It is a top view of the wafer during step S7 of embodiment 2 of the present invention.

[0037] Figure 21 yes Figure 20 A-A' cross-section.

[0038] Figure 22 yes Figure 20 Cross-section view at B-B'.

[0039] Figure 23 yes Figure 20 Cross-sectional view at C-C'.

[0040] Figure 24 It is a top view of the wafer during step S8 of embodiment 2 of the present invention.

[0041] Figure 25 yes Figure 24 A-A' cross-section.

[0042] Figure 26 yes Figure 24 Cross-section view at B-B'.

[0043] Figure 27 yes Figure 24 Cross-sectional view at C-C'.

[0044] Figure 28 It is a top view of the wafer during step S9 of embodiment 2 of the present invention.

[0045] Figure 29 yes Figure 28 A-A' cross-section.

[0046] Figure 30 yes Figure 28 Cross-section view at B-B'.

[0047] Figure 31 Schematic diagram of ohmic contact in step S10 of Example 2 of the present invention.

[0048] Figure 32 Schematic diagram of the Schottky contact in step S10 of Example 2 of the present invention.

[0049] Figure 33It is a top view of the wafer during step S9 of embodiment 4 of the present invention.

[0050] Figure 34 yes Figure 33 A-A' cross-section.

[0051] Figure 35 yes Figure 33 Cross-section view at B-B'.

[0052] Figure 36 Schematic diagram of ohmic contact in step S10 of Example 4 of the present invention.

[0053] Figure 37 Schematic diagram of Schottky contact in step S10 of Example 4 of the present invention.

[0054] Figure 38 It is a top view of the wafer during step S9 of embodiment 5 of the present invention.

[0055] Figure 39 yes Figure 38 Cross-section view at B-B'.

[0056] Figure 40 yes Figure 38 Cross-sectional view at C-C'.

[0057] Figure 41 yes Figure 38 Sectional view at D-D'.

[0058] Figure 42 3 is a diagram showing the on-state current density distribution of the CC' cross section in Example 5 of the present invention.

[0059] Figure 43 This is a forward conduction characteristic curve diagram of the device in Example 5 of the present invention.

[0060] Figure 44 3 is a current density distribution diagram of the BB' section in Example 5 of the present invention.

[0061] Figure 45 3 is a diagram showing the on-state current density distribution of the D-D' cross section in Example 5 of the present invention.

[0062] Figure 46 3 is a comparison diagram of the third quadrant simulation characteristics of the device with integrated low-barrier diode and the device without integrated low-barrier diode in Example 5 of the present invention.

[0063] Figure numerals: substrate 1; drift region 2; epitaxial layer 201; current diffusion layer 202; well layer 3; source region 4; first source region 401; second source region 402; first trench 5; protection zone 6; sidewall protection zone 601; bottom protection zone 602; gate oxide layer 7; gate electrode 8; second trench 9; source 10; drain 11; first hard mask Y1; second hard mask Y2; third hard mask Y3; fourth hard mask Y4. DETAILED DESCRIPTION

[0064] In order to make the objectives, technical solutions and advantages of the present invention more clear, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific implementation method described herein is only an optimal embodiment of the present invention, which is only used to explain the present invention and does not limit the scope of protection of the present invention. All other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0065] For clarity, the thicknesses of layers and regions are exaggerated in the drawings. It will also be understood that when a layer is referred to as being "on" another layer or substrate, it can be directly on that layer or substrate, or intervening layers may be present. Furthermore, the terms "first type" and "second type" refer to opposite semiconductor conductivity types, such as N-type and P-type. It will be understood that when the first type is N-type, the second type refers to P-type, and similarly, when the first type is P-type, the second type refers to N-type.

[0066] Example 1 This embodiment provides a fin field effect transistor with an integrated low barrier diode. Figures 1 to 3 , including a substrate 1, a drift region 2, a well layer 3, a first source region 401, a second source region 402, a first trench 5, a sidewall protection area 601, a bottom protection area 602, a gate oxide layer 7, a gate electrode 8, a second trench 9 and a source 10.

[0067] In this embodiment, the substrate is a heavily doped first type (e.g., N+ type) substrate, the drift region includes a lightly doped first type (e.g., N- type) epitaxial layer 201 formed on the substrate, and a medium doped first type (e.g., N- type) current diffusion layer 202 formed on the epitaxial layer, and the well layer is formed in the current diffusion layer, extending downward from the upper surface of the current diffusion layer and having a depth not exceeding the current diffusion layer.

[0068] It should be noted that "heavy doping", "medium doping" and "light doping" refer to the impurity concentration of layers or regions formed by doping with N-type media. The three are relative. That is to say, in this embodiment, the impurity concentration of the substrate doping is greater than the impurity concentration of the current diffusion layer doping, and the impurity concentration of the current diffusion layer doping is greater than the impurity concentration of the epitaxial layer doping.

[0069] The first source region and the second source region are formed in the well layer, the second source region is configured to extend downward from several independent rectangular areas on the upper surface of the well layer, the first source region extends downward from an area on the upper surface of the well layer located outside the rectangular areas, and the depth of the first source region does not exceed the well layer. The depths of the first source region and the second source region may be different, and the first source region and the second source region can cover the entire upper surface of the well layer.

[0070] It should be noted that the depth of the first source region does not exceed the well layer, and the depth of the second source region may not exceed the well layer, may penetrate the well layer, or may extend to the current diffusion layer.

[0071] The opening of the first trench is rectangular and extends downward from the upper surface of the first source region. The depth must penetrate the well region and may also extend to the current diffusion layer or penetrate the current diffusion layer.

[0072] The spacing between adjacent first trenches in the first direction (Y direction) is 50nm to 100nm to ensure that the channel region can form "body inversion", thereby increasing the carrier concentration in the inversion layer, reducing surface scattering, reducing the lateral electric field in the channel, and improving the mobility of the device, so that the device has a FINFET effect.

[0073] The sidewall protection zone is formed in the well layer and the current diffusion layer on the side wall of the first trench and extends to the current diffusion layer at the bottom edge. The bottom protection zone is formed in the current diffusion layer at the bottom center of the first trench. The bottom protection zone is connected to the sidewall protection zone and is electrically connected to the well layer, so that the potential of the bottom protection zone is always close to the potential of the well layer.

[0074] A gate oxide layer is formed on the inner surface of the first trench and completely covers the inner surface of the first trench and extends to cover the upper surface of the first source region between adjacent first trenches in the first direction. A gate electrode is filled in the first trench.

[0075] The opening of the second trench may be rectangular and extend downward from the upper surface of the first source region and / or the second source region. The opening of the second trench may fall entirely within the N+ type first source region, entirely within the P+ type second source region, or partially within the N+ type first source region and partially within the P+ type second source region. This embodiment illustrates a case where the second trench partially falls within the N+ type first source region and partially falls within the P+ type second source region.

[0076] The depth of the second trench may not be completely equal to the depth of the first trench, and the lowest point of the second trench may be higher than the lowest point of the first trench. However, it is necessary to ensure that the lowest point of the second trench extends to the current diffusion layer.

[0077] In this embodiment, the second trench is in a quadrangular prism shape, the bottom plane of the trench is located in the current diffusion layer, a plurality of second trenches are distributed in an array, and the second trenches do not contact the first trenches.

[0078] The source is located in the second trench and forms an ohmic or Schottky contact with the sidewall of the second trench, forming a diode structure. The P-type sidewall protection zone and P-type bottom protection zone of the first trench create a pinch-off effect on the ohmic contact / ohmic contact. In the blocking state, the barrier of the Schottky diode is not directly exposed to high electric fields, which can improve the blocking capability of the device. When the contact is an ohmic contact, the diode is a new type of pinch-off barrier diode; when the contact is a Schottky contact, it is a Schottky diode.

[0079] It should be noted that the shapes, sizes, numbers and arrangements of the first source region, the second source region, the first trench and the second trench in this embodiment are only used as examples and are not limited thereto. Those skilled in the art may make adjustments according to actual needs.

[0080] Example 2 This embodiment provides a method for manufacturing a fin field effect transistor with an integrated low barrier diode, which can realize the fin field effect transistor with an integrated low barrier diode described in Example 1, and includes the following steps.

[0081] Step S1 , forming a first type substrate and a first type drift region.

[0082] In this embodiment, the first type refers to N-type, and the second type refers to P-type.

[0083] Figure 4 FIG1 shows a cross-sectional view of a fin field effect transistor with an integrated low barrier diode manufactured according to the manufacturing method of this embodiment at this step, as shown in FIG1 . Figure 4 As shown, an N-type heavily doped N+ type substrate wafer is prepared, and an N- type epitaxial layer and an N- type current diffusion layer are grown on the N+ type substrate wafer. The epitaxial layer and the current diffusion layer together constitute a drift region.

[0084] Step S2: forming a second type well layer.

[0085] Figure 5 FIG1 shows a cross-sectional view of a fin field effect transistor with an integrated low barrier diode manufactured according to the manufacturing method of this embodiment at this step, as shown in FIG1 . Figure 5 As shown, P-type implantation is performed on the upper surface of the wafer by flood implantation to form a P-type well layer, and the depth of the P-type well layer does not exceed the N-type current diffusion layer.

[0086] Step S3: forming a first type first source region.

[0087] Figure 6 FIG2 shows a top view of a fin field effect transistor with an integrated low barrier diode manufactured according to the manufacturing method of this embodiment at this step, Figure 7 for Figure 6In the cross-section diagram along line A-A', Figure 8 for Figure 6 In the cross-section diagram of B-B', Figures 6 to 8 As shown, a first hard mask is grown on the surface of the wafer, and an N+ type first source region is formed on the upper surface of the wafer by photolithography, etching, and N-type ion implantation. The depth of the N+ type first source region is lower than the P-type well layer, and finally all hard masks are washed away.

[0088] like Figure 6 As shown, the first hard mask forms a covered area and an exposed area on the wafer's top surface. The covered area consists of a plurality of rectangular regions arranged in an array. The covered area is covered by the first hard mask, while the area outside the covered area is the exposed area. The wafer's top surface in the exposed area is exposed. Using the first hard mask as a mask, photolithography, etching, and N-type ion implantation are performed to form an N+-type first source region on the wafer's top surface, with a cross-sectional shape identical to that of the exposed area.

[0089] Step S4, forming a second type second source region.

[0090] Figure 9 FIG2 shows a top view of a fin field effect transistor with an integrated low barrier diode manufactured according to the manufacturing method of this embodiment at this step, Figure 10 for Figure 9 In the cross-section diagram along line A-A', Figure 11 for Figure 9 In the cross-section diagram of B-B', Figures 9 to 11 As shown, a second hard mask is grown on the surface of the wafer, and a P+ type second source region is formed on the upper surface of the wafer by photolithography, etching, and P-type ion implantation. The depth of the P+ type second source region can penetrate the P-type well layer or the N-type current diffusion layer, and finally all the hard masks are washed away.

[0091] like Figure 9 As shown, the second hard mask has a plurality of openings, each of which is a first rectangular shape and is distributed in an array. The second hard mask also forms a covered area and an exposed area on the upper surface of the wafer. The area where the first rectangular openings are located is the exposed area, and the area other than the exposed area is the covered area. Figure 6 The areas shown correspond to the exposed areas of the first hard mask, with the covered areas of the second hard mask corresponding to the exposed areas of the first hard mask. The wafer's top surface in the covered areas of the second hard mask is covered by the second hard mask, while the wafer's top surface in the exposed areas of the second hard mask remains exposed. Using the second hard mask as a mask, photolithography, etching, and P-type ion implantation are performed to form a P+-type second source region on the wafer's top surface with a cross-sectional shape identical to that of the exposed areas of the second hard mask.

[0092] In this embodiment, the N+ type first source region is located below the source metal and is doped with a high concentration (usually >1×10 19 cm -3 ), significantly reducing the potential barrier at the metal-semiconductor interface, forming an ohmic contact and reducing current losses when flowing through the source. The N+ first source region forms a PN junction with the P-type well layer. When a positive voltage is applied to the gate, the P-type well layer inverts to form a channel, and the N+ first source region acts as a carrier injection source, providing conductive electrons.

[0093] The P+ type second source region short-circuits the P-type well layer where the channel is located to the source through metal, ensuring that the potential of the P-well region is consistent with the source, avoiding false start-up or latch-up effects due to potential fluctuations.

[0094] Step S5: forming a first trench.

[0095] Figure 12 FIG2 shows a top view of a fin field effect transistor with an integrated low barrier diode manufactured according to the manufacturing method of this embodiment at this step, Figure 13 for Figure 12 In the cross-section diagram along line A-A', Figure 14 for Figure 12 In the cross-section diagram at B-B', Figure 15 for Figure 12 In the cross-section diagram of C-C', Figures 12 to 15 As shown, a third hard mask is grown on the surface of the wafer, and a first trench is formed by photolithography and etching. The depth of the first trench must be lower than the P-type well layer and can penetrate the current diffusion layer.

[0096] like Figure 12 As shown, the third hard mask also has several openings, each of which is a second rectangular shape. These second rectangular openings are arranged in an array. Notably, all of the second rectangular openings in the third hard mask fall within the covered area of ​​the second hard mask. The third hard mask also forms covered and exposed areas on the wafer's top surface. The area containing the second rectangular openings is the exposed area, while the area outside the exposed area is the covered area. The wafer's top surface in the covered area of ​​the third hard mask is covered by the third hard mask, while the wafer's top surface in the exposed area of ​​the third hard mask is exposed. The third hard mask is used as a mask for photolithography and etching, forming a first trench structure on the wafer's top surface with a cross-sectional shape identical to that of the exposed area of ​​the third hard mask. These first trenches are each formed as quadrangular prism-shaped grooves extending downward from the wafer's top surface. These grooves are arranged in an array on the wafer's top surface.

[0097] The first trench is used to accommodate the gate electrode. In the first direction, a fin FIN is formed between two adjacent first trenches. The spacing between two adjacent first trenches in the first direction, i.e., the fin width, is 50-100 nm. When a voltage is applied between the source and the gate, the doped electrons gather at the contact surface between the P-well layer and the gate, forming a three-dimensional conductive channel with an inverted U-shape in a cross-section perpendicular to the X-direction. The gates on both sides of the channel can control the channel simultaneously, thereby causing a three-dimensional inversion phenomenon in the channel region.

[0098] Step S6: forming a second type of sidewall protection zone.

[0099] Figure 16 FIG2 shows a top view of a fin field effect transistor with an integrated low barrier diode manufactured according to the manufacturing method of this embodiment at this step, Figure 17 for Figure 16 In the cross-section diagram along line A-A', Figure 18 for Figure 16 In the cross-section diagram at B-B', Figure 19 for Figure 16 In the cross-section diagram of C-C', Figures 16 to 19 As shown, P-type sidewall injection is performed on the wafer surface to form a P-type sidewall protection zone, ensuring that the concentration of the sidewall protection zone is much lower than the concentration of the first source region and greater than the concentration of the current diffusion layer, so that the first source region will not be inverted and part of the current diffusion layer will be inverted to P type.

[0100] Step S7: forming a second type of bottom protection zone.

[0101] Figure 20 FIG2 shows a top view of a fin field effect transistor with an integrated low barrier diode manufactured according to the manufacturing method of this embodiment at this step, Figure 21 for Figure 20 In the cross-section diagram along line A-A', Figure 22 for Figure 20 In the cross-section diagram at B-B', Figure 23 for Figure 20 In the cross-section diagram of C-C', Figures 20 to 23 As shown, the third hard mask is not washed away, and a fourth hard mask is deposited on the wafer surface. The wafer surface is then etched through a self-aligned process until the area at the bottom of the trench is exposed. P-type implantation is then performed to form a P-type bottom protection zone at the bottom of the first trench. At the same time, the P-type bottom protection zone is connected to the P-type sidewall protection zone to ensure that the potential of the P-type bottom protection zone is always close to the potential of the P-type well layer.

[0102] It should be noted that the implantation of the first trench bottom protection area cannot be performed in step S6, otherwise the FIN structure may be easily pinched off.

[0103] like Figure 20As shown, the fourth hard mask deposited on the wafer surface covers the entire upper surface of the wafer. After etching, the fourth hard mask still covers the sidewalls and bottom edge of the first trench, exposing the central area of ​​the bottom of the first trench. Etching is performed using the fourth hard mask as a mask. A bottom protection area connected to the sidewall protection area can be formed in the central area of ​​the bottom of the first trench. The size of the central area of ​​the bottom of the first trench can be precisely controlled by the thickness relationship between the third hard mask and the fourth hard mask.

[0104] In this technical solution, the injection width of the protection zone at the bottom of the trench is precisely controlled through a self-alignment process, so that one side of the first trench continues to conduct current, thereby enhancing the conduction performance of the device and reducing device resistance and loss.

[0105] Step S8: forming a gate oxide layer and a gate electrode.

[0106] Figure 24 FIG2 shows a top view of a fin field effect transistor with an integrated low barrier diode manufactured according to the manufacturing method of this embodiment at this step, Figure 25 for Figure 24 In the cross-section diagram along line A-A', Figure 26 for Figure 24 In the cross-section diagram at B-B', Figure 27 for Figure 24 In the cross-section diagram of C-C', Figures 24 to 27 As shown, all masks are washed away, and an oxide layer, namely the gate oxide layer, is formed on the surface of the wafer through an oxidation process, and then gate polysilicon is formed through a deposition process, and the excess oxide layer and polysilicon are removed through photolithography and etching.

[0107] Step S9: forming a second trench.

[0108] Figure 28 FIG2 shows a top view of a fin field effect transistor with an integrated low barrier diode manufactured according to the manufacturing method of this embodiment at this step, Figure 29 for Figure 28 In the cross-section diagram along line A-A', Figure 30 for Figure 28 In the cross-section diagram of B-B', Figures 28 to 30As shown, the second trench is formed by deposition, photolithography, and etching processes. It should be noted that the second trench can fall entirely in the N+ type first source region, entirely in the P+ type second source region, or partially in the N+ type first source region and partially in the P+ type second source region. This embodiment shows the case where the second trench partially falls in the N+ type first source region and partially in the P+ type second source region. The depth of the second trench may not be completely equal to the depth of the first trench, and the lowest point of the second trench may be higher than the lowest point of the first trench, but it is necessary to ensure that the second trench is etched into the current diffusion layer. At the same time, the second trench can be etched into a shape and stacking method where the trench contacts the current diffusion layer by etching in multiple times.

[0109] In this embodiment, the second trench is in a quadrangular prism shape, the bottom plane of the trench is located in the current diffusion layer, a plurality of second trenches are distributed in an array, and the second trenches do not contact the first trenches.

[0110] Step S10: forming a source and a drain.

[0111] A source metal is formed in the second trench through a metallization process, and a drain is formed under the first substrate.

[0112] The source electrode makes ohmic contact or Schottky contact with the sidewall of the second trench to form a diode structure. The P-type sidewall protection zone and the P-type bottom protection zone of the first trench will form a pinch-off effect on the ohmic contact or Schottky contact. In the blocking state, the barrier of the Schottky diode is not directly exposed to the high electric field, which can improve the blocking capability of the device. Figure 31 As shown, when the contact is an ohmic contact, the diode is a new type of diode with a pinch-off barrier, such as Figure 32 As shown, when the contact is a Schottky contact, it is a Schottky diode.

[0113] Example 3 This embodiment provides a fin field-effect transistor with an integrated low-barrier diode, comprising a substrate 1, a drift region 2, a well layer 3, a first source region 401, a second source region 402, a first trench 5, a sidewall protection zone 601, a bottom protection zone 602, a gate oxide layer 7, a gate electrode 8, a second trench 9, and a source 10. Unlike embodiment 1, the bottom of the second trench in this embodiment is configured to be stepped.

[0114] Based on Example 1, the same structure is not repeated here.

[0115] The opening of the second trench extends downward from the upper surface of the first source region and / or the second source region. The opening of the second trench may be entirely located in the N+ type first source region, entirely located in the P+ type second source region, or partially located in the N+ type first source region and partially located in the P+ type second source region. This embodiment shows a case where the second trench partially lies in the N+ type first source region and partially lies in the P+ type second source region.

[0116] The depth of the second trench may not be completely equal to the depth of the first trench, and the lowest point of the second trench may be higher than the lowest point of the first trench. However, it is necessary to ensure that the lowest point of the second trench extends to the current diffusion layer.

[0117] In this embodiment, the bottom of the second trench is stepped, and the lowest point of the second trench is located in the current diffusion layer. Specifically, the second trench can be regarded as a structure formed by two quadrangular prism-shaped grooves, which extend downward from the upper surface of the wafer to form a first quadrangular prism-shaped groove. The first quadrangular prism-shaped groove just passes through the P-type well layer, and a second quadrangular prism-shaped groove continues to extend downward from the bottom center of the first quadrangular prism-shaped groove. The bottom area of ​​the first quadrangular prism is larger than the bottom area of ​​the second quadrangular prism, so that the bottom of the second trench is stepped. Several second trenches have the same structure and are distributed in an array. The second trench does not contact the first trench.

[0118] The source electrode is arranged in the second trench and forms an ohmic contact or a Schottky contact with the sidewall of the trench to form a diode structure. The bottom of the second trench is stepped to improve the contact effect.

[0119] It should be noted that the shapes, sizes, numbers and arrangements of the first source region, the second source region, the first trench and the second trench in this embodiment are only used as examples and are not limited thereto. Those skilled in the art may make adjustments according to actual needs.

[0120] Example 4 This embodiment provides a method for manufacturing a fin field effect transistor with an integrated low barrier diode, which can realize the fin field effect transistor with an integrated low barrier diode described in Example 3, and includes the following steps.

[0121] Steps S1 to S8 of the manufacturing method in this embodiment are the same as steps S1 to S8 in Example 2, and are not described in detail here.

[0122] Step S9: forming a second trench.

[0123] Figure 33 FIG2 shows a top view of a fin field effect transistor with an integrated low barrier diode manufactured according to the manufacturing method of this embodiment at this step, Figure 34 for Figure 33 In the cross-section diagram along line A-A', Figure 35 for Figure 33In the cross-section diagram of B-B', Figures 33 to 35 As shown, the second trench is formed by deposition, photolithography, and etching processes. It should be noted that the second trench can fall entirely in the N+ type first source region, entirely in the P+ type second source region, or partially in the N+ type first source region and partially in the P+ type second source region. This embodiment shows the case where the second trench partially falls in the N+ type first source region and partially in the P+ type second source region. The depth of the second trench may not be completely equal to the depth of the first trench, and the lowest point of the second trench may be higher than the lowest point of the first trench, but it is necessary to ensure that the second trench is etched into the current diffusion layer. At the same time, the second trench can be etched into a shape and stacking method where the trench contacts the current diffusion layer by etching in multiple times.

[0124] In this embodiment, the bottom of the second trench is stepped, and the lowest point of the second trench is located in the current diffusion layer. Specifically, the second trench can be regarded as a structure formed by two quadrangular prism-shaped grooves, which extend downward from the upper surface of the wafer to form a first quadrangular prism-shaped groove. The first quadrangular prism-shaped groove just passes through the P-type well layer, and a second quadrangular prism-shaped groove continues to extend downward from the bottom center of the first quadrangular prism-shaped groove. The bottom area of ​​the first quadrangular prism is larger than the bottom area of ​​the second quadrangular prism, so that the bottom of the second trench is stepped. Several second trenches have the same structure and are distributed in an array. The second trench does not contact the first trench.

[0125] Step S10: forming a source and a drain.

[0126] A source metal is formed in the second trench through a metallization process, and a drain is formed under the first substrate.

[0127] The source electrode makes ohmic contact or Schottky contact with the sidewall of the second trench to form a diode structure. The P-type sidewall protection zone and the P-type bottom protection zone of the first trench will form a pinch-off effect on the ohmic contact or Schottky contact. In the blocking state, the barrier of the Schottky diode is not directly exposed to the high electric field, which can improve the blocking capability of the device. Figure 36 As shown in , when the contact is an ohmic contact, the diode is a new type of diode with a pinch-off barrier. Figure 37 As shown, when the contact is a Schottky contact, the diode is a Schottky diode.

[0128] Example 5 This embodiment provides a method for manufacturing a fin field effect transistor with an integrated low-barrier diode. The difference from Example 2 is that the second trench of this embodiment extends to the current diffusion layer and the depth of the second trench is greater than the depth of the first trench, that is, the lowest point of the second trench is lower than the lowest point of the first trench.

[0129] It is worth noting that in this embodiment, a P-type protection implant is also performed at the bottom of the second trench, such as Figure 38When the device diode is required to be turned on, the current flows from the metal electrode in the second trench through the junction between the sidewall of the second trench and the current diffusion layer to the current diffusion layer, and then diffuses to the epitaxial layer and the substrate in sequence, and finally reaches the drain.

[0130] The simulation results obtained by simulating the device structure of Example 5 are described in detail below.

[0131] The forward conduction characteristics of the device were simulated under the following conditions: the gate-drain voltage was fixed at 20V, and the drain-source voltage was swept from 0V to 2V.

[0132] When the drain-source voltage is 2V, the current density distribution along the CC' section is as follows: Figure 42 As shown, from Figure 42 It can be seen that electrons are injected downward into the drift region through the FIN structure, and the entire FIN becomes an effective conductive channel.

[0133] The corresponding forward IV characteristic curve is as follows Figure 43 As shown, from Figure 43 As can be seen from the curve, the device has relatively excellent conduction characteristics, with a specific on-resistance of about 2mΩ·cm 2 .

[0134] The conduction characteristics of the body diode were evaluated. To prevent channel conduction, the gate-source voltage was set to -5V and the drain-source voltage was swept from 0V to -3.5V.

[0135] The current density distribution along the BB' section is as follows: Figure 44 As shown, the current density distribution along the D-D' section is as follows Figure 45 As shown in FIG, it can be seen from the simulation results that the current does not flow through the parasitic anti-parallel PN junction diode, but flows completely through the low barrier diode integrated on the sidewall.

[0136] Figure 46 Further comparisons of the third-quadrant characteristics of the two structures, with and without integrated low-barrier diodes, show that the third-quadrant diode characteristics of the device using the structure of this embodiment can be turned on at only approximately 0.6V, significantly reducing reverse conduction and switching losses. Even when the drain-source voltage reaches -3.5V, the parasitic anti-parallel PN junction diode remains non-conductive, effectively suppressing the risk of bipolar degradation.

Claims

1. A fin field effect transistor with an integrated low barrier diode, characterized in that: include: A first-type substrate (1); a first-type drift region (2) formed on the substrate; a second-type well layer (3) formed in the drift region; a source region (4) formed in the well layer; a first trench (5) extending downward from the upper surface of the source region and penetrating the well layer; a protection zone (6) formed on the sidewalls and bottom of the first trench; and a gate oxide layer (7) covering the inner surface of the first trench. A gate electrode (8) filled in the first trench; a second trench (9) extending downward from the upper surface of the source region to the drift region; A source electrode (10) is filled in the second trench.

2. The fin field effect transistor with integrated low barrier diode according to claim 1, characterized in that: The substrate (1) is heavily doped, and the drift region (2) comprises a lightly doped first-type epitaxial layer (201) formed on the substrate (1) and a moderately doped first-type current diffusion layer (202) located on the epitaxial layer.

3. The fin field effect transistor with integrated low barrier diode according to claim 1 or 2, characterized in that: The source region comprises a first source region (401) of a first type and a second source region (402) of a second type, wherein the first source region (401) and the second source region (402) jointly cover the entire upper surface of the well region, and the depth of the first source region does not exceed the well layer.

4. The fin field effect transistor with integrated low barrier diode according to claim 3, characterized in that: The protection zone (6) comprises a sidewall protection zone (601) and a bottom protection zone (602), wherein the impurity concentration of the sidewall protection zone is greater than the impurity concentration of the current diffusion layer (202) and less than the impurity concentration of the first source zone (401).

5. The fin field effect transistor with integrated low barrier diode according to claim 1, characterized in that: The distance between two adjacent first trenches in the first direction is 50 nm to 100 nm.

6. The fin field effect transistor with integrated low barrier diode according to claim 3, characterized in that: The first trench (5) extends from the upper surface of the first source region (401) to the current diffusion layer (202) or penetrates the current diffusion layer, and the first trench does not contact the second source region (402).

7. The fin field effect transistor with integrated low barrier diode according to claim 1, characterized in that: The shape of the second trench (9) in contact with the drift region (2) is step-shaped.

8. The fin field effect transistor with integrated low barrier diode according to claim 2, characterized in that: The second groove (9) extends to the current diffusion layer (202).

9. The fin field effect transistor with integrated low barrier diode according to claim 1 or 2, characterized in that: The first type has an N-type conductivity and the second type has a P-type conductivity; or the first type has a P-type conductivity and the second type has an N-type conductivity.

10. A method for manufacturing a fin field effect transistor with an integrated low barrier diode, which realizes the fin field effect transistor with an integrated low barrier diode according to any one of claims 1 to 9, characterized in that: The following steps are involved: S1, forming a first type substrate and a first type drift region; S2, forming a second type well layer; S3, forming the first type first source region; S4, forming the second type second source region; S5, forming a first trench; S6, forming the second type of sidewall protection zone; S7, forming a second type of bottom protection zone connected to the side wall protection zone; S8, forming a gate oxide layer and a gate electrode in the first trench; S9, forming a second trench; S10, forming a source in the second trench.

Images