A fin field effect transistor integrated with a low-barrier diode and a manufacturing method thereof

Abstract

This invention discloses a fin field-effect transistor with an integrated low-barrier diode and its manufacturing method, relating to the field of power semiconductor device manufacturing. The transistor includes: a first-type substrate; a first-type drift region formed on the substrate; a second-type well layer formed in the drift region; a source region formed in the well layer; a first trench extending downward from the upper surface of the source region and penetrating the well layer; a protection zone formed on the sidewalls and bottom of the first trench; a gate oxide layer covering the inner surface of the first trench; a gate electrode filled in the first trench; a second trench extending downward from the upper surface of the source region to the drift region; and a source electrode filled in the second trench. This invention's fin field-effect transistor with an integrated low-barrier diode and its manufacturing method, by integrating a low-barrier diode as a freewheeling path within a power FINFET device, can reduce device switching losses and degradation risks, thereby improving device reliability.

Description

Technical Field

[0001] This invention relates to the field of power semiconductor device manufacturing technology, specifically to a fin field-effect transistor with integrated low-barrier diode and its manufacturing method. Background Technology

[0002] Switching devices in a power converter control the switching of input electrical energy, switching the circuit according to different control signals. Common power switches include transistors, MOSFETs, and IGBTs. In most power converter applications, the switching devices require a freewheeling diode to provide a reverse freewheeling path. Currently, there are three ways to achieve freewheeling: the first is to use a switching device and a freewheeling diode in parallel in the circuit, but this method has the problems of high cost and large parasitic parameters; the second, taking a power MOSFET as an example, is to achieve freewheeling through its own parasitic anti-parallel PN junction diode, however, this parasitic diode has problems such as long reverse recovery time, large reverse recovery charge, and easy bipolar degradation of the device; the third is to directly integrate the diode as the freewheeling path in the power device design.

[0003] For example, there is a Chinese patent with publication number CN119835982B, which relates to the structure of a trench gate power MOSFET and a method for manufacturing a trench gate power MOSFET. It requires parallel connection with a freewheeling diode in the circuit or to achieve freewheeling through its own parasitic diode, which has the problems of high cost, large parasitic parameters, or easy bipolar degradation of the device. Summary of the Invention

[0004] To improve circuit stability, this invention proposes a fin field-effect transistor with integrated low-barrier diode and its manufacturing method. By integrating a low-barrier diode as a freewheeling path inside the power FINFET device, the switching losses and degradation risk of the device can be reduced, thereby improving the device reliability.

[0005] To achieve the above objectives, the present invention adopts the following technical solution: a fin field-effect transistor integrating a low-barrier diode, comprising: a first type substrate; a first type drift region formed on the substrate; a second type well layer formed in the drift region; a source region formed in the well layer; a first trench extending downward from the upper surface of the source region and penetrating the well layer; a protection zone formed on the sidewalls and bottom of the first trench; a gate oxide layer covering the inner surface of the first trench; a gate electrode filled in the first trench; a second trench extending downward from the upper surface of the source region to the drift region; and a source electrode filled in the second trench.

[0006] In this technical solution, by sinking the source into the second trench and forming a diode structure with the second trench in ohmic contact and / or Schottky contact, the bipolar degradation of the device caused by the parasitic anti-parallel PN junction diode is avoided.

[0007] Preferably, the substrate is heavily doped, and the drift region includes a lightly doped first-type epitaxial layer formed on the substrate and a medium-doped first-type current diffusion layer located on the epitaxial layer.

[0008] Preferably, the source region includes a first type of first source region and a second type of second source region, the first source region and the second source region together cover the entire upper surface of the well region, and the depth of the first source region does not exceed the well layer.

[0009] Preferably, the protected area includes a sidewall protected area and a bottom protected area, wherein the impurity concentration in the sidewall protected area is greater than the impurity concentration in the current diffusion layer and less than the impurity concentration in the first source region.

[0010] Preferably, the spacing between two adjacent first trenches in the first direction is 50 nm to 100 nm.

[0011] Preferably, the first trench extends from the upper surface of the first source region to or through the current diffusion layer, and the first trench does not contact the second source region.

[0012] Preferably, the second groove has a stepped shape in contact with the drift area.

[0013] Preferably, the second trench extends into the current diffusion layer.

[0014] Preferably, the first type has an N-type conductivity and the second type has a P-type conductivity; or the first type has a P-type conductivity and the second type has an N-type conductivity.

[0015] The present invention also employs the following technical solution: a method for manufacturing a fin field-effect transistor with an integrated low-barrier diode, realizing the above-mentioned fin field-effect transistor with an integrated low-barrier diode, comprising the following steps: S1, forming a first type substrate and a first type drift region; S2, forming a second type well layer; S3, forming a first type first source region; S4, forming a second type second source region; S5, forming a first trench; S6, forming a second type sidewall protection region; S7, forming a second type bottom protection region connected to the sidewall protection region; S8, forming a gate oxide layer and a gate electrode in the first trench; S9, forming a second trench; S10, forming a source electrode in the second trench.

[0016] The beneficial effects of this invention are:

[0017] 1) Reduce the on-resistance and conduction loss of the device by using the FINFET structure;

[0018] 2) Improve device reliability and reduce device switching losses by integrating low-barrier diodes inside the chip. Attached Figure Description

[0019] Figure 1 This is a top view of the fin field-effect transistor of Embodiment 1 of the present invention without the three electrodes.

[0020] Figure 2 yes Figure 1 Cross-sectional view at B-B'.

[0021] Figure 3 yes Figure 1 Cross-sectional view at C-C'.

[0022] Figure 4 This is a schematic diagram of step S1 in embodiment 2 of the present invention.

[0023] Figure 5 This is a schematic diagram of step S2 in embodiment 2 of the present invention.

[0024] Figure 6 This is a top view of the wafer during step S3 of embodiment 2 of the present invention.

[0025] Figure 7 This is a cross-sectional view of the wafer along A-A' during step S3 of embodiment 2 of the present invention.

[0026] Figure 8 This is a cross-sectional view of the wafer along line B-B' during step S3 of embodiment 2 of the present invention.

[0027] Figure 9 This is a top view of the wafer during step S4 of embodiment 2 of the present invention.

[0028] Figure 10 yes Figure 9 Cross-sectional view at A-A'.

[0029] Figure 11 yes Figure 9 Cross-sectional view at B-B'.

[0030] Figure 12 This is a top view of the wafer during step S5 of embodiment 2 of the present invention.

[0031] Figure 13 yes Figure 12 Cross-sectional view at A-A'.

[0032] Figure 14 yes Figure 12 Cross-sectional view at B-B'.

[0033] Figure 15 yes Figure 12 Cross-sectional view at C-C'.

[0034] Figure 16 This is a top view of the wafer during step S6 of embodiment 2 of the present invention.

[0035] Figure 17 yes Figure 16 Cross-sectional view at A-A'.

[0036] Figure 18 yes Figure 16 Cross-sectional view at B-B'.

[0037] Figure 19 yes Figure 16 Cross-sectional view at C-C'.

[0038] Figure 20 This is a top view of the wafer during step S7 of embodiment 2 of the present invention.

[0039] Figure 21 yes Figure 20 Cross-sectional view at A-A'.

[0040] Figure 22 yes Figure 20 Cross-sectional view at B-B'.

[0041] Figure 23 yes Figure 20 Cross-sectional view at C-C'.

[0042] Figure 24 This is a top view of the wafer during step S8 of embodiment 2 of the present invention.

[0043] Figure 25 yes Figure 24 Cross-sectional view at A-A'.

[0044] Figure 26 yes Figure 24 Cross-sectional view at B-B'.

[0045] Figure 27 yes Figure 24 Cross-sectional view at C-C'.

[0046] Figure 28 This is a top view of the wafer during step S9 of embodiment 2 of the present invention.

[0047] Figure 29 yes Figure 28 Cross-sectional view at A-A'.

[0048] Figure 30 yes Figure 28 Cross-sectional view at B-B'.

[0049] Figure 31 This is a schematic diagram of the ohmic contact in step S10 of embodiment 2 of the present invention.

[0050] Figure 32 This is a schematic diagram of the Schottky contact in step S10 of embodiment 2 of the present invention.

[0051] Figure 33 This is a top view of the wafer during step S9 of embodiment 4 of the present invention.

[0052] Figure 34 yes Figure 33 Cross-sectional view at A-A'.

[0053] Figure 35 yes Figure 33 Cross-sectional view at B-B'.

[0054] Figure 36 This is a schematic diagram of the ohmic contact in step S10 of embodiment 4 of the present invention.

[0055] Figure 37 This is a schematic diagram of the Schottky contact in step S10 of embodiment 4 of the present invention.

[0056] Figure 38 This is a top view of the wafer during step S9 of embodiment 5 of the present invention.

[0057] Figure 39 yes Figure 38 Cross-sectional view at B-B'.

[0058] Figure 40 yes Figure 38 Cross-sectional view at C-C'.

[0059] Figure 41 yes Figure 38 Cross-sectional view at D-D'.

[0060] Figure 42 This is a current density distribution diagram of the C-C' section in Embodiment 5 of the present invention.

[0061] Figure 43 This is a graph showing the forward conduction characteristics of the device in Embodiment 5 of the present invention.

[0062] Figure 44 This is the current density distribution diagram of the B-B' section in Embodiment 5 of the present invention.

[0063] Figure 45 This is a current density distribution diagram of the D-D' section in Embodiment 5 of the present invention.

[0064] Figure 46 This is a comparison chart of the simulation characteristics in the third quadrant of Embodiment 5 of the present invention between devices with integrated low-barrier diodes and those without integrated low-barrier diodes.

[0065] Reference numerals: Substrate 1; Drift region 2; Epitaxial layer 201; Current diffusion layer 202; Well layer 3; Source region 4; First source region 401; Second source region 402; First trench 5; Protective environment 6; Sidewall protective environment 601; Bottom protective environment 602; Gate oxide layer 7; Gate electrode 8; Second trench 9; Source 10; Drain 11; First hard mask Y1; Second hard mask Y2; Third hard mask Y3; Fourth hard mask Y4. Detailed Implementation

[0066] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only one preferred embodiment of this invention and are only used to explain this invention. They do not limit the scope of protection of this invention. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0067] For clarity, the thickness of layers and regions has been enlarged in the accompanying drawings. It can also be understood that when a layer is referred to as "above" another layer or substrate, it can be directly on top of that layer or substrate, or an intercalation layer may be present. Furthermore, the terms "Type I" and "Type II" refer to opposite semiconductor conductivity types, such as N-type and P-type. It should be understood that when Type I is N-type, Type II refers to P-type, and correspondingly, when Type I is P-type, Type II refers to N-type.

[0068] Example 1

[0069] This embodiment provides a finned field-effect transistor with an integrated low-barrier diode, referenced... Figures 1 to 3 It includes a substrate 1, a drift region 2, a well layer 3, a first source region 401, a second source region 402, a first trench 5, a sidewall protection zone 601, a bottom protection zone 602, a gate oxide layer 7, a gate electrode 8, a second trench 9, and a source electrode 10.

[0070] In this embodiment, the substrate is a heavily doped first type (e.g., N+ type) substrate, the drift region includes a lightly doped first type (e.g., N- type) epitaxial layer 201 formed on the substrate, and a moderately doped first type (e.g., N- type) current diffusion layer 202 formed on the epitaxial layer, the well layer is formed in the current diffusion layer, extends downward from the upper surface of the current diffusion layer and the depth does not exceed the depth of the current diffusion layer.

[0071] It should be noted that "heavy doping", "medium doping" and "light doping" refer to the impurity concentration of the N-type dielectric used to form the layer or region. These three terms are relative. In other words, in this embodiment, the impurity concentration of the substrate is greater than that of the current diffusion layer, and the impurity concentration of the current diffusion layer is greater than that of the epitaxial layer.

[0072] The first source region and the second source region are formed in the well layer. The second source region is configured to extend downward from several independent rectangular regions on the upper surface of the well layer. The first source region extends downward from the region on the upper surface of the well layer outside the rectangular regions and the depth of the first source region does not exceed the well layer. The depths of the first source region and the second source region can be different. The first source region and the second source region can cover the entire upper surface of the well layer.

[0073] It should be noted that the depth of the first source region does not exceed the depth of the well layer, while the depth of the second source region may not exceed the depth of the well layer, may penetrate the well layer, or may extend to the current diffusion layer.

[0074] The opening of the first trench is rectangular, extending downward from the upper surface of the first source region. Its depth must penetrate the well region, or it can extend to or through the current diffusion layer.

[0075] The spacing between adjacent first trenches in the first direction (Y direction) is 50nm to 100nm to ensure that the channel region can form a "bulk inversion", thereby increasing the carrier concentration of the inversion layer, reducing surface scattering, reducing the lateral electric field in the channel, improving the mobility of the device, and enabling the device to have the FINFET effect.

[0076] The sidewall protection zone is formed on the trap layer and current diffusion layer of the first trench sidewall and extends to the current diffusion layer at the bottom edge. The bottom protection zone is formed on the current diffusion layer at the center of the bottom of the first trench. The bottom protection zone is connected to the sidewall protection zone and electrically connected to the trap layer, so that the potential of the bottom protection zone is always close to the potential of the trap layer.

[0077] A gate oxide layer is formed on the inner surface of the first trench and completely covers the inner surface of the first trench and extends to cover the upper surface of the first source region in the region between adjacent first trenches in the first direction. The gate electrode is filled in the first trench.

[0078] The opening of the second trench can be rectangular, extending downward from the upper surface of the first source region and / or the second source region. The opening of the second trench can fall entirely within the N+ type first source region, entirely within the P+ type second source region, or partially within the N+ type first source region and partially within the P+ type second source region. This embodiment shows the case where the second trench falls partially within the N+ type first source region and partially within the P+ type second source region.

[0079] The depth of the second trench may not be exactly the same as the depth of the first trench, and the lowest point of the second trench may be higher than the lowest point of the first trench, but it is necessary to ensure that the lowest point of the second trench extends to the current diffusion layer.

[0080] In this embodiment, the second trench is a quadrangular prism, the bottom plane of the trench is located in the current diffusion layer, and a plurality of second trenches are distributed in an array, and the second trenches do not contact the first trench.

[0081] The source is disposed in the second trench, making an ohmic or Schottky contact with the sidewall of the second trench, forming a diode structure. The P-type sidewall protection zone and P-type bottom protection zone of the first trench create a pinch-off effect on the ohmic / ohmic contact. In the blocking state, the barrier of this Schottky diode is not directly exposed to a high electric field, which can improve the blocking capability of the device. When the contact is an ohmic contact, the diode is a novel barrier-pinch diode; when the contact is a Schottky contact, it is a Schottky diode.

[0082] It should be noted that the shape, size, number, and arrangement of the first source region, second source region, first trench, and second trench in this embodiment are only examples and are not limited thereto. Those skilled in the art can make adjustments according to actual needs.

[0083] Example 2

[0084] This embodiment provides a method for manufacturing a fin field-effect transistor with an integrated low-barrier diode, which can realize the fin field-effect transistor with an integrated low-barrier diode as described in Embodiment 1, including the following steps.

[0085] Step S1: Forming a first-type substrate and a first-type drift region.

[0086] In this embodiment, type 1 refers to type N and type 2 refers to type P.

[0087] Figure 4 The diagram shows a cross-sectional view of the fin field-effect transistor with an integrated low-barrier diode fabricated according to the method described in this embodiment at this step. Figure 4 As shown, an N-type heavily doped N+ type substrate wafer is prepared, and an N-type epitaxial layer and an N-type current diffusion layer are grown on the N+ type substrate wafer. The epitaxial layer and the current diffusion layer together constitute the drift region.

[0088] Step S2, forming the second type of trap layer.

[0089] Figure 5 The diagram shows a cross-sectional view of the fin field-effect transistor with an integrated low-barrier diode fabricated according to the method described in this embodiment at this step. Figure 5 As shown, P-type implantation is performed on the upper surface of the wafer by generalized implantation to form a P-type well layer. The depth of the P-type well layer does not exceed that of the N-type current diffusion layer.

[0090] Step S3: Form the first source region of the first type.

[0091] Figure 6A top view of the fin field-effect transistor with an integrated low-barrier diode fabricated according to the method described in this embodiment is shown at this step. Figure 7 for Figure 6 In the cross-sectional view at A-A', Figure 8 for Figure 6 In the cross-sectional view of B-B', as shown Figures 6 to 8 As shown, a first hard mask is grown on the wafer surface. An N+ type first source region is formed on the upper surface of the wafer by photolithography, etching, and N-type ion implantation. The depth of the N+ type first source region is lower than that of the P-type well layer. Finally, all hard masks are washed away.

[0092] like Figure 6 As shown, a first hard mask forms a covered area and an exposed area on the upper surface of the wafer. The covered area consists of several rectangular regions arranged in an array. The covered area is covered by the first hard mask, and the area outside the covered area is the exposed area, where the upper surface of the wafer is exposed. By using the first hard mask as a mask for photolithography, etching, and N-type ion implantation, an N+ type first source region with the same cross-sectional shape as the exposed area can be formed on the upper surface of the wafer.

[0093] Step S4: Form the second type of second source region.

[0094] Figure 9 A top view of the fin field-effect transistor with an integrated low-barrier diode fabricated according to the method described in this embodiment is shown at this step. Figure 10 for Figure 9 In the cross-sectional view at A-A', Figure 11 for Figure 9 In the cross-sectional view of B-B', as shown Figures 9 to 11 As shown, a second hard mask is grown on the wafer surface. A P+ type second source region is formed on the upper surface of the wafer by photolithography, etching, and P-type ion implantation. The depth of the P+ type second source region can penetrate the P-type well layer or the N-type current diffusion layer. Finally, all hard masks are washed away.

[0095] like Figure 9 As shown, the second hard mask has several openings, each of which is a first rectangle, and these first rectangles are arranged in an array. The second hard mask also forms a covered area and an exposed area on the upper surface of the wafer. The area where the openings of the first rectangles are located is the exposed area, and the area excluding the exposed area is the covered area. Figure 6Corresponding to the regions shown, the area covered by the second hard mask is the exposed area of ​​the first hard mask, and vice versa. The wafer surface located in the covered area of ​​the second hard mask is covered by the second hard mask, while the wafer surface located in the exposed area of ​​the second hard mask is exposed. By using the second hard mask as a mask for photolithography, etching, and P-type ion implantation, a P+ type second source region with the same cross-sectional shape as the exposed area of ​​the second hard mask can be formed on the wafer surface.

[0096] In this embodiment, the N+ type first source region is located below the source metal, and is formed by high-concentration doping (typically >1×10⁻⁶). 19 cm -3 This significantly reduces the potential barrier at the metal-semiconductor interface, forming an ohmic contact and reducing losses when current flows through the source. The N+ type first source region forms a PN junction with the P-type well layer. When a positive voltage is applied to the gate, the P-type well layer inverts to form a channel, and the N+ type first source region acts as a carrier injection source, providing conductive electrons.

[0097] The P+ type second source region shorts the P-type well layer containing the channel to the source through a metal, ensuring that the potential of the P-well region is consistent with that of the source, and avoiding false turn-on or latch-up effects caused by potential fluctuations.

[0098] Step S5: Form the first trench.

[0099] Figure 12 A top view of the fin field-effect transistor with an integrated low-barrier diode fabricated according to the method described in this embodiment is shown at this step. Figure 13 for Figure 12 In the cross-sectional view at A-A', Figure 14 for Figure 12 In the cross-sectional view at B-B', Figure 15 for Figure 12 In the cross-sectional view of C-C', as shown Figures 12 to 15 As shown, a third hard mask is grown on the wafer surface, and a first trench is formed by photolithography and etching. The depth of the first trench must be lower than that of the P-type well layer, so that the current diffusion layer can be penetrated.

[0100] like Figure 12As shown, the third hard mask also has several openings, which are second rectangles arranged in an array. Notably, all the second rectangular openings of the third hard mask fall within the coverage area of ​​the second hard mask. The third hard mask also forms a coverage area and an exposed area on the upper surface of the wafer. The area where the second rectangular openings are located is the exposed area, and the area outside the exposed area is the coverage area. The upper surface of the wafer located in the coverage area of ​​the third hard mask is covered by the third hard mask, while the upper surface of the wafer located in the exposed area of ​​the third hard mask is exposed. The third hard mask performs photolithography and etching, which can form a first trench structure on the upper surface of the wafer with the same cross-sectional shape as the exposed area of ​​the third hard mask. The first trenches are all formed as quadrangular prism-shaped grooves extending downward from the upper surface of the wafer, and the grooves are arranged in an array on the upper surface of the wafer.

[0101] The first trench is used to accommodate the gate electrode. In the first direction, a fin is formed between two adjacent first trenches. The spacing between two adjacent first trenches in the first direction, i.e., the fin width, is 50-100nm. When a voltage is applied between the source and the gate, the doped electrons accumulate at the contact surface between the P-well layer and the gate, forming an inverted U-shaped three-dimensional conductive channel in a cross section perpendicular to the X direction. The gates on both sides of the channel can simultaneously control the channel, thereby triggering a three-dimensional inversion phenomenon in the channel region.

[0102] Step S6 forms the second type of sidewall protection zone.

[0103] Figure 16 A top view of the fin field-effect transistor with an integrated low-barrier diode fabricated according to the method described in this embodiment is shown at this step. Figure 17 for Figure 16 In the cross-sectional view at A-A', Figure 18 for Figure 16 In the cross-sectional view at B-B', Figure 19 for Figure 16 In the cross-sectional view of C-C', as shown Figures 16 to 19 As shown, P-type sidewall implantation is performed on the wafer surface to form a P-type sidewall protection zone. This ensures that the concentration of the sidewall protection zone is much lower than that of the first source region and greater than that of the current diffusion layer, so that the first source region will not be inverted and part of the current diffusion layer will be inverted to P-type.

[0104] Step S7 forms the second type of bottom protection zone.

[0105] Figure 20 A top view of the fin field-effect transistor with an integrated low-barrier diode fabricated according to the method described in this embodiment is shown at this step. Figure 21 for Figure 20 In the cross-sectional view at A-A', Figure 22 for Figure 20 In the cross-sectional view at B-B', Figure 23 for Figure 20 In the cross-sectional view of C-C', as shown Figures 20 to 23 As shown, without washing away the third hard mask, a fourth hard mask is deposited on the wafer surface. Then, the wafer surface is etched through a self-aligned process until the area at the bottom of the trench is exposed. Then, P-type implantation is performed to form a P-type bottom protection zone at the bottom of the first trench. At the same time, the P-type bottom protection zone and the P-type sidewall protection zone are connected to ensure that the potential of the P-type bottom protection zone is always close to the potential of the P-type well layer.

[0106] It should be noted that the injection of the first trench bottom protection zone cannot be performed in step S6, otherwise the FIN structure may be easily clamped.

[0107] like Figure 20 As shown, the fourth hard mask deposited on the wafer surface covers the entire upper surface of the wafer. After etching, the fourth hard mask still covers the sidewalls and bottom edge of the first trench, exposing the central area at the bottom of the first trench. By using the fourth hard mask as a mask for etching, a bottom protection zone connected to the sidewall protection zone can be formed in the central area at the bottom of the first trench. The size of the central area at the bottom of the first trench can be precisely controlled by the thickness relationship between the third hard mask and the fourth hard mask.

[0108] In this technical solution, the injection width of the bottom protection zone of the trench is precisely controlled by the self-aligned process, so that the current continues to conduct on one side of the first trench, thereby enhancing the conduction performance of the device and reducing the device resistance and loss.

[0109] Step S8: Form the gate oxide layer and the gate electrode.

[0110] Figure 24 A top view of the fin field-effect transistor with an integrated low-barrier diode fabricated according to the method described in this embodiment is shown at this step. Figure 25 for Figure 24 In the cross-sectional view at A-A', Figure 26 for Figure 24 In the cross-sectional view at B-B', Figure 27 for Figure 24 In the cross-sectional view of C-C', as shown Figures 24 to 27 As shown, all masks are washed away, and an oxide layer, namely the gate oxide layer, is formed on the wafer surface through an oxidation process. Then, a gate polysilicon is formed through a deposition process, and excess oxide layer and polysilicon are removed by photolithography and etching.

[0111] Step S9, forming the second trench.

[0112] Figure 28 A top view of the fin field-effect transistor with an integrated low-barrier diode fabricated according to the method described in this embodiment is shown at this step. Figure 29 for Figure 28 In the cross-sectional view at A-A', Figure 30 for Figure 28 In the cross-sectional view of B-B', as shown Figures 28 to 30 As shown, the second trench is formed through deposition, photolithography, and etching processes. It should be noted that the second trench can fall entirely within the N+ type first source region, entirely within the P+ type second source region, or partially within both. This embodiment illustrates the case where the second trench falls partially within the N+ type first source region and partially within the P+ type second source region. The depth of the second trench does not necessarily have to be equal to the depth of the first trench, and the lowest point of the second trench can be higher than the lowest point of the first trench, but it is necessary to ensure that the second trench is etched down to the current diffusion layer. Furthermore, the shape and stacking pattern of the contact between the trench and the current diffusion layer can be etched in multiple stages.

[0113] In this embodiment, the second trench is a quadrangular prism, the bottom plane of the trench is located in the current diffusion layer, and a plurality of second trenches are distributed in an array, and the second trenches do not contact the first trench.

[0114] Step S10: Form the source and drain.

[0115] The source metal is formed in the second trench using a metallization process. The drain is formed beneath the first-type substrate.

[0116] The source electrode is connected to an ohmic or Schottky contact on the sidewall of the second trench, forming a diode structure. The P-type sidewall protection zone and the P-type bottom protection zone of the first trench create a pinch-off effect on the ohmic or Schottky contact. In the blocking state, the barrier of this Schottky diode is not directly exposed to a high electric field, which improves the blocking capability of the device. Figure 31 As shown, when the contact is an ohmic contact, the diode is a novel type of pinch-off barrier diode, such as... Figure 32 As shown, when the contact is a Schottky contact, it is a Schottky diode.

[0117] Example 3

[0118] This embodiment provides a fin field-effect transistor with an integrated low-barrier diode, including a substrate 1, a drift region 2, a well layer 3, a first source region 401, a second source region 402, a first trench 5, a sidewall protection zone 601, a bottom protection zone 602, a gate oxide layer 7, a gate electrode 8, a second trench 9, and a source electrode 10. Unlike Embodiment 1, the bottom of the second trench in this embodiment is stepped.

[0119] Based on Example 1, the same structure will not be described again here.

[0120] The opening of the second trench extends downward from the upper surface of the first source region and / or the second source region. The opening of the second trench may fall entirely within the N+ type first source region, entirely within the P+ type second source region, or partially within the N+ type first source region and partially within the P+ type second source region. This embodiment illustrates the case where the second trench falls partially within the N+ type first source region and partially within the P+ type second source region.

[0121] The depth of the second trench may not be exactly the same as the depth of the first trench, and the lowest point of the second trench may be higher than the lowest point of the first trench, but it is necessary to ensure that the lowest point of the second trench extends to the current diffusion layer.

[0122] In this embodiment, the bottom of the second trench is stepped, and the lowest point of the second trench is located in the current diffusion layer. Specifically, the second trench can be regarded as a structure formed by two quadrangular prism-shaped grooves. The first quadrangular prism-shaped groove extends downward from the upper surface of the wafer and just penetrates the P-type well layer. The second quadrangular prism-shaped groove extends downward from the bottom center of the first quadrangular prism-shaped groove. The bottom area of ​​the first quadrangular prism is larger than the bottom area of ​​the second quadrangular prism, so that the bottom of the second trench is stepped. Several second trenches have the same structure and are distributed in an array. The second trenches do not contact the first trench.

[0123] The source is positioned within the second trench, making ohmic or Schottky contact with the trench sidewalls to form a diode structure. The stepped bottom of the second trench improves the contact effect.

[0124] It should be noted that the shape, size, number, and arrangement of the first source region, second source region, first trench, and second trench in this embodiment are only examples and are not limited thereto. Those skilled in the art can make adjustments according to actual needs.

[0125] Example 4

[0126] This embodiment provides a method for manufacturing a fin field-effect transistor with an integrated low-barrier diode, which can realize the fin field-effect transistor with an integrated low-barrier diode as described in Embodiment 3, and includes the following steps.

[0127] Steps S1 to S8 of the manufacturing method in this embodiment are the same as steps S1 to S8 in Embodiment 2, and will not be repeated here.

[0128] Step S9, forming the second trench.

[0129] Figure 33 A top view of the fin field-effect transistor with an integrated low-barrier diode fabricated according to the method described in this embodiment is shown at this step. Figure 34 for Figure 33 In the cross-sectional view at A-A', Figure 35 for Figure 33 In the cross-sectional view of B-B', as shown Figures 33 to 35 As shown, the second trench is formed through deposition, photolithography, and etching processes. It should be noted that the second trench can fall entirely within the N+ type first source region, entirely within the P+ type second source region, or partially within both. This embodiment illustrates the case where the second trench falls partially within the N+ type first source region and partially within the P+ type second source region. The depth of the second trench does not necessarily have to be equal to the depth of the first trench, and the lowest point of the second trench can be higher than the lowest point of the first trench, but it is necessary to ensure that the second trench is etched down to the current diffusion layer. Furthermore, the shape and stacking pattern of the contact between the trench and the current diffusion layer can be etched in multiple stages.

[0130] In this embodiment, the bottom of the second trench is stepped, and the lowest point of the second trench is located in the current diffusion layer. Specifically, the second trench can be regarded as a structure formed by two quadrangular prism-shaped grooves. The first quadrangular prism-shaped groove extends downward from the upper surface of the wafer and just penetrates the P-type well layer. The second quadrangular prism-shaped groove extends downward from the bottom center of the first quadrangular prism-shaped groove. The bottom area of ​​the first quadrangular prism is larger than the bottom area of ​​the second quadrangular prism, so that the bottom of the second trench is stepped. Several second trenches have the same structure and are distributed in an array. The second trenches do not contact the first trench.

[0131] Step S10: Form the source and drain.

[0132] The source metal is formed in the second trench using a metallization process. The drain is formed beneath the first-type substrate.

[0133] The source electrode is connected to an ohmic or Schottky contact on the sidewall of the second trench, forming a diode structure. The P-type sidewall protection zone and the P-type bottom protection zone of the first trench create a pinch-off effect on the ohmic or Schottky contact. In the blocking state, the barrier of this Schottky diode is not directly exposed to a high electric field, which improves the blocking capability of the device. Figure 36 As shown, when the contact is an ohmic contact, the diode is a novel type of pinch-off barrier diode. (As...) Figure 37 As shown, when the contact is a Schottky contact, the diode is a Schottky diode.

[0134] Example 5

[0135] This embodiment provides a method for manufacturing a fin field-effect transistor with an integrated low barrier diode. Unlike embodiment 2, in this embodiment, the second trench extends to the current diffusion layer and the depth of the second trench is greater than the depth of the first trench. That is, the lowest point of the second trench is lower than the lowest point of the first trench.

[0136] It is worth noting that this embodiment also performs P-type protective injection at the bottom of the second trench, such as... Figure 38 As shown. When the diode needs to be turned on, the current flows from the metal electrode in the second trench, through the junction of the sidewall of the second trench and the current diffusion layer, diffuses into the current diffusion layer, and then diffuses sequentially into the epitaxial layer and the substrate, finally reaching the drain.

[0137] The simulation results obtained by simulating the device structure of Example 5 are described in detail below.

[0138] The forward conduction characteristics of the device were simulated under the following conditions: the gate-drain voltage was fixed at 20V, and the drain-source voltage was scanned from 0V to 2V.

[0139] When the drain-source voltage is 2V, the current density distribution along the C-C' cross section is as follows: Figure 42 As shown, from Figure 42 It can be seen that electrons are injected downward into the drift region through the FIN structure, and the entire FIN becomes an effective conductive channel.

[0140] The corresponding positive IV characteristic curve is as follows Figure 43 As shown, from Figure 43 As can be seen from the curve, the device has excellent conduction characteristics, with a specific on-resistance of approximately 2 mΩ·cm. 2 .

[0141] The conduction characteristics of the body diode were evaluated. To prevent channel conduction, the gate-source voltage was set to -5V, and the drain-source voltage was scanned in reverse from 0V to -3.5V.

[0142] Current density distribution along section B-B' is as follows Figure 44 As shown, the current density distribution along the D-D' section is as follows: Figure 45 As shown in the simulation results, the current does not flow through the parasitic anti-parallel PN junction diode, but rather through the low-barrier diode integrated on the sidewall.

[0143] Figure 46 The third-quadrant characteristics of the integrated and non-integrated low-barrier diode structures were further compared. It is evident that the diode characteristics in the third quadrant of the device using this embodiment require only approximately 0.6V to turn on, significantly reducing reverse conduction and switching losses. Even when the drain-source voltage reaches -3.5V, the parasitic anti-parallel PN junction diode remains unconducted, effectively suppressing the risk of bipolar degradation.

Claims

1. A fin field-effect transistor with an integrated low-barrier diode, characterized in that, include: A type 1 substrate (1); a type 1 drift region (2) formed on the substrate; a type 2 well layer (3) formed in the drift region; a source region (4) formed in the well layer; a first trench (5) extending downward from the upper surface of the source region and penetrating the well layer; and a protection zone (6) formed on the sidewalls and bottom of the first trench. A gate oxide layer (7) covering the inner surface of the first trench; a gate electrode (8) filling the first trench; a second trench (9) extending downward from the upper surface of the source region to the drift region; a source electrode (10) filling the second trench; the protection zone (6) includes a sidewall protection zone (601) and a bottom protection zone (602), wherein the impurity concentration of the sidewall protection zone is greater than the impurity concentration of the current diffusion layer (202) and less than the impurity concentration of the first source region (401).

2. The fin field-effect transistor with integrated low-barrier diode according to claim 1, characterized in that, The substrate (1) is heavily doped, and the drift region (2) includes a lightly doped first-type epitaxial layer (201) formed on the substrate (1) and a medium-doped first-type current diffusion layer (202) located on the epitaxial layer.

3. A fin field-effect transistor with an integrated low-barrier diode according to claim 1 or 2, characterized in that, The source region includes a first source region (401) of the first type and a second source region (402) of the second type. The first source region (401) and the second source region (402) together cover the entire upper surface of the well region. The depth of the first source region does not exceed the well layer.

4. A fin field-effect transistor with integrated low-barrier diode according to claim 1, characterized in that, The spacing between two adjacent first trenches in the first direction is 50 nm to 100 nm.

5. A fin field-effect transistor with an integrated low-barrier diode according to claim 3, characterized in that, The first trench (5) extends from the upper surface of the first source region (401) to the current diffusion layer (202) or through the current diffusion layer, and the first trench does not contact the second source region (402).

6. A fin field-effect transistor with an integrated low-barrier diode according to claim 1, characterized in that, The second groove (9) has a stepped shape when it contacts the drift area (2).

7. A fin field-effect transistor with an integrated low-barrier diode according to claim 2, characterized in that, The second trench (9) extends to the current diffusion layer (202).

8. A fin field-effect transistor with an integrated low-barrier diode according to claim 1 or 2, characterized in that, The first type has an N-type conductivity and the second type has a P-type conductivity; or the first type has a P-type conductivity and the second type has an N-type conductivity.

9. A method for manufacturing a fin field-effect transistor with an integrated low-barrier diode, realizing the fin field-effect transistor with an integrated low-barrier diode as described in any one of claims 1 to 8, characterized in that, Includes the following steps: S1 forms the first type substrate and the first type drift region; S2, forming a second type of trap layer; S3 forms the first type of first source region; S4 forms the second type of second source region; S5, forming the first trench; S6 forms a second type of sidewall protection zone; S7 forms a second type of bottom protection zone connected to the sidewall protection zone; S8, a gate oxide layer and a gate electrode are formed in the first trench; S9 forms the second trench; S10 forms the source electrode within the second trench.

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