Half-bridge circuit

Abstract

The invention relates to a half-bridge circuit (1) comprising at least two high-voltage-side transistors (T1, T2) and at least two low-voltage-side transistors (T3, T4), which are connected in each case in parallel, the transistors (T1-T4) being arranged on a common substrate (3) with metallization, the at least two high-voltage-side transistors (T1, T2) and the at least two low-voltage-side transistors (T3, T4) being arranged on a common substrate (3) with metallization. The high-voltage-side transistors (T1, T2) and the low-voltage-side transistors (T3, T4) are arranged in each case in a mirror-symmetrical manner with respect to each other or in a manner rotated by 180 DEG with respect to each other, the contact pads (4-7) for the positive voltage connection (DC +), the negative voltage connection (DC-) and the phase connection are in each case in a mirror-symmetrical manner, at least one additional substrate (8, 9) is applied between the high-voltage-side transistors (T1, T2) and between the low-voltage-side transistors (T3, T4) to the metallization of the substrate (3), and the high-voltage-side transistors (T1, T2) and the low-voltage-side transistors (T3, T4) are arranged in each case in a mirror-symmetrical manner. Wherein a common gate interface for the high-voltage-side transistors (T1, T2) and a common gate interface for the low-voltage-side transistors (T3, T4) are on the at least one additional substrate (8, 9).

Description

Technical Field

[0001] The invention relates to a half-bridge circuit having at least two high-voltage side transistors and at least two low-voltage side transistors respectively connected in parallel. Background Art

[0002] Half-bridge circuits are frequently used in various circuits, such as pulse-controlled inverters or DC / DC converters. They can also switch very high voltages and currents. The power semiconductors of the half-bridge, such as IGBTs or MOSFETs, are structural components arranged, for example, on a common substrate. MOSFETs are particularly well-known in various technologies, for example as Si or SiC transistors. In particular, the achievable chip area and, therefore, the current carrying capacity of SiC transistors have been limited. To address this problem, it is known to connect two or more MOSFETs in parallel.

[0003] DE 10 2022 204 400 A1 discloses an inverter with at least one half-bridge, wherein the half-bridge has at least one high-side transistor and a low-side transistor. In a preferred embodiment, the half-bridges each have four high-side transistors and four low-side transistors, wherein the four high-side transistors and the four low-side transistors are each connected in parallel. The high-side transistors and the low-side transistors are arranged in two columns, with the metallization of the DC voltage connection and the metallization of the AC voltage connection being designed such that a central feed point for all high-side transistors and a central feed point for all low-side transistors are provided. This ensures that the current is distributed as evenly as possible across the transistors.

[0004] Another possibility for evenly distributing the current across the transistors is individual gate control, which is technically very complex, however, since more complex gate drivers must be used and the number of control pins increases.

[0005] Another possibility is to sort the power semiconductors and connect them in parallel with switching characteristics that are as similar as possible. Summary of the Invention

[0006] The technical problem of the present invention is to create a half-bridge circuit with at least two high-side transistors and at least two low-side transistors, which are each connected in parallel and have a uniform current distribution without individual gate control, wherein thermal problems are reduced.

[0007] The solution to this technical problem is provided by the half-bridge circuit according to the present invention. Further advantageous embodiments of the present invention are provided by the present invention.

[0008] The half-bridge circuit includes at least two high-side transistors and at least two low-side transistors connected in parallel. The number of high-side transistors is equal to the number of low-side transistors and is an even number. Preferably, the number of high-side transistors is 2 or 4.

[0009] The transistors are arranged on a common substrate with a metallization. The high-side transistors and the low-side transistors are arranged mirror-symmetrically to each other, or rotated 180° relative to each other. In addition, the contact pieces for the positive voltage interface, the negative voltage interface, and the phase interface are constructed mirror-symmetrically. At least one additional substrate is applied to the metallization of the substrate between the high-side transistors and between the low-voltage side transistors. In addition, at least a common gate interface for the high-side transistor and a common gate interface for the low-voltage side transistor are arranged on the at least one additional substrate. In the mirror-symmetrical arrangement, the mirror axis of the high-side transistor is the same as the mirror axis of the low-voltage side transistor and the contact piece. As a result, not only the power path but also the signal path is symmetrical. By using the additional substrate, the metallization structure of the substrate does not need to be strongly structured (for example, by etching), so that the resistance is lower and the thermal performance is improved because the heat can be better distributed. This can be achieved because the signal path is transferred to one or more additional substrates. The transistor is preferably a MOSFET, and further preferably a SiC or GaN transistor. Preferably, the high-side transistor and the low-side transistor are selected before assembly, that is, transistors with similar characteristics (e.g., similar gate threshold voltages) are selected. If there is only one gate connection in the signal path, it can be arranged in the center of the transistor, so that the same transistor can be used regardless of whether it is arranged on the left or right side of the additional substrate.

[0010] In one embodiment, two additional substrates are provided, one of which has a gate connection for the high-side transistor and the other has a gate connection for the low-side transistor. The use of two additional substrates has the advantage of ensuring electrical isolation of the substrate metallization between the high-side transistor and the low-side transistor.

[0011] In another embodiment, a common Kelvin source contact for the high-side transistor and the low-side transistor is arranged on an additional substrate or two additional substrates. The additional Kelvin source contact now provides two interfaces in the signal path. In a mirror-symmetrical arrangement, this results in the transistor on the left side of the additional substrate being designed differently from the transistor on the right side. As a result, the signal path remains completely symmetrical. In contrast, using identical transistors rotated 180° can result in slight asymmetries.

[0012] In another embodiment, a gate terminal is arranged on the transistor, and two Kelvin source terminals are arranged symmetrically around the gate terminal. Alternatively, a Kelvin source contact is arranged on the transistor, and two gate terminals are arranged symmetrically around the Kelvin source contact. Preferably, the two Kelvin source terminals or the two gate terminals are internally interconnected. This allows the use of transistors of the same type on both sides of the at least one additional substrate, with completely symmetrical signal paths.

[0013] In another embodiment, interfaces for measuring the temperature of at least one high-side transistor and a low-side transistor are arranged on one or more additional substrates. These interfaces do not need to be symmetrical, as they have no influence on the signal path.

[0014] In another embodiment, the additional substrate or the additional substrates are configured as DBC (direct bonded copper) or AMB (active metal brazing) substrates.

[0015] In a further embodiment, the additional substrate or the additional substrates are connected to one another via an adhesive bonding, soldering or sintering connection with the metallization of the substrate.

[0016] In another embodiment, two separate contact strips are provided for the positive voltage connection. Alternatively, it can also be provided that two separate contact strips are provided for the negative voltage connection.

[0017] Furthermore, the interfaces of the additional substrate or substrates are configured as control pins oriented perpendicularly to the top side of the additional substrate or substrates, for example, as press-fit contacts.

[0018] In another embodiment, the interfaces of the additional substrate or substrates are connected to the high-side transistor and the low-side transistor by means of bonding wires.

[0019] In another embodiment, the high-side transistor and the low-side transistor are configured as bare chips.

[0020] Furthermore, preferably, a plurality of half-bridge circuits are arranged on a common heat sink.

[0021] Furthermore, the half-bridge circuit is preferably encapsulated by means of a molding compound. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The present invention will be explained in more detail below according to preferred embodiments, wherein:

[0023] Figure 1 shows a perspective view of a half-bridge circuit in a housing,

[0024] Figure 2 shows a top view of a half-bridge circuit without a housing,

[0025] Figure 3 shows a perspective view of a half-bridge circuit without housing,

[0026] Figure 4 shows a perspective view of a half-bridge circuit without contact strips,

[0027] Figure 5 shows a perspective view of the additional base plate without control pins,

[0028] Figure 6 shows a schematic diagram of a transistor pair with a gate interface and a Kelvin source interface and a mirror-symmetrical arrangement,

[0029] Figure 7 shows a schematic diagram of a transistor pair with a gate connection and a Kelvin source connection, wherein the transistors are arranged rotated 180° relative to each other, and

[0030] Figure 8 Shown is a schematic diagram of a transistor pair with a gate interface and two Kelvin source interfaces. DETAILED DESCRIPTION

[0031] exist Figure 1 The half-bridge circuit 1 is presented with a housing 2, and Figure 2 The figure is shown without housing 2. A half-bridge circuit 1 includes a first high-side transistor T1 and a second high-side transistor T2 connected in parallel. Furthermore, the half-bridge circuit 1 includes a first low-side transistor T3 and a second low-side transistor T4, also connected in parallel. Transistors T1-T4 are arranged on a common substrate 3 with structured metallization. Furthermore, two contact lugs 4 and 5 are provided for the positive voltage terminal DC+, a contact lug 6 for the negative voltage terminal DC-, and a contact lug 7 for the phase terminal. Contact lug 4 is connected to the drain terminal of the first high-side transistor T1 via the metallization. Correspondingly, contact lug 5 is connected to the second high-side transistor T2 via the metallization, with the two drain terminals of transistors T1 and T2 being connected via the metallization. The negative voltage terminal DC- is connected to the source terminals of the two low-side transistors T3 and T4 via contact lug 6. Contact lug 7 contacts the source terminals of the two high-side transistors T1 and T2 and the drain terminals of the two low-side transistors T3 and T4. Contact clips 4-7 are preferably designed as leadframes. Furthermore, a first additional substrate 8 and a second additional substrate 9 are arranged on the metallization of substrate 3. The first additional substrate 8 is associated with high-side transistors T1, T2, and the second additional substrate 9 is associated with low-side transistors T3, T4. A structured metallization is applied to the tops of both additional substrates 8 and 9. Five control pins 10 are arranged on each of the two additional substrates 8, 9, perpendicular to the surfaces of the additional substrates 8, 9.

[0032] Now follow Figure 5 The function of the control pin 10 is explained in more detail, wherein the additional substrate 9 for the low-side transistors T3, T4 is shown without the control pin 10, but with the bonding wire 11. In this case, five mutually separated metallizations 12.1-12.5 are applied to the additional substrate 9. In this case, the control pins 10 are arranged symmetrically on the metallization 12.3 (see also Figure 2 ), which serves as a common gate interface for the two low-voltage side transistors T3 and T4. A control pin 10 is symmetrically arranged on the metallization 12.4, which serves as a common Kelvin source interface for the two low-voltage side transistors T3 and T4. Therefore, the bonding wires 11, which are also symmetrically arranged, are led out on both sides. Here, the two control pins 10 can also be interchanged. The bonding wires 11 of the metallizations 12.2 and 12.5 are connected to the cathode or anode of the pn junction of the second low-voltage side transistor T4 and are used for temperature measurement. The metallization 12.1 is connected to the two drain interfaces of the two low-voltage side transistors T3 and T4 via the metallization of the substrate 3 via the bonding wires 11. The corresponding content applies to the first additional substrate 8.

[0033] This ensures that both the power path and the signal path of the half-bridge circuit 1 are completely symmetrical, which should be in accordance with Figure 2 To explain in more detail, a mirror axis A is drawn in. All contact pads 4-7 are arranged in mirror symmetry. The two high-side transistors T1, T2, like the two low-side transistors T3, T4, are also arranged in mirror symmetry with respect to the mirror axis A. The two common gate terminals and the two common Kelvin source terminals are also arranged symmetrically with respect to the associated transistors T1, T2 or T3, T4 and lie on the mirror axis A. On the other hand, the control pin 10 for measuring the temperature and the drain voltage of the low-side transistors T3, T4 or the source voltage of the high-side transistors T1, T2 has no influence on the control path.

[0034] exist Figure 3 The half-bridge circuit 1 is shown in a perspective view in FIG. 1 , in order to better illustrate the individual bends of the contact strips 4 - 7 .

[0035] exist Figure 4 In FIG. 1 , the half-bridge circuit 1 is presented without the contact pads 4 - 7 , wherein the contact surfaces 13 on the substrate 3 or the transistors T1 - T4 for the contact pads 4 - 7 are presented.

[0036] exist Figure 6The figure schematically illustrates a mirror-symmetrical arrangement, which will be explained for the high-side transistors T1 and T2. An additional substrate 8 is arranged between the two high-side transistors T1 and T2. A mirror axis A extends through the additional substrate 8. The two high-side transistors T1 and T2 each have a gate terminal G and a Kelvin source terminal S. A common gate terminal G and a common Kelvin source terminal S are located on the additional substrate 8, with electrical connections being made via bonding wires 11. While the structures of the two transistors T1 and T2 differ, the signal paths are completely symmetrical.

[0037] exist Figure 7 1 shows the situation when transistors T1, T2 are structurally identical and rotated by 180°, with the axis of rotation running centrally through the additional substrate 8 (eg, normal vector). In this case, the signal paths are not completely symmetrical.

[0038] The solution to this problem is Figure 8 , where the two transistors T1 and T2 have identical structures. This results in a mirror-image arrangement and complete symmetry with respect to the signal paths. Similarly, it is possible to provide a central Kelvin source terminal, around which two gate terminals are symmetrically arranged on transistors T1 and T2.

[0039] Reference Number List

[0040] 1 Half-bridge circuit

[0041] 2 Shell

[0042] 3 substrate

[0043] 4-7 contact piece

[0044] 8 substrate

[0045] 9 substrate

[0046] 10 Control pins

[0047] 11 Bonding wires

[0048] 12.1-12.5 Metallization

[0049] 13 contact surface

[0050] A Mirror axis

[0051] T1 first high-side transistor

[0052] T2 Second high-side transistor

[0053] T3 first low-side transistor

[0054] T4 Second low-side transistor

Claims

1. A half-bridge circuit (1), comprising at least two high-side transistors (T1, T2) and at least two low-side transistors (T3, T4) connected in parallel, wherein: The transistors (T1-T4) are arranged on a common substrate (3) with a metallization, wherein the at least two high-side transistors (T1, T2) and the at least two low-side transistors (T3, T4) are arranged mirror-symmetrically to one another or rotated 180° relative to one another, wherein the contact strips (4-7) for the positive voltage connection (DC+), the negative voltage connection (DC-) and the phase connection are each constructed mirror-symmetrically, wherein at least one additional substrate (8, 9) is applied to the metallization of the substrate (3) between the high-side transistors (T1, T2) and between the low-side transistors (T3, T4), wherein a common gate connection for the high-side transistors (T1, T2) and a common gate connection for the low-side transistors (T3, T4) are on the at least one additional substrate (8, 9).

2. The half-bridge circuit according to claim 1, characterized in that Two additional substrates (8, 9) are provided, wherein the additional substrate (8) has a gate connection for the high-side transistors (T1, T2) and the other additional substrate (9) has a gate connection for the low-side transistors (T3, T4).

3. A half-bridge circuit according to any one of the preceding claims, characterized in that A common Kelvin source contact for the high-side transistors (T1, T2) and a common Kelvin source contact for the low-side transistors (T3, T4) are arranged on one or more additional substrates (8, 9).

4. A half-bridge circuit according to any one of the preceding claims, characterized in that A gate interface (G) is arranged on the transistor (T1-T4), and two Kelvin source interfaces (S1, S2) are arranged symmetrically around the gate interface, or a Kelvin source interface is arranged on the transistor (T1-T4), and two gate interfaces are arranged symmetrically around the Kelvin source interface.

5. A half-bridge circuit according to any one of the preceding claims, characterized in that An interface for measuring the temperature of at least one high-side transistor (T1) and a low-side transistor (T4) is arranged on one or more additional substrates (8, 9).

6. A half-bridge circuit according to any one of the preceding claims, characterized in that The additional substrate or the additional substrates (8, 9) are configured as DBC or AMB substrates.

7. A half-bridge circuit according to any one of the preceding claims, characterized in that The additional substrate or the additional substrates (8, 9) are connected to the metallized portion of the substrate (3) by bonding, soldering or sintering.

8. A half-bridge circuit according to any one of the preceding claims, characterized in that Two separate contact strips (4, 5) are provided for the positive voltage connection (DC+).

9. A half-bridge circuit according to any one of the preceding claims, characterized in that The interface of the additional substrate or the additional substrates (8, 9) is designed as a control pin (10), which is oriented perpendicularly to the upper side of the other substrate or substrates (8, 9).

10. A half-bridge circuit according to any one of the preceding claims, characterized in that The interfaces of the additional substrate or the additional substrates (8, 9) are connected to the high-voltage side transistors (T1, T2) and the low-voltage side transistors (T3, T4) by means of bonding wires (11).

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