Light-emitting chip

Abstract

The invention relates to the technical field of light-emitting diodes, in particular to a light-emitting chip. The light-emitting chip comprises a light-emitting area, and the light-emitting area comprises a first semiconductor layer, an active layer and a second semiconductor layer which are stacked in sequence; the first bonding pad is electrically connected with the first semiconductor layer; the second bonding pad is electrically connected with the second semiconductor layer; wherein the light-emitting area is provided with a first hole area and a second hole area, the first hole area comprises a plurality of first through holes exposing the first semiconductor layer, and the second hole area comprises a plurality of second through holes exposing the first semiconductor layer; the first hole area is closer to the second bonding pad than the second hole area, the maximum distance between the adjacent first through holes is larger than that between the adjacent second through holes, and the number of the first through holes is smaller than that of the second through holes. According to the light-emitting chip, the total area of the first bonding pad and the second bonding pad is increased, and the heat dissipation area of the chip is increased.

Description

Technical Field

[0001] The present invention relates to the technical field of light-emitting diodes, and in particular to a light-emitting chip. Background Art

[0002] As a light source, LEDs are energy-efficient and can provide bright, clear illumination while consuming minimal power and requiring less battery life. This makes them a significant advantage and is now widely used in outdoor lighting, emergency preparedness, and everyday use. Advances in LED technology have led to significant innovations in the flashlight market in recent years, producing flashlights that are longer-lasting and brighter than ever before while using less energy.

[0003] LED flashlight packages often incorporate a lens package. This lens provides the LED with a certain degree of directional illumination, but it also complicates the design of the secondary optics (the flashlight's light-scattering components). Refraction can cause color cast, dispersion, and unevenness in the light spot, making it difficult to maintain a consistent light pattern. Furthermore, the uniform distribution of small holes exposing the N-GaN layer in the light-emitting area of ​​existing LEDs reduces the P-PAD area, resulting in low PAD thrust and poor light extraction efficiency.

[0004] In view of this, the present invention is proposed. Summary of the Invention

[0005] An object of the present invention is to provide a light emitting chip to solve the above technical problems. The light emitting chip of the present invention can improve light extraction efficiency.

[0006] In order to achieve the above-mentioned purpose of the present invention, the following technical solutions are adopted:

[0007] A light-emitting chip, comprising:

[0008] substrate;

[0009] a light-emitting region located on the substrate, the light-emitting region comprising a first semiconductor layer, an active layer, and a second semiconductor layer stacked in sequence;

[0010] a first pad electrically connected to the first semiconductor layer;

[0011] a second pad electrically connected to the second semiconductor layer;

[0012] In which, the light-emitting area is provided with a first hole area and a second hole area, the non-edge area of ​​the first hole area includes a plurality of first through holes exposing the first semiconductor layer, and the non-edge area of ​​the second hole area includes a plurality of second through holes exposing the first semiconductor layer; the first hole area is closer to the second pad than the second hole area, the maximum spacing between adjacent first through holes is greater than the maximum spacing between adjacent second through holes, and the number of first through holes is less than the number of second through holes.

[0013] In some embodiments, the isolation median line between the first pad and the second pad is defined as isolation median line L1, the direction of the straight line where the isolation median line L1 is located is defined as the first direction, the direction different from the isolation median line L1 is the second direction, the pitch in the first direction between adjacent first through-holes is D3, the pitch in the second direction is D6, the pitch in the first direction between adjacent second through-holes is D4, the pitch in the second direction is D5, D4 < D3, D6 < D5, and D4, D3, D5, and D6 are all less than 500 μm.

[0014] In some embodiments, the radius R1 of the first through-hole and the radius R2 of the second through-hole satisfy: 1 / 2·R1 ≤ R2 ≤ R1.

[0015] In some embodiments, the area of the first hole region is less than or equal to the area of the second hole region.

[0016] In some embodiments, the substrate is rectangular, the substrate includes a first side, a third side, a second side, and a fourth side connected in sequence, the first side and the second side are parallel to the isolation median line L1, the distance E1 from the first side to the isolation median line L1, the distance E2 from the first side to the second side, and E1 and E2 satisfy the relationship: 1 / 5·E2 ≤ E1 ≤ 1 / 2·E2.

[0017] In some embodiments, the outer contour of the projection of the light-emitting region on the substrate surface is circular or rectangular, and the difference between the side length D1 of the substrate and the diameter D2 of the outer contour of the projection of the light-emitting region is greater than or equal to 15 μm.

[0018] In some embodiments, when the shortest distance H from the first through-hole to the circumcircle of the light-emitting region is greater than 1 / 20·D1, at least one notch is provided at the edge of the light-emitting region, the shortest distance D7 between the inner side of the notch and the first through-hole, D6 ≤ D7, D7 < 500 μm, 1 / 6·D1 ≤ D7 ≤ 1 / 3·D1.

[0019] In some embodiments, the substrate includes a first region and a second region, the light-emitting region is located on the first region, and a first insulating layer and a metal reflective layer located on the first insulating layer are provided on the light-emitting region and the second region.

[0020] In some embodiments, the metal reflective layer is electrically connected to the second semiconductor layer through the through-hole of the first insulating layer, and the first through-hole and the second through-hole are exposed;

[0021] In some embodiments, the metal reflective layer includes a first reflective layer and a second reflective layer, the first reflective layer is located on the upper surface of the light-emitting area and is electrically connected to the second semiconductor layer through a through hole in the first insulating layer, and the second reflective layer is located on the second area and is not electrically connected to the first reflective layer.

[0022] In some embodiments, the light-emitting chip further includes a transparent conductive layer, the transparent conductive layer being located on the upper surface of the light-emitting area, the transparent conductive layer being provided with a fifth through hole exposing the second semiconductor layer, and the metal reflective layer forming an ohmic connection with the second semiconductor layer through the fifth through hole.

[0023] In some embodiments, the second reflective layer includes four independent reflective regions located at four corner regions of the substrate, and the distance between any of the reflective regions and the light emitting region is greater than 10 μm.

[0024] In some embodiments, a second insulating layer, a first electrode layer, a second electrode layer, and a third insulating layer are further disposed between the first insulating layer and the first pad and / or the second pad.

[0025] The second insulating layer covers the metal reflective layer and has a third through hole exposing the first through hole and the second through hole, and a fourth through hole exposing the metal reflective layer.

[0026] The first electrode layer is electrically connected to the first semiconductor layer through the third through hole, and the second electrode layer is electrically connected to the second semiconductor layer through the fourth through hole;

[0027] The third insulating layer covers the surfaces of the second insulating layer, the first electrode and the second electrode, and includes through holes exposing the first electrode layer and the second electrode layer.

[0028] The first pad and the second pad are electrically connected to the first electrode layer and the second electrode layer through the through holes, respectively.

[0029] In some embodiments, an N platform is provided at the edge of the light emitting area, the second insulating layer has an external through hole exposing the N platform, and the first electrode layer is electrically connected to the first semiconductor layer through the third through hole and the external through hole.

[0030] In some embodiments, the area S2 of the first electrode layer and the area S1 of the second electrode layer satisfy: 1≤S2 / S1≤8. Preferably, 1≤S2 / S1≤4.

[0031] In some embodiments, at least one opening region is further provided in the first electrode layer. The width of each opening region is F5, the extension length is F4, the maximum distance in the first direction of the substrate is F2, and the distance between the projections of the two sides of the first electrode layer perpendicular to the straight line where the second side is located on the substrate is F1. Then, F1, F2, F4, and F5 satisfy: 1 / 5·F1 ≤ F4 ≤ F1, 10 μm < F5 < F2; preferably, 1 / 2·F1 < F4 < 4 / 5·F1, 10 μm < F5 < 1 / 3·F2. A thimble region is provided in the opening region, and a metal layer is provided in the thimble region.

[0032] In some embodiments, at least one opening region is further provided in the first electrode layer. The opening region includes: one or more second-direction opening regions, a cross-shaped opening region, or an inverted V-shaped opening region.

[0033] In some embodiments, the area S3 of the first pad is smaller than the area S4 of the second pad.

[0034] In some embodiments, the number of the first pads is one or more, and for any of the first pads, the area S5 > S3.

[0035] In some embodiments, isolation grooves are provided in the non-light-emitting region of the light-emitting chip. The isolation grooves are linear near the first side and the second side of the substrate and are arc-shaped near the four corners of the substrate. The minimum distance A1 between the isolation grooves and the scribe satisfies: 4 μm < A1 ≤ 15 μm; the nearest distance A2 between the ISO isolation grooves and the projection of the top surface of the light-emitting region on the substrate is < 9 μm.

[0036] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0037] For the light-emitting chip of the present invention, the arrangement manners of the first through holes and the second through holes in the light-emitting region are different, and the first through holes are closer to the second pad than the second through holes, which can ensure that the first pad and the second pad have as large a total area as possible within a limited chip size and improve the light extraction efficiency; by arranging the light-emitting region in a circular shape, the influence of light at the four corners of the square is solved, and a circular light shape of the LED is realized; the excessive metal stress can be solved, and the stress of the pads can be released; through the irregular area design, the current distribution is made uniform; through the non-conductive metal reflection layer, light reflection is realized, and the surrounding scattered light is reduced. Description of the Drawings

[0038] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0039] Figure 1 is a cross-sectional view of the light-emitting area;

[0040] Figure 2 A top view of the light-emitting area;

[0041] Figure 3 A cross-sectional view of a first insulating layer provided on the light emitting area;

[0042] Figure 4 A top view of a first insulating layer provided on the light emitting area;

[0043] Figure 5 A cross-sectional view showing the arrangement of a metal reflective layer;

[0044] Figure 6 Another cross-sectional view showing the arrangement of a metal reflective layer;

[0045] Figure 7 A top view of the metal reflective layer is provided;

[0046] Figure 8 A cross-sectional view showing the second insulating layer;

[0047] Figure 9 A top view of setting a second insulating layer;

[0048] Figure 10 A cross-sectional view showing the arrangement of a first electrode layer and a second electrode layer;

[0049] Figure 11 A top view of the first electrode layer and the second electrode layer;

[0050] Figure 12 is a cross-sectional view of a light-emitting chip;

[0051] Figure 13 is a top view of the light-emitting chip;

[0052] Figure 14 Schematic diagram of the spacing markings between the first through hole and the second through hole in the asymmetric light-emitting chip;

[0053] Figure 15 is a schematic diagram of the size markings of the opening area of ​​the first electrode layer;

[0054] Figure 16are different topography images of the opening area of ​​the first electrode layer;

[0055] Figure 17 is a schematic diagram of different structures of the first pad;

[0056] Figure 18 This is a schematic diagram of the light-emitting chip structure of Example 4;

[0057] Figure 19 This is a schematic diagram of the light-emitting chip structure of Example 5;

[0058] Figure 20 1 is a light distribution diagram of the light emitting chip in Example 1 and Comparative Example 1 of the present invention;

[0059] Figure 21 Schematic diagram of through-hole distribution of the light-emitting chip of comparative example 1 of the present invention.

[0060] Reference numerals:

[0061] 1-substrate, 110-first region, 120-second region, 2-light-emitting region, 201-first semiconductor layer, 202-active layer, 203-second semiconductor layer, 205-first through hole, 206-second through hole, 3-N platform, 4-isolation region, 5-first insulating layer, 501-sixth through hole, 502-seventh through hole, 6-metal reflective layer, 610-first reflective layer, 620-second reflective layer, 7-second insulating layer, 701-fourth through hole, 702-eighth through hole, 703-third through hole, 8-second electrode layer, 9-first electrode layer, 10-opening region, 11-top pin region, 12-first pad, 13-second pad, 14-transparent conductive layer, 15-third insulating layer. DETAILED DESCRIPTION

[0062] The embodiments of the present invention will be described in detail below with reference to the examples, but it will be understood by those skilled in the art that the following examples are merely illustrative of the present invention and should not be construed as limiting the scope of the invention. Where specific conditions are not specified in the examples, the methods were performed according to conventional conditions or the conditions recommended by the manufacturer. Where the manufacturers of the reagents or instruments are not specified, they are all commercially available conventional products.

[0063] A light-emitting chip, comprising:

[0064] substrate;

[0065] a light-emitting region located on the substrate, the light-emitting region comprising a first semiconductor layer, an active layer, and a second semiconductor layer stacked in sequence;

[0066] a first pad electrically connected to the first semiconductor layer;

[0067] The second pad is electrically connected to the second semiconductor layer;

[0068] Among them, the light-emitting region is provided with a first hole region and a second hole region. The non-edge region of the first hole region includes a plurality of first through holes exposing the first semiconductor layer, and the non-edge region of the second hole region includes a plurality of second through holes exposing the first semiconductor layer; the first hole region is closer to the second pad than the second hole region. The maximum distance between adjacent first through holes is greater than the maximum distance between adjacent second through holes, and the number of first through holes is less than the number of second through holes.

[0069] For the light-emitting chip of the present invention, the arrangement of the first through holes and the second through holes in the light-emitting region is different, and the first through holes are closer to the second pad than the second through holes, which can ensure that the first pad and the second pad have as large a total area as possible within the limited chip size and improve the light extraction efficiency. [[ID=⑧]]

[0070] In some embodiments, let the isolation center line between the first pad and the second pad be the isolation center line L1, let the direction of the straight line where the isolation center line L1 is located be the first direction, and the direction different from the isolation center line L1 be the second direction. The first-direction distance between adjacent first through holes is D3, and the second-direction distance is D6. The first-direction distance between adjacent second through holes is D4, and the second-direction distance is D5. D4 < D3, D6 < D5, and D4, D3, D5, and D6 are all less than 500 μm; for example, 100 μm, 200 μm, 300 μm, 400 μm, 480 μm, etc. In some embodiments, the radius R1 of the first through hole and the radius R2 of the second through hole satisfy: 1 / 2·R1 ≤ R2 ≤ R1. By setting the appropriate distances and sizes of the first through holes and the second through holes, the through holes have an appropriate number and a relatively large single area, which can avoid congestion of diffusion points and improve the light-emitting performance of the diode.

[0071] [[ID=I2]]In some embodiments, the isolation center line L1 coincides with the center line L2 of the light-emitting chip and is defined as a symmetric pad. If they do not coincide, it is defined as an asymmetric pad.

[0072] In some embodiments, the first semiconductor layer is an N-GAN layer, and the second semiconductor layer is a P-GAN layer.

[0073] In some embodiments, the first through holes can adopt a variety of different distribution methods. For example, a combined arrangement method of linear arrangement and cross arrangement can be adopted to achieve the largest area of the P-side pad. For symmetric pads, a cross arrangement method is adopted. For asymmetric pads, the N holes on the P side are arranged linearly in the vertical direction and crosswise in the horizontal direction.

[0074] In some embodiments, the substrate is rectangular, and includes a first side, a third side, a second side, and a fourth side connected in sequence. The first side and the second side are parallel to the isolation center line L1. The distance from the first side to the isolation center line L1 is E1, and the distance from the first side to the second side is E2. E1 and E2 satisfy the relationship: 1 / 5·E2≤E1≤1 / 2·E2.

[0075] In some embodiments, the substrate is sapphire.

[0076] In some embodiments, the outer contour of the projection of the light-emitting area on the substrate surface is circular or rectangular, preferably circular, and the difference between the side length D1 of the substrate and the diameter D2 of the outer contour of the projection of the light-emitting area is greater than or equal to 15μm, for example 15μm, 20μm, 25μm, etc.

[0077] In some embodiments, when the shortest distance H from the first through hole to the circumscribed circle of the light-emitting area is greater than 1 / 20·D1, an incision is set at the light-emitting area, and the shortest distance between the inner side of the incision and the first through hole is D7, D6≤D7, D7<500μm, 1 / 6·D1≤D7≤1 / 3·D1. The reason for setting this is to minimize the transmission distance of the nearby P hole to the N hole.

[0078] In some embodiments, the substrate includes a first region and a second region, the light-emitting region being located on the first region, and a first insulating layer and a metal reflective layer located on the first insulating layer being disposed on the light-emitting region and the second region; the metal reflective layer is electrically connected to the second semiconductor layer via through-holes in the first insulating layer, exposing the first and second through-holes. The first insulating layer may be a single SiO2 layer, a SiO2+DBR layer, an ALD+DBR+SiO2 layer, an ALD+DBR+ALD layer, or a SiO2+ALD layer. ALD (Atomic Layer Deposition) is a high-precision thin-film deposition technology based on chemical vapor deposition. It deposits material onto a surface layer by layer in the form of a single atomic film using chemical vapor deposition. The ALD layer in this embodiment is an insulating layer deposited using ALD technology. The insulating layer material may be a single layer or multiple layers of an oxide or nitride material such as aluminum oxide, silicon oxide, silicon nitride, or titanium oxide.

[0079] In some embodiments, the metal reflective layer includes a first reflective layer and a second reflective layer. The first reflective layer is located on the upper surface of the light-emitting region and is electrically connected to the second semiconductor layer via a through-hole in the first insulating layer. The second reflective layer is located on the second region and is not electrically connected to the first reflective layer. The second reflective layer is non-conductive, and the first and second reflective layers are physically isolated.

[0080] In some embodiments, the second reflective layer includes four independent reflective regions located at the four corners of the substrate. The reflective regions can have any shape, and any reflective region is located at a distance greater than 10 μm from the light-emitting region, such as 12 μm, 15 μm, or 20 μm. The reflective regions can reflect lateral light and reduce scattered light. The metal reflective layer includes at least an Ag reflective layer or an Al reflective layer. When the metal reflective layer includes Ag, since Ag has better adhesion to GaN than oxide, the first insulating layer on the isolation region can also be provided with a through-hole structure. The metal reflective layer is connected to the GaN layer or sapphire substrate through the through-hole, which has better adhesion.

[0081] In some embodiments, the light-emitting chip further includes a transparent conductive layer, the transparent conductive layer being located on an upper surface of the light-emitting region. The transparent conductive layer is provided with a fifth through-hole exposing the second semiconductor layer, and the metal reflective layer forms an ohmic connection with the second semiconductor layer through the fifth through-hole. In some embodiments, the transparent conductive layer is ITO, TCO, or graphene.

[0082] In some embodiments, a second insulating layer, a first electrode layer (N-metal, N-side metal layer), a second electrode layer (P-metal, P-side metal layer), and a third insulating layer are further disposed between the first insulating layer and the first pad and / or the second pad. The second insulating layer covers the metal reflective layer and has a third through-hole exposing the first and second through-holes, and a fourth through-hole exposing the metal reflective layer. The first electrode layer is electrically connected to the first semiconductor layer via the third through-hole, and the second electrode layer is electrically connected to the second semiconductor layer via the fourth through-hole. The third insulating layer covers the surface of the second insulating layer, the first electrode, and the second electrode, and includes through-holes exposing the first and second electrode layers. The first pad and the second pad are electrically connected to the first and second electrode layers, respectively, via through-holes. In some embodiments, the second insulating layer and the third insulating layer can each be a single layer or multiple layers, such as a single layer or a composite layer of SiO2, TiO2, SiN, or aluminum oxide.

[0083] In some embodiments, an N platform is provided at the edge of the light emitting area, the second insulating layer has an external through hole exposing the N platform, and the first electrode layer is electrically connected to the first semiconductor layer through the third through hole and the external through hole.

[0084] In some embodiments, the P-metal region is connected on the P side, and its area is defined as S1; the N-metal region is connected on the N side, and its area is defined as S2. That is, the area S2 of the first electrode layer and the area S1 of the second electrode layer satisfy: 1≤S2 / S1≤8, preferably 1≤S2 / S1≤4.

[0085] In some embodiments, the first electrode layer is further provided with at least one opening region. The width of each opening region is F5, the extension length is F4, the maximum distance in the first direction of the substrate is F2, and the distance between the projections of the two sides of the first electrode layer perpendicular to the straight line where the second side is located on the substrate is F1. Then, F1, F2, F4, and F5 satisfy: 1 / 5·F1 ≤ F4 ≤ F1, 10μm < F5 < F2. Preferably, 1 / 2·F1 < F4 < 4 / 5·F1, 10μm < F5 < 1 / 3·F2. F2 is actually the maximum size of the chip, which can be dozens of micrometers, hundreds of micrometers, or thousands of micrometers. For example, the size of some flip-chip products is between 700μm and 1400μm. For example, F5 = 15μm, F2 = 1000μm. Because the metal connection region is too large, the metal stress will be very large, which will cause the problem of film layer peeling. By setting the above opening region on the first electrode layer and satisfying the above relational formula, the present invention can effectively release stress and improve mechanical properties. In some embodiments, the opening region includes: one or more second-direction opening regions, a cross-shaped opening region, or an inverted八字-shaped opening region. In some embodiments, a thimble region is provided in the opening region, and a metal layer is provided in the thimble region.

[0086] In some embodiments, the area S3 of the first pad is smaller than the area S4 of the second pad. The number of the first pads is one or more, and the first pads are divided into independent regions or are small regions with connected hollowed-out parts, and the area S5 of any first pad > S3.

[0087] In some embodiments, the light-emitting chip can adopt an ISO isolation groove or no ISO isolation groove. An isolation groove is provided in the non-light-emitting region of the light-emitting chip. The ISO isolation groove is an irregular figure, and the figure is approximately circular. The isolation groove is linear near the first side and the second side of the substrate, and is arc-shaped near the four corners of the substrate. This region forms a connection path between the second connection electrode and the N-GAN. The minimum distance A1 between the isolation groove and the scribe satisfies: 4μm < A1 ≤ 15μm. Appropriate dimensions are beneficial to the light-emitting efficiency and the yield. If the dimensions are too large, the light-emitting area will be sacrificed, and if they are too small, the product yield will be affected. The minimum distance A2 between the ISO isolation groove and the projection of the top surface of the light-emitting region on the substrate < 9μm.

[0088] The following will be further explained with specific examples and comparative examples.

[0089] Example 1

[0090] Appendix Figure 1 To Appendix Figure 14 shows a schematic structural diagram of a light-emitting chip during the preparation process. Among them, Figure 1 and Figure 2Shows a schematic structural diagram of forming a single light-emitting region from an epitaxial wafer by etching in the preparation of a light-emitting chip, which includes a substrate 1 and a light-emitting region 2. Among them, the light-emitting region 2 is located on the substrate 1. The light-emitting region 2 includes a first semiconductor layer 201, an active layer 202, and a second semiconductor layer 203 that are sequentially stacked. A partial cross-sectional view of the light-emitting region 2 is as shown in Figure 1 shown, and a top view of the light-emitting region 2 is as shown in Figure 2 shown. The light-emitting region 2 is provided with a first hole region on one side and a second hole region on the other side. The non-edge region of the first hole region includes a plurality of first through holes 205 exposing the first semiconductor layer 201, and the non-edge region of the second hole region includes a plurality of second through holes 206 exposing the first semiconductor layer 201; the first hole region is closer to the second pad 13 than the second hole region. The number of the first through holes 205 is less than the number of the second through holes 206. Define the isolation median line between the first hole region and the second hole region as L1. The pad electrode provided on the first hole region is electrically connected to the second semiconductor layer, and the pad electrode provided on the second hole region is electrically connected to the first semiconductor. The isolation median line L1 is also the isolation median line of the pad electrodes of different conduction types.

[0091] The substrate 1 includes a first region 110 and a second region 120, and the light-emitting region 2 is located on the first region 110; usually, the second region 120 is an isolation region 4 formed by etching the epitaxial layer. There is usually no first semiconductor layer on the isolation region 4, but there can also be a first semiconductor layer with a certain thickness. An outer ring N platform 3 exposing the first semiconductor layer 201 is also provided on the outer ring of the light-emitting region 2, forming a stepped structure with the first semiconductor layer located on the second region 120, increasing the light extraction from the sidewalls of the semiconductor. The sidewall of any semiconductor layer formed by etching has an inclination angle less than 90°.

[0092] The lateral pitch between adjacent first through holes 205 is D3, and the longitudinal pitch is D6. The lateral pitch between adjacent second through holes 206 is D4, and the longitudinal pitch is D5. D4 < D3, D6 < D5, and D4, D3, D5, and D6 are all less than 500 μm; the radius R1 of the first through hole 205 and the radius R2 of the second through hole 206 satisfy: 1 / 2·R1 ≤ R2 ≤ R1.

[0093] The substrate 1 is rectangular, with a first side b1, a third side b3, a second side b2, and a fourth side b4 connected in sequence. The first side b1 and the second side b2 are both parallel to the isolation median line L1, and the third side b3 is parallel to the fourth side b4. The distance E1 from the first side b1 to the isolation median line L1 and the length E2 of the third side satisfy the relationship: 1 / 5·E2 ≤ E1 ≤ 1 / 2·E2. The outer contour of the projection of the light-emitting region 2 on the surface of the substrate 1 is circular, and the difference between the length D1 of the first side of the substrate 1 and the diameter D2 of the outer contour of the projection of the light-emitting region 2 is greater than or equal to 15 μm. When the shortest distance H from the first through-hole 205 at the edge of the light-emitting region 2 to the circumcircle of the light-emitting region 2 is greater than 1 / 20·D1, a cut is provided at the light-emitting region 2. The shortest distance between the inner side of the cut and the first through-hole 205 is D7, D6 ≤ D7, D7 < 500 μm, 1 / 6·D1 ≤ D7 ≤ 1 / 3·D1. A schematic diagram of the pitch marks of the first through-hole and the second through-hole in the light-emitting chip is as Figure 14 shown.

[0094] Due to the presence of the N platform 3, in the top view direction, the top pattern and the bottom pattern of the light-emitting region 2 are not concentric circle structures. The bottom pattern is composed of arcs and straight lines. Further, the part close to the substrate edge is a straight line, and the straight lines are connected by arcs. The distance between the straight line and the closest substrate edge is A1, 4 μm < A1 ≤ 15 μm; the maximum width of the N platform 3 is A2, A2 < 9 μm.

[0095] As Figures 3 to 5 shown, a first insulating layer 5 is provided on the light-emitting region 2 and the second region 120. The first insulating layer covers the light-emitting region 2 and the isolation region 4, and a sixth through-hole 501 exposing the second semiconductor layer is provided. The metal reflection layer 6 is electrically connected to the second semiconductor layer 203 through the through-hole of the first insulating layer 5. At the same time, the first insulating layer 5 and the metal reflection 6 are both provided with through-holes exposing the first through-hole 205, the second through-hole 206, and at least one seventh through-hole 502 exposing the N platform 3. Among them, the shape of the seventh through-hole 502 located on the N platform is similar to the N platform 3 and may include one or more. A cross-sectional view of the first insulating layer 5 provided on the light-emitting region 2 is as Figure 3 shown, and a top view of the first insulating layer 5 provided on the light-emitting region 2 is as Figure 4 shown. The first insulating layer 5 is formed by a single layer or multiple layers of insulating materials, such as a DBR reflection layer. There are 4 seventh through-holes 502, and the external shape is arc-shaped. The four seventh through-holes 502 surround the outside of the light-emitting region 2, and the circumference formed by the through-holes is more than 1 / 2 of the circumference of the shape of the light-emitting region 2, and further more than 3 / 4.

[0096] The metal reflective layer 6 includes a first reflective layer 610 and a second reflective layer 620. The first reflective layer is located on the upper surface of the light-emitting region 2 and is electrically connected to the second semiconductor layer 203 through the sixth through-hole 501 of the first insulating layer. The second reflective layer 620 is located on the isolation region 4 and is not electrically connected to the first reflective layer 610 or the first semiconductor layer. Preferably, the second reflective layer 620 includes four independent reflective regions located at the four corner regions of the substrate 1, and the distance between any reflective region and the light-emitting region 2 is greater than 10 μm. A cross-sectional view of the arrangement of the metal reflective layer 6 is shown in FIG. Figure 5 As shown, the first reflective layer 610 is similar in shape to the light emitting region 2, and its outer contour is a circular shape. The second reflective layer 620 is disposed on the isolation region 4, and the first insulating layer 5 is disposed between the second reflective layer 620 and the isolation region 4. The top view of the metal reflective layer is shown in FIG. Figure 7 As shown, there are four independent second reflective layers 620, and their shapes can be similar to those of the isolation region 4, or can be other shapes. In another possible embodiment, as shown in FIG. Figure 6 The second reflective layer 620 shown may also be directly connected to the substrate 1 through the first insulating layer 5 , or form an ohmic contact with the first semiconductor layer located on the isolation region 4 .

[0097] The light-emitting chip also includes a transparent conductive layer 14 (ITO), which is located on the upper surface of the light-emitting area 2. The transparent conductive layer 14 is provided with a fifth through hole exposing the second semiconductor layer 203. The metal reflective layer 6 forms an ohmic connection with the second semiconductor layer 203 through the fifth through hole.

[0098] The second insulating layer 7 covers the metal reflective layer 6 and the sidewall of the light emitting region 2, and has a third through hole 703 exposing the first through hole 205 and the second through hole 206, a fourth through hole 701 exposing the metal reflective layer, and an eighth through hole 702 exposing the N platform 3. The cross-sectional view of the second insulating layer 7 is shown in FIG. Figure 8 As shown, the top view of the second insulating layer is as shown Figure 9 The second insulating layer 7 is a single-layer or multi-layer insulating layer, such as SiO2.

[0099] The first electrode layer 9 is electrically connected to the first semiconductor layer 201 through the third through hole 703 and the eighth through hole 702, and the second electrode layer 8 is electrically connected to the second semiconductor layer 203 through the fourth through hole 701. The area S2 of the first electrode layer 9 and the area S1 of the second electrode layer 8 satisfy the following relationship: 1≤S2 / S1≤8. Due to the large area of ​​the first electrode layer 9, a longitudinal opening region 10 is provided to reduce stress. The size of the opening region 10 of the first electrode layer 9 is shown in the schematic diagram. Figure 15As shown, each opening area 10 has a width of F5 and an extension length of F4. The maximum lateral distance of the substrate 1 is F2. The distance between the projections of the two sides of the first electrode layer 9 perpendicular to the straight line on which the second side is located on the substrate 1 is F1. Then F1, F2, F4 and F5 satisfy: 1 / 5·F1≤F4≤F1, 10μm<F5<F2; a pin area 11 is provided in the opening area 10, and a metal layer is provided in the pin area 11. The cross-sectional view of the first electrode layer 9 and the second electrode layer 8 is shown in FIG. Figure 10 As shown, the top view of the first electrode layer and the second electrode layer is as shown Figure 11 shown.

[0100] like Figures 12 to 14 As shown, third insulating layer 15 covers the surfaces of second insulating layer 7, first electrode layer 9, and second electrode layer 8, and includes through-holes exposing first electrode layer 9 and second electrode layer 8. The third insulating layer is SiO2. First pad 12 and second pad 13 are electrically connected to first electrode layer 9 and second electrode layer 8, respectively, via through-holes. Area S3 of first pad 12 is larger than area S4 of second pad 13.

[0101] Example 2

[0102] A light-emitting chip, which differs from Example 1 in that:

[0103] The topography of the opening region 10 of the first electrode layer 9 is shown in FIG. Figure 16 As shown in (a), (b), and (c), it can be set to a cross shape extending longitudinally or transversely, more than two openings in the longitudinal or transverse direction, or an inverted eight-shaped opening and other different shapes to release the metal stress of the first electrode layer 9.

[0104] Example 3

[0105] A light-emitting chip, the difference between the first embodiment and the second embodiment is that:

[0106] The number of independent regions of the first pad 12 is 2, 4, or 6. Figure 17 As shown, (d) represents two, (e) represents four, and (f) represents six. They are also used to release stress caused by the large area of ​​the active first bonding pad 12 .

[0107] Example 4

[0108] A light-emitting chip, such as Figure 18 As shown, the substrate 1 is rectangular and the light-emitting area 2 is circular. The preparation process is basically the same as that of Example 1, except that:

[0109] The arrangement of the first through-hole 205 and the second through-hole 206 , the arrangement of the first electrode layer 9 and the second electrode layer 8 , and the arrangement of the first pad 12 and the second pad 13 .

[0110] Among them, the isolation center line L1 of the first pad 12 and the second pad 13 is also the center of the chip, that is, the distance E1 from the first side to the isolation center line L1 and the distance E2 from the first side to the second side are in the relationship of E1=1 / 2·E2; ​​a first pad 12 and a second pad 13 are symmetrically arranged.

[0111] Example 5

[0112] A light-emitting chip, such as Figure 19 As shown, the substrate 1 and the light emitting area 2 on the substrate 1 are both rectangular. Similar to the embodiment 1, the area S3 of the first pad 12 is larger than the area S4 of the second pad 13, wherein S3 is 1.5 to 5 times of S4.

[0113] Comparative Example 1

[0114] An existing conventional light-emitting chip, such as Figure 21 As shown, the projection outer contour of the light-emitting area on the substrate is a square, the areas of the first hole area and the second hole area are equal and arranged regularly, the first through hole radius R1 = the second through hole radius R2, and the horizontal and vertical spacing are equal.

[0115] Test example

[0116] The light emitting chips of the embodiment and the comparative example were tested for light angle, as shown in Table 1. The light distribution diagrams of the light emitting chips in the embodiment 2 and the comparative example 1 are shown in Table 1. Figure 20 shown.

[0117] Table 1 Light angle test

[0118]

[0119] Compared with the conventional diode in Comparative Example 1, the light emitting chip of the present invention has a smaller light angle and can reduce lateral light.

[0120] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A light-emitting chip, characterized in that: Comprising: A substrate; A light-emitting region located on the substrate, the light-emitting region including a first semiconductor layer, an active layer, and a second semiconductor layer stacked in sequence; A first pad electrically connected to the first semiconductor layer; A second pad electrically connected to the second semiconductor layer; Wherein, the light-emitting region is provided with a first hole region and a second hole region. The non-edge region of the first hole region includes a plurality of first through-holes exposing the first semiconductor layer, and the non-edge region of the second hole region includes a plurality of second through-holes exposing the first semiconductor layer; the first hole region is closer to the second pad than the second hole region. The maximum distance between adjacent first through-holes is greater than the maximum distance between adjacent second through-holes, and the number of first through-holes is less than the number of second through-holes.

2. The light-emitting chip according to claim 1, wherein: Comprising at least one of the following features (1) to (3): (1) Let the isolation median line between the first pad and the second pad be isolation median line L1, let the direction of the straight line where the isolation median line L1 is located be the first direction, and the direction different from the isolation median line L1 be the second direction. The first-direction distance between adjacent first through-holes is D3, and the second-direction distance is D6. The first-direction distance between adjacent second through-holes is D4, and the second-direction distance is D5. D4 < D3, D6 < D5, and D4, D3, D5, and D6 are all less than 500 μm; (2) The radius R1 of the first through-hole and the radius R2 of the second through-hole satisfy: 1 / 2·R1 ≤ R2 ≤ R1; (3) The area of the first hole region is less than or equal to the area of the second hole region.

3. The light-emitting chip according to claim 2, characterized in that: The substrate is rectangular, the substrate includes a first side, a third side, a second side, and a fourth side connected in sequence. The first side and the second side are parallel to the isolation median line L1. The distance E1 from the first side to the isolation median line L1, and the distance E2 from the first side to the second side. E1 and E2 satisfy the relationship: 1 / 5·E2 ≤ E1 ≤ 1 / 2·E2; The outer contour of the projection of the light-emitting region on the substrate surface is circular or rectangular. The difference between the side length D1 of the substrate and the diameter D2 of the outer contour of the projection of the light-emitting region is greater than or equal to 15 μm; Preferably, when the shortest distance H from the first through-hole to the circumcircle of the light-emitting region is greater than 1 / 20·D1, at least one notch is provided at the edge of the light-emitting region. The shortest distance between the inner side of the notch and the first through-hole is D7, D6 ≤ D7, D7 < 500 μm, 1 / 6·D1 ≤ D7 ≤ 1 / 3·D1.

4. The light-emitting chip according to claim 3, characterized in that: The substrate includes a first region and a second region. The light-emitting region is located on the first region. A first insulating layer and a metal reflection layer located on the first insulating layer are provided on the light-emitting region and the second region; The metal reflection layer is electrically connected to the second semiconductor layer through a through-hole of the first insulating layer, and exposes the first through-hole and the second through-hole; Preferably, the metal reflection layer includes a first reflection layer and a second reflection layer. The first reflection layer is located on the upper surface of the light-emitting region and is electrically connected to the second semiconductor layer through a through-hole of the first insulating layer. The second reflection layer is located on the second region and is not electrically connected to the first reflection layer; Preferably, the light-emitting chip further includes a transparent conductive layer, the transparent conductive layer is located on the upper surface of the light-emitting area, the transparent conductive layer is provided with a fifth through hole exposing the second semiconductor layer, and the metal reflective layer forms an ohmic connection with the second semiconductor layer through the fifth through hole.

5. The light-emitting chip according to claim 4, characterized in that: The second reflective layer includes four independent reflective regions located in four corner regions of the substrate, and the distance between any of the reflective regions and the light emitting region is greater than 10 μm.

6. The light-emitting chip according to claim 4, characterized in that: A second insulating layer, a first electrode layer, a second electrode layer and a third insulating layer are further provided between the first insulating layer and the first pad and / or the second pad; The second insulating layer covers the metal reflective layer and has a third through hole exposing the first through hole and the second through hole, and a fourth through hole exposing the metal reflective layer; The first electrode layer is electrically connected to the first semiconductor layer through the third through hole, and the second electrode layer is electrically connected to the second semiconductor layer through the fourth through hole; The third insulating layer covers the surfaces of the second insulating layer, the first electrode and the second electrode, and includes through holes exposing the first electrode layer and the second electrode layer; The first pad and the second pad are electrically connected to the first electrode layer and the second electrode layer through the through holes, respectively.

7. The light-emitting chip according to claim 6, characterized in that: An N platform is provided at the edge of the light emitting area, the second insulating layer has an external through hole exposing the N platform, and the first electrode layer is electrically connected to the first semiconductor layer through the third through hole and the external through hole.

8. The light-emitting chip according to claim 6, wherein: Contains at least one of the following features (1) to (3): (1) The area S2 of the first electrode layer and the area S1 of the second electrode layer satisfy: 1≤S2 / S1≤8; preferably, 1≤S2 / S1≤4; (2) The first electrode layer is further provided with at least one opening area, each of the opening areas has a width of F5, an extension length of F4, a maximum distance in the first direction of the substrate of F2, and a spacing between projections of two sides of the first electrode layer perpendicular to the straight line on which the second side is located on the substrate of F1, then F1, F2, F4 and F5 satisfy: 1 / 5·F1≤F4≤F1, 10μm<F5<F2; preferably, 1 / 2·F1<F4<4 / 5·F1, 10μm<F5<1 / 3·F2; a pin area is provided in the opening area, and a metal layer is provided in the pin area; (3) The first electrode layer is further provided with at least one opening area, and the opening area includes: one or more second direction opening areas, cross-shaped opening areas or inverted eight-shaped opening areas.

9. The light-emitting chip according to claim 1, wherein: Contains at least one of the following features (1) to (2): (1) The area S3 of the first pad is smaller than the area S4 of the second pad; (2) The number of the first pads is one or more, and the area S5 of any of the first pads is greater than S3.

10. The light-emitting chip according to claim 4, characterized in that: An isolation groove is provided in the non-light-emitting area of the light-emitting chip. The isolation groove is linear near the first and second sides of the substrate and is arc-shaped near the four corners of the substrate. The minimum distance A1 between the isolation groove and the scribe line satisfies: 4μm < A1 ≤ 15μm; the minimum distance A2 between the ISO isolation groove and the projection of the top surface of the light-emitting area on the substrate is less than 9μm.

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