Baseband IQ signal generation method and device

Abstract

The invention relates to the technical field of automatic testing, and particularly discloses a baseband IQ signal generation method and device, and the method comprises the following steps: S1, a control unit receives IQ baseband data, calls reference voltage and temperature compensation data, and verifies a data format, a transmission rate and a storage sequence; s2, the data processing unit performs FIR filtering, DAC nonlinear correction and amplitude-frequency error compensation on the data through the FPGA, and dynamically adjusts calibration parameters in combination with real-time temperature; s3, a data conversion unit converts a signal through a 16-bit DAC, and a pre-stage driving circuit completes amplitude adjustment and filtering; and S4, sampling an output signal in real time by the acquisition unit, calculating an image rejection ratio, if the image rejection ratio does not reach the standard, triggering closed-loop calibration, and adjusting FPGA parameters until the indexes are met. And through a multi-stage calibration and closed-loop feedback mechanism, the image rejection ratio is improved, and the reliability of a test result is improved.

Description

Technical Field

[0001] The present invention relates to the field of automated testing technology, and in particular to a baseband IQ signal generating method and device. Background Art

[0002] IQ signals (in-phase and quadrature signals) are core signal forms in fields such as communications and radar, and their accuracy directly affects system performance. In integrated circuit testing, the image rejection ratio (IQImage) of analog IQ baseband signals is a key metric. Traditional analog IQ baseband signal generators commonly suffer from the following drawbacks: First, the image rejection ratio is insufficient. Existing equipment typically only achieves a -50dB image rejection ratio, which is difficult to meet the high-precision signal requirements below -48dB for modern communication chip testing. This is especially true when the chip baseband interface requires a -38dB performance rating, as traditional solutions lack sufficient margin. For example, in hybrid circuit testing of communication chips, insufficient image rejection can easily lead to interference in test results, resulting in misjudgments of chip performance.

[0003] Second, poor stability. Affected by ambient temperature, device temperature drift, and analog circuit construction errors, signals fluctuate significantly across different bandwidths (such as 10MHz and 20MHz) and environmental conditions, resulting in low test reliability. For example, in environments with significant temperature fluctuations, the amplitude and phase of the IQ signals output by traditional devices will drift significantly, affecting test consistency.

[0004] Third, there's a lack of a closed-loop calibration mechanism. Traditional solutions rely on open-loop control, which can't dynamically adjust based on real-time signal feedback. This makes it difficult to compensate for non-ideal factors in complex operating conditions, such as DAC nonlinearity and pre-stage circuit amplitude-frequency errors. This prevents errors in signal processing from being corrected in a timely manner, further reducing signal accuracy. The hardware limitations of existing technologies lie in their reliance on fixed-parameter digital-to-analog converters (DACs) and simple filtering circuits, without the introduction of multi-stage calibration and real-time feedback mechanisms. The algorithm's single nature is reflected in the failure to incorporate environmental parameters (such as temperature) for dynamic modeling, making it impossible to effectively compensate for time-varying factors such as temperature drift. The lack of system integration is manifested in the independent operation of each functional module and the lack of collaborative optimization, resulting in significant error accumulation in the signal processing chain. Summary of the Invention

[0005] The object of the present invention is to provide a baseband IQ signal generation method and device to solve the problems of insufficient image rejection ratio, poor stability and lack of closed-loop calibration.

[0006] The purpose of the present invention can be achieved through the following technical solutions: A baseband IQ signal generation method comprises the following steps: S1: The control unit receives IQ baseband data, retrieves reference voltage and temperature compensation data, and verifies the data format, transmission rate, and storage order; S2: The data processing unit performs FIR filtering, DAC nonlinearity correction, and amplitude-frequency error compensation on the data through FPGA, and dynamically adjusts the calibration parameters based on real-time temperature; S3: The data conversion unit converts the signal through 16-bit DAC, and the pre-stage drive circuit completes amplitude adjustment and filtering; S4: The acquisition unit samples the output signal in real time and calculates the image rejection ratio. If it does not meet the standard, it triggers closed-loop calibration and adjusts the FPGA parameters until the indicators are met.

[0007] As a further solution of the present invention: the temperature compensation data in S2 establishes a temperature-error mapping table through historical test data, and uses a linear interpolation algorithm to achieve dynamic compensation with a resolution of 0.1°C.

[0008] As a further solution of the present invention: the image suppression ratio calculation method in S4 is: IQ Image =20log 10 (P image / P carrier ), the calibration threshold is set to -60dB.

[0009] A baseband IQ signal generating device, comprising: Control unit: used for data analysis, calibration parameter management and closed-loop control; Data processing unit: Based on FPGA, integrated with FIR filter module, nonlinear correction module and temperature compensation module; Data conversion unit: includes 16-bit DAC and pre-stage driver circuit, supports programmable gain and bandwidth switching; Reference and temperature compensation unit: provides reference voltage and real-time temperature data; Acquisition unit: 16-bit ADC, used for real-time sampling of output signals and error feedback.

[0010] As a further solution of the present invention: the FPGA adopts Xilinx ultrascale series to achieve real-time algorithm scheduling.

[0011] As a further solution of the present invention: the pre-stage driving circuit includes an eighth-order Butterworth low-pass filter with a cut-off frequency of 80 MHz and a ripple ≤ 0.5 dB.

[0012] The beneficial effects of the present invention are as follows: through multi-stage calibration and closed-loop feedback mechanism, the image rejection ratio can reach below -60dB, which is more than 10dB higher than the traditional solution, and can meet the high-precision testing requirements of high-end communication chips and radar equipment, and improve the reliability of test results; with the help of temperature compensation and real-time closed-loop feedback, the signal is stable in the range of 0℃~85℃, with an error of ≤1.5dB, adapting to various complex environmental conditions and broadening the application scenarios of the device; supporting multiple bandwidth switching such as 10MHz / 20MHz, the FPGA architecture facilitates algorithm upgrades and function expansions, can adapt to the evolution of future communication standards and technological development needs, and has a long technical life cycle. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The present invention will be further described below with reference to the accompanying drawings.

[0014] Figure 1 It is a flow chart of a baseband IQ signal generating method of the present invention. DETAILED DESCRIPTION

[0015] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present invention.

[0016] The baseband IQ signal generating device of the present invention includes the following core modules: The control unit, based on a PC or server, is responsible for data analysis, calibration parameter retrieval, and system timing control. As the core control hub of the entire device, this unit requires powerful data processing and command-transmitting capabilities to ensure coordinated operation between modules.

[0017] Data processing unit: Using an FPGA platform, it implements refined filtering, correction, and temperature compensation modeling of digital signals. The FPGA's high-speed parallel processing capabilities enable it to efficiently complete complex digital signal processing tasks.

[0018] The data conversion unit, which includes a 16-bit DAC and pre-driver circuits, performs digital-to-analog conversion and amplitude adjustment. The high-precision DAC is a key component for digital-to-analog conversion, while the pre-driver circuits further condition the analog signal.

[0019] Reference and Compensation Unit: Provides real-time reference voltage and temperature compensation data, supporting closed-loop calibration feedback. This unit provides a stable reference for the system and provides compensation data based on ambient temperature changes.

[0020] Acquisition and feedback unit: The 16-bit ADC collects the output signal in real time, forming a closed-loop calibration. The ADC's high-precision sampling capability ensures the accuracy of the feedback signal, providing a reliable basis for closed-loop calibration.

[0021] like Figure 1 As shown, a baseband IQ signal generating method includes: S1: Data analysis and calibration parameter loading: The control unit receives IQ baseband data input from the user, supporting various data formats such as binary and hexadecimal, and parses the data frame structure to extract the payload, such as the number of sampling points and symbol rate. It then retrieves preset calibration parameters from the system database, including reference voltages (2.5V and 5.0V reference voltages for DAC linearity calibration) and temperature compensation data (a temperature-error mapping table based on historical test data, covering the 0°C to 85°C temperature range with a resolution of 0.1°C). A CRC check is then performed on the data format (such as IEEE754 floating-point format), transmission rate (supporting 500Mbps), and storage order to ensure data integrity and prevent subsequent processing errors caused by data errors.

[0022] S2: Digital signal processing (FPGA platform): Multi-stage filtering and correction processing is performed on the FPGA platform. First, the first stage of filtering utilizes a multi-order FIR filter, which offers excellent filtering performance, with a passband ripple of ≤0.1dB and a stopband attenuation of ≥60dB, effectively suppressing out-of-band noise. Second, the second stage of correction applies compensation to each data point based on a preset calibration algorithm (such as least-squares fitting). This includes compensating for DAC nonlinearity by looking up a pre-stored DAC transfer function table (16-bit resolution, containing 65,536 calibration points) to correct for nonlinear distortion. Furthermore, the previous stage compensates for amplitude-frequency errors by applying gain and phase correction to each frequency point based on the measured amplitude-frequency response curve (frequency range 0-50MHz, resolution 100kHz).

[0023] At the same time, temperature compensation data is used to adjust the digital filter coefficients and calibration parameters based on the real-time ambient temperature (accuracy ±0.5°C) collected. This compensates for gain and phase errors caused by temperature drift. A temperature-coefficient mapping model is established: H(f,T)=H0(f)×(1+αT×(T−T0)), where αT is the temperature coefficient. This is obtained by fitting historical data, enabling dynamic response to temperature changes.

[0024] S3: Digital-to-analog conversion and analog signal conditioning: The data conversion unit uses a 16-bit DAC (such as the AD9726B, with a settling time of ≤50ns and an INL of ≤±1LSB) to convert the corrected digital signal into a differential analog IQ signal (voltage range ±5V). The pre-driver circuit uses a high-speed op amp (such as the THS3001CDGN or LMH6552MA, with a slew rate of 500V / μs) to achieve programmable gain control (gain range 0–40dB, 0.1dB resolution) to adjust the amplitude of the analog signal. An eighth-order Butterworth low-pass filter (with a selectable cutoff frequency of 80MHz and a ripple of ≤0.5dB) then filters out high-frequency noise. The driver output impedance is matched to 50Ω, ensuring an output power of ≥10dBm, meeting the input requirements of subsequent test equipment.

[0025] S4: Closed-loop calibration feedback mechanism: The acquisition unit samples the output signal in real time using a 16-bit ADC (e.g., a THS4631DGN high-speed op amp for amplitude adjustment and a high-speed ADC for signal acquisition). The sampling point density is 8 times the highest frequency of the signal, satisfying the Nyquist sampling theorem. The collected data is compared with the preset target value (e.g., an ideal sine wave, square wave, etc.) to calculate the image rejection ratio (IQImage): IQ Image =20loglog 10 (P image / P carrier ), where P image is the image signal power, P carrier is the carrier power.

[0026] If the calculated IQ Image > -60dB, indicating that the current signal accuracy does not meet the requirements, adjust the calibration parameters in the FPGA (such as filter coefficients, DAC gain factors), and re-execute steps S2 to S4 until IQ Image If the temperature change exceeds 5°C, it is considered that the ambient temperature has changed significantly, and the temperature compensation data is re-retrieved and the digital processing model is updated to adapt to the signal calibration requirements under the new temperature conditions.

[0027] Take 10MHz bandwidth signal generation as a specific embodiment: Hardware configuration: Control unit: It uses an industrial-grade PC configured with an Intel i7-11700 processor, 32GB RAM, and runs the Windows 10 IoT operating system. It has powerful data processing and communication capabilities and can stably control the operation of the entire device.

[0028] Data processing unit: Xilinx ultrascale FPGA XCKU060 is selected. This FPGA can realize real-time algorithm scheduling and high-speed digital signal processing to meet complex signal processing requirements.

[0029] Data conversion unit: uses a high-speed DAC (16-bit, 500MSPS) for digital-to-analog conversion, and uses an ADA4897 op amp as a pre-stage driver circuit to achieve signal amplitude adjustment and filtering.

[0030] Acquisition unit: Use a high-speed ADC (16-bit, 100MSPS) to sample the output signal in real time to ensure that the sampling accuracy and rate meet the closed-loop calibration requirements.

[0031] Temperature sensor: MAX31855 temperature sensor is used to communicate with the control unit through the SPI interface, with an accuracy of ±2°C, providing real-time ambient temperature data.

[0032] Software process: Parameter settings: Input IQ data rate to 10Mbps, modulation mode to QPSK. Recall calibration parameters, select reference voltage 2.5V, and load the temperature compensation table with a 25°C reference to provide a reference for subsequent signal processing.

[0033] Signal processing: A multi-order FIR filter with a cutoff frequency set to 10MHz is implemented within the FPGA to filter the raw data. A DAC nonlinearity correction table containing 65,536 linear interpolation points is used to correct for DAC nonlinear distortion. Furthermore, based on the measured amplitude-frequency response curve of the pre-amplifier circuit, the signal's amplitude-frequency error is compensated and the signal gain and phase are adjusted. The pre-amplifier driver gain is set to 20dB, and the output impedance is matched to 50Ω to ensure that the signal amplitude and impedance meet the requirements.

[0034] Closed-loop calibration: High-speed ADC collects output signals in real time and calculates IQ Image It is -62dB, which meets the -60dB index requirement. No parameter adjustment is required, and the signal generation process is completed.

[0035] Wide temperature range stability test: Test conditions: Temperature range: 0℃~85℃, step 10℃, covering the common temperature range of industrial applications.

[0036] Signal parameters: bandwidth 20MHz, carrier frequency 100MHz, amplitude 2Vpp. Set a wider bandwidth and higher carrier frequency to test the stability of the device under complex signal conditions.

[0037] Test results: Measured IQ at different temperaturesImage The data is as follows: At 25℃, measured IQ Image The value is -62.5dB, with an error of -0.5dB, which is better than the target value.

[0038] At 60℃, the measured IQ Image It is -61.5dB, with an error of +1.5dB.

[0039] At 85℃, the measured IQ Image It is -60.3dB, with an error of +0.3dB.

[0040] In the full temperature range, IQ Image The error is ≤-60dB, and the maximum error caused by temperature is +1.5dB, which verifies the effectiveness of the temperature compensation mechanism. The device can maintain stable high-precision signal output in a wide temperature range environment.

[0041] The above is a detailed description of an embodiment of the present invention. However, the content described is only a preferred embodiment of the present invention and should not be considered to limit the scope of the present invention. All equivalent changes and improvements made within the scope of the present invention should still fall within the scope of the patent coverage of the present invention.

Claims

1. A baseband IQ signal generation method, characterized in that: The following steps are involved: S1: The control unit receives IQ baseband data, retrieves reference voltage and temperature compensation data, and verifies the data format, transmission rate, and storage order; S2: The data processing unit performs FIR filtering, DAC nonlinearity correction, and amplitude-frequency error compensation on the data through FPGA, and dynamically adjusts the calibration parameters based on real-time temperature; S3: The data conversion unit converts the signal through 16-bit DAC, and the pre-stage drive circuit completes amplitude adjustment and filtering; S4: The acquisition unit samples the output signal in real time and calculates the image rejection ratio. If it does not meet the standard, it triggers closed-loop calibration and adjusts the FPGA parameters until the indicators are met.

2. The baseband IQ signal generating method according to claim 1, wherein: The temperature compensation data in S2 establishes a temperature-error mapping table through historical test data, and uses a linear interpolation algorithm to achieve dynamic compensation with a resolution of 0.1°C.

3. The baseband IQ signal generating method according to claim 1, wherein: The image rejection ratio calculation method in S4 is: IQ Image =20log 10 (P image / P carrier ), the calibration threshold is set to -60dB; Among them, P image is the image signal power, P carrier is the carrier power.

4. A device for generating a baseband IQ signal according to any one of claims 1 to 3, characterized in that: include: Control unit: used for data analysis, calibration parameter management and closed-loop control; Data processing unit: Based on FPGA, integrated with FIR filter module, nonlinear correction module and temperature compensation module; Data conversion unit: includes 16-bit DAC and pre-stage driver circuit, supports programmable gain and bandwidth switching; Reference and temperature compensation unit: provides reference voltage and real-time temperature data; Acquisition unit: 16-bit ADC, used for real-time sampling of output signals and error feedback.

5. The baseband IQ signal generating device according to claim 4, wherein: The FPGA adopts Xilinx UltraScale series to realize real-time algorithm scheduling.

6. The baseband IQ signal generating device according to claim 4, wherein: The pre-stage driving circuit includes an eighth-order Butterworth low-pass filter with a cut-off frequency of 80 MHz and a ripple of ≤0.5 dB.

Images