System and method for configuring signal path in interposer between integrated circuits

Abstract

The invention relates to a system and method for configuring a signal path in an interposer between integrated circuits. A circuit system includes: an interposer including a conductor and a switching circuit coupled to the conductor; a first integrated circuit die coupled to the interposer; and a second integrated circuit die coupled to the interposer. The first integrated circuit die includes a master controller circuit for configuring the switching circuit. The second integrated circuit die includes a secondary controller circuit. The primary controller circuit configures the configurable logic circuit in the second integrated circuit die by providing configuration bits to the secondary controller circuit via the interposer.

Description

Technical Field

[0001] The present disclosure relates to electronic circuit systems, and more particularly to systems and methods for configuring signal paths in an interposer between integrated circuits coupled to the interposer. Background Art

[0002] Configurable integrated circuits (ICs) can be configured by the user to implement desired custom logic functions. In a typical scenario, a logic designer uses a computer-aided design (CAD) tool to create a custom circuit design. When the design process is complete, the CAD tool generates an image containing configuration data bits. The configuration data bits are then loaded into configuration memory elements, which configure the configurable logic circuitry within the IC to perform the functions of the custom circuit design. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Figure 1 is a diagram depicting an example of an integrated circuit (IC) package that includes four integrated circuit (IC) dies and an active interposer.

[0004] Figure 2A It is a depiction Figure 1 An illustration of a side view of an integrated circuit package.

[0005] Figure 2B is a diagram depicting an example of a switching circuit that can be used to implement Figure 1 One of the switching circuits, a subset of the switching circuits, or each switching circuit in the active interposer.

[0006] Figure 3 is a diagram depicting an example of a configurable logic integrated circuit that can implement the techniques disclosed herein.

[0007] Figure 4A is a block diagram of a system that can be used to implement a circuit design to be programmed onto a programmable logic device using design software.

[0008] Figure 4B is a diagram depicting an example of a programmable logic device including a fabric die and a base die interconnected via microbumps.

[0009] Figure 5 is a block diagram illustrating a computing system configured to implement one or more aspects of the techniques disclosed herein. DETAILED DESCRIPTION

[0010] In some integrated circuit packages, multiple configurable integrated circuit (IC) dies are interconnected within a single integrated circuit package via an interposer to provide a higher density device. The configurable IC dies coupled together on the interposer form a multi-chip module (MCM).

[0011] In an MCM with four or more IC dies coupled together via an interposer, signal transmission delays between the IC dies through the interposer can be prohibitive. For example, in a previously known MCM with four IC dies, signals between two diagonally arranged IC dies (as viewed from a top view) in the MCM are routed through a third IC die located between the source and destination IC dies in the MCM. The cumulative signal delays through the third IC die can make the MCM unacceptable for many circuit systems.

[0012] Therefore, it is desirable to be able to dynamically program the coupling in the interposer in an MCM to form a signal path between two IC dies that optimizes signal transmission and mode operation. It is also desirable to be able to partially reconfigure the coupling in the interposer for specific functions in the configurable IC die.

[0013] According to some examples disclosed herein, an integrated circuit package includes multiple integrated circuit (IC) dies coupled to an active interposer. The active interposer includes switching circuits and interconnect conductors that can be partially and dynamically reconfigured. Two IC dies arranged diagonally (from a top view) in the IC die of the IC package can be coupled together through the interconnect conductors in the active interposer without routing through a third IC die, which greatly reduces the signal delay between the IC dies. These couplings between the IC dies through the interposer can simplify the logic layout in the IC die by allowing circuit layout flexibility. The IC dies can be configurable IC dies that can be fully configured, partially configured, and / or dynamically reconfigured through the interconnect conductors in the active interposer. The dynamic and partial reconfigurability of the switching circuits in the active interposer allows the protocols and operating modes in the IC package to be changed without redesigning the IC package.

[0014] According to other examples disclosed herein, one of the integrated circuit (IC) dies in an IC package includes a primary controller circuit (PCC) that configures (i.e., programs) multiple configurable IC dies in the IC package. The PCC can also configure and reconfigure switch circuits to configure signal paths through interconnect conductors in an active interposer. The other IC dies in the IC package can each include a secondary controller circuit (SCC). The active interposer can also include an SCC. The active interposer can include configurable coupling between the PCC and each SCC in the IC package to enable system programming. The PCC and SCC can control the state machine in the IC die in an optimized manner to achieve various operating modes.

[0015] The PCC can use the SCC to control the power-on of the IC dies in the IC package. The PCC can control the order in which the IC dies in the IC package are powered on by controlling the SCC. The PCC can also configure only one of the IC dies or only a portion of one or more IC dies. The PCC can also configure the reconfigurable switch circuits in the active interposer to achieve coupling between the IC dies. The PCC can also reconfigure and dynamically reprogram the reconfigurable switch circuits for different signal paths through the conductors, thereby achieving different operating modes. The PCC can only partially reconfigure the reconfigurable switch circuits in the active interposer that need to be reconfigured to achieve different couplings and signal paths, and can maintain the configuration of the remaining switch circuits in the active interposer. The reconfigurable switch circuits can be partially and dynamically reconfigured using configuration bit enable, fuse bit enable, or control bits generated by firmware or software to configure the reconfigurable switch circuits to establish coupling and signal paths between the IC dies.

[0016] In other examples, an IC package may include IC dies coupled together using metal masked, custom-routed interconnect conductors in a passive interposer using metal via connections. In these examples, the metal masked, custom-routed interconnect conductors in the passive interposer are specific to the package design. The routing interconnect conductors in the passive interposer can be modified for a specific design by modifying one or more new masks for one or more layers of the routing interconnect conductors, without having to modify the masks for all layers of the interposer, which reduces development costs.

[0017] One or more specific examples are described below. In order to provide a concise description of these examples, not all features of actual implementations are described in this specification. It should be understood that in the development of any such actual implementation, as in any engineering or design project, many implementation-specific decisions must be made to achieve the developer's specific goals, such as complying with system-related and business-related constraints, which may vary from implementation to implementation. Furthermore, it should be understood that such development work may be complex and time-consuming, but it remains a routine task of design, manufacturing, and production for those of ordinary skill having the benefit of this disclosure.

[0018] Throughout the specification and claims, the terms "connected" and "connect" refer to a direct electrical connection between the circuits being connected, without any intervening devices. The terms "coupled" and "coupling" refer to a direct electrical connection between the circuits or an indirect electrical connection through one or more passive or active intermediary devices that allow information to be transferred between the circuits. The term "circuit" may refer to one or more passive and / or active electrical components that are arranged to cooperate with each other to provide a desired functionality.

[0019] The present disclosure discusses integrated circuit devices, including configurable (programmable) logic integrated circuits, such as field programmable gate arrays (FPGAs) and programmable logic devices. As discussed herein, integrated circuits (ICs) can include hard logic and / or soft logic. Circuits in an integrated circuit device (e.g., in a configurable logic IC) that can be configured by an end user are referred to as "soft logic." "Hard logic" generally refers to circuits in an integrated circuit device that have significantly fewer or no configurable features than soft logic.

[0020] Figure 1 is a diagram depicting an example of an integrated circuit (IC) package 100 that includes four integrated circuit (IC) dies 101, 102, 103, and 104 and an active interposer 105. Figure 1 Four IC dies are shown; in other implementations, the IC package can have any number of IC dies according to the techniques disclosed herein. IC dies 101-104 can be any type of IC die, such as a configurable IC (e.g., a field programmable gate array (FPGA) or programmable logic device), a microprocessor IC, a graphics processing unit IC, a memory IC, an application-specific IC, a transceiver IC, a memory IC, or any combination thereof. Figure 1 A top view of IC package 100 is shown.

[0021] Active interposer 105 includes vertical routing interconnect conductors 130, horizontal routing interconnect conductors 140, and die-to-die routing interconnect conductors 151-154, which are configurable and reconfigurable to couple together any of IC dies 101-104 in IC package 100. Vertical routing interconnect conductors 130 may, for example, be located in a first conductive layer of active interposer 105, and horizontal routing interconnect conductors 140 may, for example, be located in a second conductive layer of active interposer 105. Active interposer 105 also includes reprogrammable interconnect switch circuits 160, which are configurable and reconfigurable to couple together any two intersecting routing interconnect conductors. For example, each of reprogrammable interconnect switch circuits 160 may include one or more multiplexers or transmission gates. The reprogrammable interconnect switch circuit 160 can be partially and dynamically reconfigured using configuration bits, partial reconfiguration bits, dynamic reconfiguration bits, fuse bits, or firmware / software generated control bits to set (and later change) the coupling between routing interconnect conductors, thereby establishing (and later changing) the coupling between IC dies 101-104. These bits can be used, for example, to control the reprogrammable interconnect switch circuit 160. In a passive interposer, the interconnect switch circuit 160 can be programmed using fuse bits or programmable vias set during interposer fabrication.

[0022] Each of the IC dies 101-104 can be coupled to two adjacent IC dies via die-to-die routing interconnect conductors. For example, input / output (I / O) circuitry 121 in IC die 101 and input / output (I / O) circuitry 123 in IC die 102 can be coupled together via die-to-die routing interconnect conductors 151 in active interposer 105. Input / output (I / O) circuitry 122 in IC die 101 and input / output (I / O) circuitry 125 in IC die 103 can be coupled together via die-to-die routing interconnect conductors 154 in active interposer 105. Input / output (I / O) circuitry 124 in IC die 102 and input / output (I / O) circuitry 128 in IC die 104 can be coupled together via die-to-die routing interconnect conductors 152 in active interposer 105. Input / output circuitry (I / O) 126 in IC die 103 and input / output circuitry (I / O) 127 in IC die 104 may be coupled together through die-to-die routing interconnect conductors 153 in active interposer 105 .

[0023] Furthermore, the IC dies 101-104 in the IC package 100 are arranged diagonally (from Figure 1Two IC dies (as viewed from a top view) can be coupled together via reconfigurable interconnect conductors 130, 140, and 151-154 in active interposer 105 without routing through a third IC die. This coupling significantly reduces signal delays between the two IC dies. For example, I / O circuitry 121 in IC die 101 and I / O circuitry 128 in IC die 104 can be coupled together via die-to-die interconnect conductor 151, one vertical interconnect conductor 130, one horizontal interconnect conductor 140, die-to-die interconnect conductor 152, and three interconnect switch circuits 160 in active interposer 105. As another example, I / O circuitry 124 in IC die 102 and I / O circuitry 125 in IC die 103 can be coupled together via die-to-die interconnect conductor 152, one horizontal interconnect conductor 140, die-to-die interconnect conductor 154, and two interconnect switch circuits 160 in active interposer 105. As another example, I / O circuitry 123 in IC die 102 and I / O circuitry 126 in IC die 103 may be coupled together through a die-to-die interconnect conductor 151, one vertical interconnect conductor 130, a die-to-die interconnect conductor 153, and two interconnect switch circuits 160 in active interposer 105. Signals may be transmitted between IC dies 101-104 through signal transmission paths in these couplings and any other couplings created through interconnect conductors and switch circuits 160 in active interposer 105.

[0024] like Figure 1 As shown, each of IC dies 101-104 includes four I / O circuits. Furthermore, each of IC dies 101-104 includes controller circuitry. IC die 101 includes primary controller circuitry (PCC) 111. IC die 102 includes secondary controller circuitry (SCC) 112. IC die 103 includes SCC 113. IC die 104 includes SCC 114. In some examples, PCC 111 and each of SCCs 112-114 may be a secure device manager (SDM) that performs security functions (such as encrypting and decrypting configuration bits) that configure the IC die.

[0025] The coupling between IC dies 101-104 through reconfigurable interconnect conductors 130, 140, and 151-154 in active interposer 105 can be partially or fully reconfigured to change one or more signal transmission paths between IC dies 101-104 by reconfiguring one or more switch circuits 160. PCC 111 in IC die 101 can configure and reconfigure switch circuits 160 using configuration bits, fuse bits, firmware or software bits, or other types of bits to set and reconfigure signal transmission paths through interconnect conductors in interposer 105 to establish coupling between IC dies 101-104. Switch circuits 160 can be controlled by metal via connections or using fuse bits during the fabrication process of the passive interposer.

[0026] Reconfiguration of the switch circuitry 160 enables partial reconfiguration of any subset of the die-to-die couplings between the IC dies 101-104, while other die-to-die couplings can remain unchanged to enable continued operation of the IC package. For example, an accelerated workload of a configurable IC may require different die-to-die couplings through the interposer 105, while the system infrastructure (e.g., Ethernet or Peripheral Component Interconnect Express (PCIe) connections) may need to remain active. Dynamic reconfiguration of the settings of the switch circuitry 160 can enable different die-to-die couplings. As described above, during the manufacturing process of the passive interposer, the couplings between the interconnect conductors in the passive interposer can be through-programmed using design-specific vias or metal masks.

[0027] In implementations where IC dies 101-104 are configurable IC dies, primary controller circuitry (PCC) 111 in IC die 101 can configure and partially or fully reconfigure the configurable logic circuitry in configurable IC dies 101-104. Furthermore, PCC 111 in IC die 101 can partially and dynamically configure and reconfigure switch circuitry 160 to change the signal transmission paths through routing interconnect conductors 130, 140, and 151-154 in active interposer 105. For example, PCC 111 can configure only one of IC dies 102-104 or partially reconfigure only one of IC dies 102-104. PCC 111 may perform configuration or reconfiguration of configurable logic circuits in IC dies 102-104 by providing configuration bits to SCCs 112-114 in IC dies 102-104 via I / O circuitry, switch circuitry 160, and reconfigurable interconnect conductors 130, 140, and / or 151-154 in active interposer 105. PCC 111 may partially and dynamically configure and reconfigure switch circuitry 160 to provide a signaling path for transmitting configuration bits from PCC 111 to SCCs 112-114 via routing interconnect conductors 130, 140, and 151-154 in interposer 105. Alternatively, PCC 111 may perform configuration or reconfiguration of configurable logic circuitry in IC dies 102-104 by providing configuration bits to SCCs 112-114 in IC dies 102-104, respectively, via fixed, non-programmable connections (e.g., vias) between conductors and I / O circuitry in active interposer 105. SCCs 112-114 may use the configuration bits received from PCC 111 to configure the configurable logic circuitry in the corresponding IC dies 102-104.

[0028] In some implementations, PCC 111 can dynamically reconfigure switch circuits 160 into different patterns to implement various operating modes and different signal transmission paths. PCC 111 can reconfigure only the switch circuits 160 that need to be changed to couple together the interconnect conductors required for the new signal transmission paths between IC dies, while maintaining the current configuration of the remaining switch circuits 160. The SCCs 112-114 in the IC dies 102-104 work in conjunction with PCC 111 to implement the operating modes of IC package 100, including full system programmability.

[0029] For example, during startup of the IC package 100, the PCC 111 can generate and send control signals to each of the SCCs 112-114 through the I / O circuits in the interposer 105, selected switch circuits in the switch circuitry 160, and interconnect conductors to control the order in which the IC dies 101-104 are powered on. The PCC 111 can also generate and send control signals to one or more of the SCCs 112-114 through selected switch circuits in the switch circuitry 160 and interconnect conductors in the interposer 105 to power down or keep powered down one or more of the IC dies 102-104, respectively. The PCC 111 and the SCCs 112-114 can work together to control the state machines across the IC dies 101-104 in an optimized manner to implement various operating modes.

[0030] Figure 2A It is a depiction Figure 1 FIG. 1 is an illustration of a side view of an integrated circuit package 100. Figure 2A In the side view of FIG, active interposer 105 is coupled to IC die 201 through conductive microbumps 211 and to IC die 202 through conductive microbumps 212. IC dies 201 and 202 may be IC dies 103 and 104, IC dies 104 and 102, IC dies 102 and 101, or IC dies 101 and 103, depending on the configuration of the IC die. Figure 2A From which of the four sides of the IC package 100 the view is taken.

[0031] Figure 2B is a diagram depicting an example of a switching circuit 250 that may be used to implement Figure 1 One of the switch circuits 160, a subset of the switch circuits 160, or each switch circuit 160 in the active interposer 105 of the embodiment of the present invention. For example, the switch circuit 250 may include one or more transmission gate circuits or two multiplexer circuits coupled in a bidirectional manner. The conduction state of the switch circuit 250 is controlled by one or more control bits CB. The control bits CB also control the direction of the signal allowed to pass through the switch circuit 250. Figure 2B In the example of , control bit CB may configure switch circuit 250 to allow a signal to be transmitted from one of conductors 130 to one of conductors 140 , or from one of conductors 140 to one of conductors 130 .

[0032] Figure 3 is a diagram illustrating an example of a configurable logic IC 300 that can implement the techniques disclosed herein. Figure 1 and Figures 2A-2B The disclosed IC die may include the architecture of a configurable logic IC 300. Figure 3As shown, configurable logic IC 300 includes a two-dimensional array of configurable functional circuit blocks, including a configurable logic array block (LAB) 310 and other functional circuit blocks, such as a random access memory (RAM) block 330 and a digital signal processing (DSP) block 320. Functional blocks, such as LAB 310, may include smaller configurable logic circuits (e.g., logic elements, logic blocks, or adaptive logic modules) that receive input signals and perform custom functions on the input signals to generate output signals.

[0033] In some examples, Figure 1 Each of the IC dies 101-104 is a configurable IC having the architecture of IC 300, such as Figure 3 The LAB 310 shown in FIG is a configurable logic circuit in each of the IC dies 101-104. In these examples, the main controller circuit (PCC) 111 in the IC die 101 can configure and partially or fully reconfigure the LAB 310 in each of the configurable IC dies 101-104. The PCC 111 can be configured by the PCC 111 through the LAB 310 described in detail in the present disclosure. Figure 1 The disclosed I / O circuits, switch circuits 160, and reconfigurable interconnect conductors 130, 140, and / or 151-154 in the active interposer 105 provide configuration data bits to the SCCs 112-114 in the IC dies 102-104 to perform configuration or reconfiguration of the LABs 310 in the IC dies 102-104. The SCCs 112-114 configure the LABs 310 in the IC dies 102-104, respectively, using the configuration data bits received from the PCC 111.

[0034] In addition, the configurable logic IC 300 may have input / output elements (IOEs) 302 for driving the configurable logic IC 300 to send signals and receive signals from other devices. The IOEs 302 may include parallel input / output circuits, serial data transceiver circuits, differential receiver and transmitter circuits, or other circuits for connecting one integrated circuit to another integrated circuit. As shown, the IOEs 302 may be located on the periphery of the chip. If desired, the configurable logic IC 300 may have IOEs 302 arranged in different ways. For example, the IOEs 302 may form one or more columns of input / output elements, one or more rows of input / output elements, or islands of input / output cells, which may be located anywhere on the configurable IC 300. Input / output elements 302 may include general-purpose input / output (GPIO) circuits (e.g., on the top and bottom edges of IC 300), high-speed input / output (HSIO) circuits (e.g., on the left edge of IC 300), and on-package input / output (OPIO) circuits (e.g., on the right edge of IC 300).

[0035] Configurable logic IC 300 may also include programmable interconnect circuitry in the form of vertical routing channels 330 (i.e., interconnects formed along the vertical axis of configurable IC 300) and horizontal routing channels 330 (i.e., interconnects formed along the horizontal axis of configurable IC 300), each of which includes at least one wire track for routing at least one wire. One or more of routing channels 330 and / or 350 may be part of a network-on-chip (NOC) having router circuitry.

[0036] Note that except Figure 3 In addition to the interconnect topology shown in FIG, other routing topologies can be used. For example, in the case of a three-dimensional integrated circuit, the routing topology can include wires running diagonally or horizontally and vertically along different parts of its extent, as well as wires running perpendicular to the plane of the device. The driver of the wire can be located at a different location than at one end of the wire.

[0037] In addition, it should be understood that the Figure 1 The disclosed embodiments can be implemented in any integrated circuit or electronic system. If desired, the functional blocks of such an integrated circuit can be arranged in more levels or layers, where multiple functional blocks are interconnected to form larger blocks. Other device arrangements can use functional blocks that are not arranged in rows and columns.

[0038] Configurable logic IC 300 may include programmable memory elements. Configuration bits may be loaded into the memory elements using IOE 302. Once loaded, each memory element provides a corresponding static control signal that controls the operation of the associated configurable functional block (e.g., LAB 310, DSP block 320, RAM block 330, or IOE 302). The configuration data bits may set the functionality of the configurable functional circuit blocks (i.e., soft logic) in IC 300.

[0039] In a typical scenario, the output of the loaded memory element is applied to the gate of the field-effect transistor in the functional block to turn certain transistors on or off, thereby configuring the logic (including routing paths) in the functional block. Programmable logic circuit elements controlled in this manner include multiplexers (e.g., multiplexers used to form routing paths in interconnect circuits), lookup tables, logic arrays, AND logic gates, OR logic gates, NAND logic gates, NOR logic gates, transmission gates, and the like.

[0040] The memory elements may use any suitable volatile and / or nonvolatile memory structure, such as random access memory (RAM) cells, fuses, antifuses, programmable read-only memory cells, mask-programmed and laser-programmed structures, combinations of these structures, etc. Because the memory elements are loaded with configuration data bits during programming, the memory elements are sometimes referred to as configuration memory or programmable memory elements.

[0041] Memory elements can be organized in a configuration memory array having rows and columns. Data registers spanning all columns and address registers spanning all rows can receive configuration data bits. Configuration data bits can be transferred to the data registers. When the appropriate address register is asserted, the data register writes the configuration data bits to the configuration memory bits for the row specified by the address register.

[0042] Configurable integrated circuit 300 may include configuration memory organized in sectors, whereby a sector may include configuration bits that specify the functionality and / or interconnection of subcomponents and wires in or across the sector.Each sector may include separate data and address registers.

[0043] Figure 3The configurable IC is only one example of an IC that may include an embodiment disclosed herein. The embodiments disclosed herein may be incorporated into any suitable integrated circuit or system. For example, the embodiments disclosed herein may be incorporated into various types of devices, such as a processor integrated circuit, a central processing unit, a memory integrated circuit, a graphics processing unit integrated circuit, an application specific standard product (ASSP), an application specific integrated circuit (ASIC), and a programmable logic integrated circuit. Examples of programmable logic integrated circuits include programmable array logic (PAL), programmable logic array (PLA), field programmable logic array (FPLA), electrically programmable logic device (EPLD), electrically erasable programmable logic device (EEPLD), logic cell array (LCA), complex programmable logic device (CPLD), and field programmable gate array (FPGA), etc.

[0044] The integrated circuit disclosed in one or more embodiments herein may be part of a data processing system that includes one or more of the following components: a processor; memory; input / output circuitry; and peripheral devices. The data processing system may be used in a variety of applications, such as computer networking, data networking, instrument configuration, video processing, digital signal processing, or any other suitable application. The integrated circuit may be used to perform a variety of different logic functions.

[0045] In general, the software and data for performing any function disclosed herein can be stored in a non-transient computer-readable storage medium. A non-transient computer-readable storage medium is a tangible computer-readable storage medium that stores data and software for later access, rather than a medium (e.g., a wire) that only transmits propagation electrical signals. Software code can sometimes be referred to as software, data, program instructions, instructions, or code. A non-transient computer-readable storage medium can include, for example, a computer memory chip, a non-volatile memory (such as a non-volatile random access memory (NVRAM)), one or more hard drives (e.g., a magnetic drive or solid-state drive), one or more removable flash drives or other removable media, a compact disc (CD), a digital versatile disc (DVD), a Blu-ray disc (BD), other optical media, and a floppy disk, a magnetic tape, or any other suitable memory or (one or more) storage device.

[0046] Figure 4AA block diagram of a system 10 is shown that can be used to implement a circuit design to be programmed onto a programmable logic device 19 using design software. A designer can implement circuit design functionality on an integrated circuit, such as a reconfigurable programmable logic device 19 (e.g., a field programmable gate array (FPGA)). The designer can use design software 14 to implement the circuit design to be programmed onto the programmable logic device 19. The design software 14 can use a compiler 16 to generate a low-level circuit design program (bitstream) 18, sometimes also referred to as a program object file and / or configuration program, that programs the programmable logic device 19. Thus, the compiler 16 can provide machine-readable instructions representing the circuit design to the programmable logic device 19. For example, the programmable logic device 19 can receive one or more programs (bitstreams) 18 that describe a hardware implementation to be stored in the programmable logic device 19. The programs (bitstreams) 18 can be programmed into the programmable logic device 19 as configuration programs 20. In some cases, the configuration programs 20 can represent accelerator functionality to be executed for machine learning, video processing, speech recognition, image recognition, or other highly specialized tasks.

[0047] In some implementations, a programmable logic device can be any integrated circuit device, including a programmable logic device having two separate integrated circuit dies in which at least some programmable logic structures are separated from at least some structural support circuitry for operating the programmable logic structures. Figure 4B One example of such a programmable logic device is shown in , but many other examples may be used, and it should be understood that the present disclosure is intended to cover any suitable programmable logic device in which the programmable logic structure and the structure support circuits are at least partially separated on different integrated circuit dies.

[0048] Figure 4B is a diagram depicting an example of a programmable logic device 25 including three structural dies 22 and two base dies 24 connected to each other by microbumps 26. Figure 4B In the example of FIG, at least some of the programmable logic structures of the programmable logic device 25 are in three structural dies 22, and at least some structural support circuits for operating the programmable logic structures are in two base dies 24. For example, Figure 3 Some circuitry of configurable IC 300 shown in FIG. 3 (eg, LAB 310 , DSP 320 , and RAM 330 ) may be located in structural die 22 , and some circuitry of IC 300 (eg, input / output elements 302 ) may be located in base die 24 .

[0049] Despite Figure 4BThe structural die 22 and the base die 24 appear in a one-to-one relationship or a two-to-one relationship, but other relationships may also be used. For example, a single base die 24 can be attached to several structural die 22, or several base die 24 can be attached to a single structural die 22, or several base die 24 can be attached to several structural die 22 (e.g., in a staggered pattern). Peripheral circuitry 28 can be attached to, embedded in, and / or disposed on top of the base die 24, and a heat sink 30 can be used to reduce heat buildup on the programmable logic device 25. The heat sink 30 can appear above (as shown) and / or below the package as shown (e.g., as a double-sided heat sink). The base die 24 can be attached to the package substrate 32 via conductive bumps 34. In Figure 4B In the example of FIG, two pairs of structural die 22 and base die 24 are shown communicatively connected to each other via interconnect bridges 36 (eg, embedded multi-die interconnect bridges (EMIBs)) and microbumps 38 at bridge interfaces 39 in base die 24.

[0050] In combination, the fabric die 22 and the base die 24 can operate in combination as a programmable logic device 25, such as a field programmable gate array (FPGA). It should be understood that, for example, when the fabric die 22 and the base die 24 operate in combination, an FPGA can represent a type of circuit and / or logic arrangement of a programmable logic device. Furthermore, for the purposes of this example, an FPGA is discussed herein, but it should be understood that any suitable type of programmable logic device can be used.

[0051] Figure 5 is a block diagram illustrating a computing system 500 configured to implement one or more aspects of the embodiments described herein. Computing system 500 includes a processing subsystem 70 having processor(s) 74, system memory 72, and programmable logic device 25 communicating via an interconnect path, which may include a memory hub 71. Memory hub 71 may be a separate component within a chipset assembly or integrated within processor(s) 74. Memory hub 71 is coupled to input / output (I / O) subsystem 50 via communication link 76. I / O subsystem 50 includes input / output (I / O) hub 51, which enables computing system 500 to receive input from input device(s) 62. Furthermore, I / O hub 51 enables a display controller, which may be included in processor(s) 74, to provide output to display device(s) 61. In one embodiment, display device(s) 61 coupled to I / O hub 51 may include a local display device, an internal display device, or an embedded display device.

[0052] In one embodiment, the processing subsystem 70 includes (one or more) parallel processors 75 coupled to the memory hub 71 via a bus or other communication link 73. The communication link 73 can use one of any number of standard-based communication link technologies or protocols, such as but not limited to PCI Express, or can be a vendor-specific communication interface or communication structure. In one embodiment, the (one or more) parallel processors 75 form a compute-centric parallel or vector processing system that can include a large number of processing cores and / or processing clusters, such as many integrated core (MIC) processors. In one embodiment, the (one or more) parallel processors 75 form a graphics processing subsystem that can output pixels to one of one or more display devices 61 coupled via the I / O hub 51. The (one or more) parallel processors 75 can also include a display controller and display interface (not shown) to enable direct connection to the (one or more) display devices 63.

[0053] Within the I / O subsystem 50, a system storage unit 56 may be connected to the I / O hub 51 to provide a storage mechanism for the computing system 500. An I / O switch 52 may be used to provide an interface mechanism to enable connections between the I / O hub 51 and other components, such as a network adapter 54 and / or a wireless network adapter 53 that may be integrated into the platform, as well as various other devices that may be added via add-in device(s) 55. The network adapter 54 may be an Ethernet adapter or another wired network adapter. The wireless network adapter 53 may include one or more of Wi-Fi, Bluetooth, near field communication (NFC), or other network devices including one or more wireless radios.

[0054] The computing system 500 may include Figure 5 Other components not shown include other port connections, optical storage drives, video capture devices, etc. that may also be connected to the I / O hub 51. Figure 5 The communication paths interconnecting the various components may be implemented using any suitable protocol, such as a PCI (Peripheral Component Interconnect) based protocol (e.g., PCI Express), or any other bus or point-to-point communication interface and / or protocol(s) such as the NV Link high-speed interconnect, or interconnect protocols known in the art.

[0055] In one embodiment, the parallel processor(s) 75 include circuits optimized for graphics and video processing (including, for example, video output circuitry) and constitute a graphics processing unit (GPU). In another embodiment, the parallel processor(s) 75 include circuits optimized for general-purpose processing while retaining the underlying computing architecture. In another embodiment, the components of the computing system 500 can be integrated with one or more other system elements on a single integrated circuit. For example, the parallel processor(s) 75, the memory hub 71, the processor(s) 74, and the I / O hub 51 can be integrated into a system-on-chip (SoC) integrated circuit. Alternatively, the components of the computing system 500 can be integrated into a single package to form a system-in-package (SIP) configuration. In one embodiment, at least a portion of the components of the computing system 500 can be integrated into a multi-chip module (MCM), which can be interconnected with other multi-chip modules into a modular computing system.

[0056] The computing system 500 shown herein is illustrative. Other variations and modifications are also possible. The connection topology, including the number and arrangement of bridges, the number of (one or more) processors 74, and the number of (one or more) parallel processors 75, can be modified as needed. For example, in some embodiments, the system memory 72 is connected to the (one or more) processors 74 directly rather than through a bridge, while other devices communicate with the system memory 72 through the memory hub 71 and (one or more) processors 74. In other alternative topologies, (one or more) parallel processors 75 are connected to the I / O hub 51 or directly to one of (one or more) processors 74, rather than being connected to the memory hub 71. In other embodiments, the I / O hub 51 and the memory hub 71 can be integrated into a single chip. Some embodiments may include two or more groups of (one or more) processors 74 connected via multiple sockets, which can be coupled to two or more instances of (one or more) parallel processors 75.

[0057] Some specific components shown herein are optional and may not be included in all implementations of computing system 500. For example, any number of add-in cards or peripherals may be supported, or certain components may be eliminated. Additionally, some architectures may be Figure 5 Components similar to those shown in FIG are referred to using different terminology. For example, in some architectures, memory hub 71 may be referred to as a north bridge, while I / O hub 51 may be referred to as a south bridge.

[0058] Additional examples are now described. Example 1 is a circuit system comprising: an interposer including conductors and switch circuitry coupled to the conductors; a first integrated circuit die coupled to the interposer, wherein the first integrated circuit die includes a primary controller circuit for configuring the switch circuitry; and a second integrated circuit die coupled to the interposer, wherein the second integrated circuit die includes a first secondary controller circuitry, and wherein the primary controller circuitry configures a first configurable logic circuit in the second integrated circuit die by providing a first configuration bit to the first secondary controller circuitry via the interposer.

[0059] In Example 2, the circuit system according to Example 1 also includes: a third integrated circuit die coupled to the interposer, wherein the third integrated circuit die includes a second auxiliary controller circuit, and wherein the main controller circuit configures the second configurable logic circuit in the third integrated circuit die by providing a second configuration bit to the second auxiliary controller circuit through the interposer.

[0060] In Example 3, the circuit system according to Example 2 also includes: a fourth integrated circuit die, coupled to the interposer, wherein the fourth integrated circuit die includes a third auxiliary controller circuit, and wherein the main controller circuit configures the third configurable logic circuit in the fourth integrated circuit die by providing a third configuration bit to the third auxiliary controller circuit through the interposer.

[0061] In Example 4, the circuit system according to Example 3 may preferably include, wherein the main controller circuit provides control signals to the first auxiliary controller circuit, the second auxiliary controller circuit, and the third auxiliary controller circuit through the switching circuit and the conductor to control the order in which the second integrated circuit die, the third integrated circuit die, and the fourth integrated circuit die are powered on.

[0062] In Example 5, the circuit system according to any one of Examples 1 to 4 may preferably include, wherein the main controller circuit reconfigures the first configurable logic circuit in the second integrated circuit die by providing second configuration bits to the first auxiliary controller circuit through the interposer.

[0063] In Example 6, the circuit system according to any one of Examples 1 to 5 may preferably include, wherein the main controller circuit configures the switch circuit to couple a first subset of the conductors together, and wherein the main controller circuit reconfigures the switch circuit to couple a second subset of the conductors together.

[0064] In Example 7, the circuit system according to any one of Examples 1 to 6 may preferably include, wherein the main controller circuit configures the first subset of the switch circuits to couple the subset of conductors together while maintaining the configuration of the second subset of the switch circuits.

[0065] In Example 8, the circuit system according to any one of Examples 1 to 7 may preferably include, wherein the first auxiliary controller circuit uses the first configuration bits to configure the first configurable logic circuit and the second configurable logic circuit in the second integrated circuit die.

[0066] In Example 9, the circuit system according to any one of Examples 1 to 8 may preferably include, wherein the main controller circuit reconfigures the switch circuit to provide a path for transmitting signals between the first integrated circuit die and the second integrated circuit die to implement the operating mode.

[0067] In Example 10, the circuit system according to any one of Examples 1 to 9 may preferably include, wherein the main controller circuit uses at least one of a second configuration bit, a partial reconfiguration bit, a dynamic reconfiguration bit, a fuse bit, a firmware bit, or a software bit to configure the switching circuit to set the coupling between the conductors.

[0068] Example 11 is a method for configuring a first configurable logic circuit, the method comprising: configuring a first switch circuit in the interposer using a main controller circuit in a first integrated circuit die coupled to the interposer to provide a first signal path, the first signal path being used to transmit a first signal through the first switch circuit and a first conductor in the interposer; providing a first configuration bit from the main controller circuit to a first auxiliary controller circuit in a second integrated circuit die coupled to the interposer through the interposer; and configuring the first configurable logic circuit in the second integrated circuit die using the first auxiliary controller circuit using the first configuration bit.

[0069] In Example 12, the method of Example 11 further includes configuring, using the main controller circuit, a second switch circuit in the interposer to provide a second signal path for transmitting a second signal through the second switch circuit in the interposer and the second conductor.

[0070] In Example 13, the method according to any one of Examples 11 to 12 also includes: providing a second configuration bit from the main controller circuit to a second auxiliary controller circuit in a third integrated circuit die coupled to the interposer through the interposer; and configuring the second configurable logic circuit in the third integrated circuit die using the second auxiliary controller circuit with the second configuration bit.

[0071] In Example 14, the method according to Example 13 also includes: providing a control signal from the main controller circuit to the first auxiliary controller circuit and the second auxiliary controller circuit through a third switching circuit in the interposer and a third conductor in the interposer to control the order in which the second integrated circuit die and the third integrated circuit die are powered on.

[0072] In Example 15, the method according to any one of Examples 11 to 14 further includes: configuring a second switch circuit in the interposer using the main controller circuit to provide a second signal path, the second signal path being used to transmit a second signal between the first integrated circuit die and the second integrated circuit die through the interposer to implement the operating mode.

[0073] In Example 16, the method according to any one of Examples 11 to 15 may preferably include, wherein the main controller circuit configures the first switch circuit to couple the first conductors together while maintaining the configuration of the second switch circuit in the interposer.

[0074] Example 17 is a non-transitory computer-readable storage medium comprising computer-readable instructions stored thereon, the computer-readable instructions causing a circuit system to: configure a first switch circuit in the interposer using a main controller circuit in a first integrated circuit die coupled to the interposer to provide a first signal path, the first signal path being used to transmit a first signal through the first switch circuit and a first conductor in the interposer; provide a first configuration bit from the main controller circuit to a first auxiliary controller circuit in a second integrated circuit die coupled to the interposer through the interposer; and configure a first configurable logic circuit in the second integrated circuit die using the first auxiliary controller circuit using the first configuration bit.

[0075] In Example 18, the non-transitory computer-readable storage medium according to Example 17 may preferably include, wherein the computer-readable instructions also cause the main controller circuit to provide a second configuration bit to the second auxiliary controller circuit through a second signal path to configure a second configurable logic circuit in a third integrated circuit coupled to the interposer.

[0076] In Example 19, the non-transitory computer-readable storage medium according to any one of Examples 17 to 18 may preferably include, wherein the computer-readable instructions further cause the main controller circuit to configure the first switching circuit using any one of a second configuration bit, a partial reconfiguration bit, a dynamic reconfiguration bit, a fuse bit, a firmware bit, or a software bit to implement the first signal path.

[0077] In Example 20, the non-transitory computer-readable storage medium according to any one of Examples 17 to 19 may preferably include, wherein the computer-readable instructions further cause the main controller circuit to control the order in which the second integrated circuit die and the third integrated circuit die in the circuit system are powered on by providing a control signal through the interposer.

[0078] The above description of exemplary embodiments has been provided for illustrative purposes. The above description is not intended to be exhaustive or limiting of the examples disclosed herein. The above content is merely illustrative of the principles of the present disclosure, and various modifications may be made by those skilled in the art. The above embodiments may be implemented individually or in any combination.

Claims

1. A circuit system comprising: an interposer comprising a conductor and a switching circuit coupled to the conductor; a first integrated circuit die coupled to the interposer, wherein the first integrated circuit die includes a main controller circuit for configuring the switch circuit; and A second integrated circuit die is coupled to the interposer, wherein the second integrated circuit die includes a first auxiliary controller circuit, and wherein the main controller circuit configures a first configurable logic circuit in the second integrated circuit die by providing a first configuration bit to the first auxiliary controller circuit through the interposer.

2. The circuit system according to claim 1 , further comprising: A third integrated circuit die is coupled to the interposer, wherein the third integrated circuit die includes a second auxiliary controller circuit, and wherein the main controller circuit configures a second configurable logic circuit in the third integrated circuit die by providing a second configuration bit to the second auxiliary controller circuit through the interposer.

3. The circuit system according to claim 2, further comprising: a fourth integrated circuit die coupled to the interposer, wherein the fourth integrated circuit die includes a third auxiliary controller circuit, and wherein the main controller circuit configures a third configurable logic circuit in the fourth integrated circuit die by providing a third configuration bit to the third auxiliary controller circuit through the interposer.

4. The circuit system according to claim 3, wherein: The main controller circuit provides control signals to the first auxiliary controller circuit, the second auxiliary controller circuit, and the third auxiliary controller circuit through the switching circuit and the conductor to control the order in which the second integrated circuit die, the third integrated circuit die, and the fourth integrated circuit die are powered on.

5. The circuit system according to any one of claims 1 to 4, wherein: The primary controller circuit reconfigures the first configurable logic circuit in the second integrated circuit die by providing second configuration bits to the first secondary controller circuit through the interposer.

6. The circuit system according to any one of claims 1 to 4, wherein: The main controller circuit configures the switch circuit to couple a first subset of the conductors together, and wherein the main controller circuit reconfigures the switch circuit to couple a second subset of the conductors together.

7. The circuit system according to any one of claims 1 to 4, wherein: The master controller circuit configures a first subset of the switching circuits to couple the subset of the conductors together while maintaining the configuration of a second subset of the switching circuits.

8. The circuit system according to any one of claims 1 to 4, wherein: The first secondary controller circuit configures the first and second configurable logic circuits in the second integrated circuit die using the first configuration bits.

9. The circuit system according to any one of claims 1 to 4, wherein: The main controller circuit reconfigures the switch circuit to provide a path for transmitting signals between the first integrated circuit die and the second integrated circuit die to implement an operating mode.

10. The circuit system according to any one of claims 1 to 4, wherein: The master controller circuit configures the switch circuit using at least one of a second configuration bit, a partial reconfiguration bit, a dynamic reconfiguration bit, a fuse bit, a firmware bit, or a software bit to set the coupling between the conductors.

11. A method for configuring a first configurable logic circuit, the method comprising: configuring, using a main controller circuit in a first integrated circuit die coupled to the interposer, a first switch circuit in the interposer to provide a first signal path for transmitting a first signal through the first switch circuit and a first conductor in the interposer; providing a first configuration bit from the primary controller circuit through the interposer to a first secondary controller circuit in a second integrated circuit die coupled to the interposer; as well as The first configurable logic circuit in the second integrated circuit die is configured with the first configuration bits using the first secondary controller circuit.

12. The method according to claim 11, further comprising: The main controller circuit is used to configure a second switch circuit in the interposer to provide a second signal path for transmitting a second signal through the second switch circuit and a second conductor in the interposer.

13. The method according to any one of claims 11 to 12, further comprising: providing a second configuration bit from the primary controller circuit through the interposer to a second secondary controller circuit in a third integrated circuit die coupled to the interposer; as well as A second configurable logic circuit in the third integrated circuit die is configured with the second configuration bits using the second secondary controller circuit.

14. The method according to claim 13, further comprising: Control signals are provided from the primary controller circuit to the first and second secondary controller circuits through a third switch circuit in the interposer and a third conductor in the interposer to control the order in which the second and third integrated circuit dies are powered on.

15. The method according to any one of claims 11 to 12, further comprising: A second switch circuit in the interposer is configured using the main controller circuit to provide a second signal path for transmitting a second signal between the first integrated circuit die and the second integrated circuit die through the interposer to implement an operating mode.

16. The method according to any one of claims 11 to 12, wherein The main controller circuit configures the first switching circuit to couple the first conductors together while maintaining the configuration of the second switching circuit in the interposer.

17. A non-transitory computer-readable storage medium comprising computer-readable instructions stored thereon, the computer-readable instructions causing a circuit system to: configuring, using a main controller circuit in a first integrated circuit die coupled to the interposer, a first switch circuit in the interposer to provide a first signal path for transmitting a first signal through the first switch circuit and a first conductor in the interposer; providing a first configuration bit from the primary controller circuit through the interposer to a first secondary controller circuit in a second integrated circuit die coupled to the interposer; as well as A first configurable logic circuit in the second integrated circuit die is configured with the first configuration bits using the first secondary controller circuit.

18. The non-transitory computer-readable storage medium of claim 17, wherein: The computer-readable instructions further cause the primary controller circuit to provide second configuration bits to a second secondary controller circuit through the interposer to configure a second configurable logic circuit in a third integrated circuit coupled to the interposer.

19. The non-transitory computer-readable storage medium according to any one of claims 17 to 18, wherein: The computer-readable instructions further cause the main controller circuit to configure the first switch circuit using any of second configuration bits, partial reconfiguration bits, dynamic reconfiguration bits, fuse bits, firmware bits, or software bits to implement the first signal path.

20. The non-transitory computer-readable storage medium according to any one of claims 17 to 18, wherein: The computer-readable instructions further cause the main controller circuit to control the order in which the second integrated circuit die and the third integrated circuit die in the circuit system are powered on by providing control signals to the second integrated circuit die and the third integrated circuit die through the interposer.

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