Simulator model based on second order locally active memristor

Abstract

The application discloses a simulator model based on a second-order local active memristor, and a simulator model is constructed based on a mathematical model of the second-order local active memristor. The constructed simulator model comprises integrated operational amplifiers U1, U2, U3, multipliers U4, U5, U6, U7, U8 and resistors and capacitors. U1 is used for integral operation and inverting amplification operation, and outputs a state variable x in the interior of the memristor. U2 is used for realizing inverting amplification operation and integral operation, and obtaining a state variable y in the interior of the memristor. U3 is used for realizing inverting addition operation and inverting amplification operation, and obtaining a memristor output current i through a series connection of an external resistor. The multipliers U4, U5, U6, U7 and U8 are used for realizing multiplication operation of signals. The simulator model can replace an actual second-order local active memristor to carry out experimental and applied research.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of circuit design, and relates to a second-order locally active memristor, in particular to a simulator model based on the second-order locally active memristor. BACKGROUND

[0002] The memristor is the fourth basic circuit element after the resistor, the capacitor and the inductor, and was first predicted from the theoretical mathematical symmetry by the Chinese scientist Chua in 1971. The core feature is that the resistance value can dynamically change according to the amount of charge flowing through, and can maintain the state after power-off, realizing non-volatile storage. The memristor has the characteristics of "storage and calculation in one" (that is, direct calculation in the storage unit), which provides a new idea for breaking through the bottleneck of the traditional von Neumann architecture, and shows great potential in the fields of artificial intelligence, neuromorphic computing and big data processing.

[0003] The second-order locally active memristor is an important branch in the research of the memristor in recent years, and has the core feature of having two internal state variables and exhibiting local activity under specific working conditions, that is, being able to generate energy gain (similar to the behavior of "negative differential resistance") under small signal excitation, thereby supporting more complex nonlinear dynamic behaviors. The second-order locally active memristor represents an important trend of the development of the research of the memristor from a simple model to a complex system, and provides a new implementation path for constructing artificial intelligence hardware closer to the biological nervous system.

[0004] Compared with the passive memristor, the research on the second-order locally active memristor is relatively less, and there is a lack of mathematical models and circuit models in reality. Therefore, the application designs a mathematical model and a simulator based on the second-order locally active memristor. The mathematical model can provide a theoretical model for the physical implementation of the second-order locally active memristor, and the simulator can replace the actual second-order locally active memristor for experimental and application research, which has important significance for the implementation and research of the second-order locally active memristor. SUMMARY

[0005] To solve the above technical problems, the application provides a simulator model based on a second-order locally active memristor, a mathematical model of the second-order locally active memristor is used to construct the simulator model of the second-order locally active memristor, the mathematical model can provide a theoretical model for the physical implementation of the second-order locally active memristor, and the simulator model is used to simulate the volt-ampere characteristics of the memristor, and replace the actual memristor for circuit design and application.

[0006] To achieve the above purpose, the technical scheme adopted by the application is that t is a corresponding time point;

[0007] The simulator model based on the second-order locally active memristor is constructed based on the mathematical model of the second-order locally active memristor,

[0008] Based on the mathematical model of the second-order local active memristor, as follows:

[0009] ;

[0010] wherein i and u are the current and voltage of the memristor, x and y are the state variables of the memristor,

[0011] The simulator model comprises integrated operational amplifier U1, integrated operational amplifier U2, integrated operational amplifier U3, multipliers U4, U5, U6, U7, U8 and component resistors and capacitors,

[0012] The integrated operational amplifier U1 is used to implement inverse addition operation, inverse amplification operation and integration operation, and comprises a first control chip, resistors R1-R11 and capacitor C1, the pin 1, 2 and 3 of the first control chip and the resistors R1 and R2 constitute a first inverse amplifier, the pin 12, 13 and 14 of the first control chip and the resistors R3, R4, R5 and capacitor C1 constitute a first integrator, the pin 5, 6 and 7 of the first control chip and the resistors R6 and R7 constitute a second inverse amplifier, the pin 8, 9 and 10 of the first control chip and the resistors R8 and R9 constitute a third inverse amplifier, wherein the pin 1 outputs voltage -u, the pin 7 outputs -X1, the pin 8 outputs X1, and the pin 14 outputs the internal state variable x of the memristor;

[0013] The integrated operational amplifier U2 is used to implement inverse addition operation, inverse amplification operation and integration operation, and comprises a second control chip, resistors R10-13 and capacitor C2, the pin 1, 2 and 3 of the second control chip and the resistors R10 and R11 and capacitor C2 constitute a second integrator, the pin 5, 6 and 7 of the second control chip and the resistors R12 and R13 constitute a fourth inverse amplifier, wherein the pin 1 outputs the internal state variable y of the memristor, and the pin 7 outputs -Y1;

[0014] The integrated operational amplifier U3 is used to implement inverse addition operation and inverse amplification operation, and comprises a third control chip and resistors R14-R20, the pin 5, 6 and 7 of the third control chip and the resistors R14 and R15 constitute a fifth inverse amplifier, the pin 8, 9 and 10 of the third control chip and the resistors R16 and R17 constitute a sixth inverse amplifier, the pin 1, 2 and 3 of the third control chip and the resistors R18, R19 and R20 constitute an inverse adder, wherein the pin 7 outputs -X2 2 , the pin 8 outputs -Y2 2 , and the pin 1 outputs current i;

[0015] The multipliers U4, U5, U6, U7 and U8 are used to implement signal multiplication operations.

[0016] The multiplier U4 is used to realize the voltage u1 pin 9 1-9 and U2 pin 7 voltage u 2-7 The voltage at the output terminal W of the multiplier U4 is:

[0017] ;

[0018] The multiplier U5 is used to realize the voltage u1 pin 7 1-7 The voltage at the output terminal W of the multiplier U5 is:

[0019] ;

[0020] The multiplier U6 is used to realize the voltage u at pin 7 of U2 2-7 The voltage at the output terminal W of the multiplier U6 is:

[0021] ;

[0022] The multiplier U7 is used to realize the input voltage u and the voltage u of U3 pin 7 3-7 The voltage at the output terminal W of the multiplier U7 is:

[0023] ;

[0024] The multiplier U8 is used to realize the input voltage u and the voltage u at pin 8 of U3. 3-8 The voltage at the output terminal W of the multiplier U7 is:

[0025] .

[0026] As a preferred technical solution of the present invention: the first control chip in the integrated operational amplifier U1 adopts TL084, pin 1 is connected to pin 2 through resistor R2; pin 2 is connected to the memristor voltage u through resistor R1, pin 3 is grounded; pin 5 is grounded; pin 6 is connected to pin 14 through resistor R6; pin 7 is connected to pin 6 through resistor R7; pin 8 is connected to pin 9 through resistor R9; pin 9 is connected to pin 7 through resistor R8; pin 10 is grounded; pin 12 is grounded; pin 13 is connected to pin 14 and multiplier U4 output -X1Y1 / 10 through resistor R3, resistor R4, and resistor R5 respectively. 4 , pin 1; pin 14 is connected to pin 13 through capacitor C1; pin 4 is connected to power supply VCC; pin 11 is connected to power supply VEE.

[0027] As a preferred technical solution of the present invention: the second control chip in the integrated operational amplifier U2 adopts TL084, pin 1 is connected to pin 2 through capacitor C2; pin 2 is connected to pin 1 and the first control chip pin 1 output -u through resistors R10 and R11 respectively; pin 3 is grounded; pin 5 is grounded; pin 6 is connected to pin 1 through resistor R12; pin 7 is connected to pin 6 through resistor R13; pin 4 is connected to power supply VCC; pin 11 is connected to power supply VEE.

[0028] As a preferred technical solution of the present invention: the third control chip in the integrated operational amplifier U3 adopts TL084, and pin 6 is connected to the multiplier U5 output X1 through the resistor R14. 2 / 10 4 Pin 7 is connected to pin 6 through resistor R15; Pin 9 is connected to multiplier U6 output Y1 through resistor R16 2 / 10 4 Pin 8 is connected to pin 9 through resistor R17; Pin 2 is connected to multiplier U7 output -X2 through resistor R18 and resistor R19 respectively 2 u / 10 4 and multiplier U8 output - Y2 2 u / 10 4 Also includes a resistor R21, pin 1 is connected to pin 2 and the memristor current i through resistors R20 and R21 respectively; pin 3 and pin 5 are grounded; pin 4 is connected to the power supply VCC; pin 11 is connected to the power supply VEE.

[0029] As a preferred technical solution of the present invention: the multiplier U4 is controlled by an AD633 chip, the multiplier U4 pin 1 is connected to the pin 8 of the first control chip to output X1; pin 3 is connected to the pin 7 of the second control chip to output -Y1; pins 2, 4, and 6 are grounded; pin 8 is connected to the power supply VCC; pin 5 is connected to the power supply VEE; pin 7 outputs -X1Y1 / 10 4 .

[0030] As a preferred technical solution of the present invention: the multiplier U5 is controlled by the AD633 chip, the multiplier U5 pin 1 is connected to the pin 8 of the first control chip to output X1; pin 3 is connected to the pin 8 of the first control chip to output X1; pins 2, 4, and 6 are grounded; pin 8 is connected to the power supply VCC; pin 5 is connected to the power supply VEE; pin 7 outputs X1 2 / 10 4 .

[0031] As a preferred technical scheme of the present application: the multiplier U6 adopts AD633 chip control, the pin 1 of the multiplier U6 is connected with the pin 7 output-Y1 of the second control chip; the pin 3 is connected with the pin 7 output-Y1 of the second control chip; the pins 2, 4 and 6 are grounded; the pin 8 is connected with the power supply VCC; the pin 5 is connected with the power supply VEE; and the pin 7 output is Y1 2 / 10 4 .

[0032] As a preferred technical scheme of the present application: the multiplier U7 adopts AD633 chip control, the pin 1 of the multiplier U7 is connected with the pin 7 output-X2 of the third control chip 2 ; the pin 3 is connected with the memristor voltage u; the pins 2, 4 and 6 are grounded; the pin 8 is connected with the power supply VCC; the pin 5 is connected with the power supply VEE; and the pin 7 output is-X2 2 u / 10 4 .

[0033] As a preferred technical scheme of the present application: the multiplier U8 adopts AD633 chip control, the pin 1 of the multiplier U8 is connected with the pin 8 output-Y2 of the third control chip 2 ; the pin 3 is connected with the memristor voltage u; the pins 2, 4 and 6 are grounded; the pin 8 is connected with the power supply VCC; the pin 5 is connected with the power supply VEE; and the pin 7 output is-Y2 2 u / 10 4 .

[0034] Compared with the prior art, the present application has the following beneficial effects:

[0035] The present application designs a mathematical model based on a second-order local active memristor, and establishes a simulator model according to the mathematical model, the simulator model containing three integrated operational amplifiers U1, U2 and U3, five multipliers U4, U5, U6, U7 and U8, and components resistors and capacitors for connection, so as to realize the volt-ampere characteristic of the second-order local active memristor through the simulator model. In the case that the actual memristor device cannot be obtained, the actual memristor can be replaced to realize the circuit design, experiment and application related to the memristor, which has important practical significance for the characteristic and application research of the memristor.

[0036] The present application uses integrated operational amplifier and analog multiplier to realize corresponding operation in the characteristic of memristor, wherein the integrated operational amplifier is mainly used to realize the inverse addition operation, integral operation, and inverse amplifier of voltage, and the analog multiplier is used to realize the product operation of voltage. BRIEF DESCRIPTION OF DRAWINGS

[0037] Figure 1 is the equivalent circuit block diagram of the simulator model in the present application;

[0038] Figure 2 is the analog equivalent circuit schematic diagram of the simulator model in the present application;

[0039] Figure 3 is the output waveform diagram of the memristor when f = 1000 Hz;

[0040] Figure 4 is the hysteresis curve diagram of the memristor when f = 1000 Hz;

[0041] Figure 5 is the hysteresis curve diagram of the memristor when f = 3000 Hz. DETAILED DESCRIPTION

[0042] The present application will be further described in detail below in combination with the accompanying drawings and specific embodiments:

[0043] The present application designs a mathematical model based on the second-order local active memristor, and the designed mathematical model can provide a theoretical model for the physical realization of the second-order local active memristor. The simulator model is constructed based on the designed mathematical model, and the simulator model can replace the actual second-order local active memristor to carry out experimental and application research, which has important significance for the realization and research of the new second-order local active memristor.

[0044] The mathematical model based on the second-order local active memristor proposed in the present application is as follows:

[0045] ;

[0046] Wherein, i and u are the current and voltage of the memristor, and x and y are the state variables of the memristor.

[0047] AsFigure 1 As shown, a simulator model is constructed based on a mathematical model of a second-order local active memristor, and the simulator model comprises integrated operational amplifier U1, integrated operational amplifier U2, integrated operational amplifier U3, multipliers U4, U5, U6, U7, U8 and component resistors and capacitors.

[0048] The integrated operational amplifier U1 is used for integral operation and inverse amplification operation, and outputs a state variable x inside the memristor;

[0049] The integrated operational amplifier U2 is used for inverse amplification operation and integral operation, and obtains a state variable y inside the memristor;

[0050] The integrated operational amplifier U3 is used for inverse addition operation and inverse amplification operation, and obtains a memristor output current i by connecting an external resistor in series;

[0051] The first control chip, the second control chip and the third control chip in the integrated operational amplifiers U1, U2 and U3 in the application all adopt a chip TL084.

[0052] The multipliers U4, U5, U6, U7 and U8 are used for multiplication operation of signals,

[0053] The multipliers U4, U5, U7 and U8 in the application all adopt a chip AD633.

[0054] As shown in the figure, Figure 2 The pins 1, 2 and 3 of the first control chip in the integrated operational amplifier U1 and the resistors R1 and R2 constitute a first inverse amplifier, an external voltage u is connected to the pin 2 through the resistor R1, and according to the calculation formula of the inverse amplifier, the voltage of the output pin 1 is:

[0055]

[0056] Since R1=10kΩ and R2=10kΩ, the voltage of the pin 1 is finally:

[0057]

[0058] The pins 12, 13 and 14 of the first control chip, the resistors R3, R4 and R5, and the capacitor C1 constitute a first integrator, the input end of the pin 13 is connected to the internal state variable x of the memristor, the output voltage -u of the pin 1 and the output of the multiplier U4-X1Y1 / 10 4 , and the current i 1-13 of the pin 13 is:

[0059]

[0060] ​​​The current on pin 14 is:

[0061] ;

[0062] According to the operational amplifier characteristics of the amplifier, the current i 1-14 on pin 14 is the same as the current i 1-13 on pin 13, so we have:

[0063] ;

[0064] Because R3 = 10kΩ, R4 = 20kΩ, R5 = 10kΩ, and the capacitance C1 = 10μF, the output voltage on pin 14 can be obtained as:

[0065] ;

[0066] The pins 5, 6, and 7 of the first control chip and the resistors R6 and R7 form a second inverting amplifier circuit. Pin 5 is directly grounded, the state variable x of the memristor is connected to pin 6 through resistor R6, and pin 7 is connected to pin 6 through resistor R7. With R6 = 1KΩ and R7 = 100KΩ, the output voltage can be obtained as:

[0067] ;

[0068] The pins 8, 9, and 10 of the first control chip and the resistors R8 and R9 form a third inverting amplifier. Pin 10 is directly grounded, the output -X1 of pin 7 is connected to pin 9 through resistor R8, and pin 8 is connected to pin 8 through resistor R9. With R8 = 10KΩ and R9 = 10KΩ, the output voltage can be obtained as:

[0069] ;

[0070] The pins 1, 2, and 3 of the second control chip in the integrated operational amplifier U2 and the resistors R10 and R11 and the capacitor C2 form a second integrator. Pin 3 is directly grounded, the internal state variable y of the memristor is connected to pin 2 through resistor R10, and the output -u of the first control chip pin 1 is connected to pin 1 through resistor R11. The current on pin 2 can be obtained as:

[0071] ;

[0072] The corresponding current on pin 1 is:

[0073] ;

[0074] With R10 = 10kΩ and R11 = 20kΩ, and the current on pin 2 being equal to the current on pin 1, the output voltage on pin 1 can be obtained as:

[0075] ;

[0076] The pin 5, pin 6, pin 7 of the second control chip and the resistors R12 and R13 constitute a fourth inverting amplifier, the pin 5 is directly grounded, the pin 6 is connected with the internal variable y of the memistor through the resistor R12, and the pin 7 is connected with the pin 6 through the resistor R13, and the output voltage of the pin 7 can be obtained as:

[0077] .

[0078] The pin 5, pin 6, pin 7 of the third control chip in the integrated operational amplifier U3 and the resistors R14 and R15 constitute a fifth inverting amplifier, the pin 5 is directly grounded, the output voltage X1 of the multiplier U5 is connected with the pin 6 through the resistor R14, the pin 7 is an output terminal, and the pin 6 is connected with the pin 7 through the resistor R15, and the output voltage is: 2 / 10 4

[0079] ;

[0080] The pin 8, pin 9, pin 10 of the third control chip and the resistors R16 and R17 constitute a sixth inverting amplifier, the pin 10 is directly grounded, the output voltage Y1 of the multiplier U6 is connected with the pin 9 through the resistor R16, the pin 8 is an output terminal, and the pin 9 is connected with the pin 8 through the resistor R17, and the output voltage is: 2 / 10 4

[0081] ;

[0082] The pin 1, pin 2, pin 3 of the third control chip and the resistors R18, R19 and R20 constitute an inverting adder, the pin 3 is directly grounded, the output voltage -X2 of the multiplier U7 is connected with the pin 2 through the resistor R18, the output voltage -Y2 of the multiplier U8 is connected with the pin 2 through the resistor R19, and the output voltage of the pin 1 is connected with the pin 2 through the resistor R20, and the output voltage of the pin 1 is: 2 u / 10 4 2 u / 10 4

[0083] ;

[0084] Because the resistors R18=10kΩ, R19=10kΩ and R20=10kΩ, the output voltage of the pin 1 can be changed as:

[0085] ;

[0086] ​​​​Pin 1 outputs current i through series resistance R21:

[0087] ;

[0088] Because R21=10Ω, u=1V is converted to u=10 3 mV at this time, and combined with the relationship between X2, Y2 and X1, Y1 and x, y, the current i is:

[0089] .

[0090] The multiplier U4 is used to realize the product operation of the voltage u 1-9 at pin 9 of U1 and the voltage u 2-7 at pin 7 of U2, and since the multiplier has a voltage of 10V (10 4 mV) that cannot be ignored, the voltage at the output W of the multiplier U4 is:

[0091] ;

[0092] The multiplier U5 is used to realize the square operation of the voltage u 1-7 at pin 7 of U1, and since the multiplier has a voltage of 10V (10 4 mV) that cannot be ignored, the voltage at the output W of the multiplier U5 is:

[0093] ;

[0094] The multiplier U6 is used to realize the square operation of the voltage u 2-7 at pin 7 of U2, and since the multiplier has a voltage of 10V (10 4 mV) that cannot be ignored, the voltage at the output W of the multiplier U6 is:

[0095] ;

[0096] The multiplier U7 is used to realize the product operation of the input voltage u and the voltage u 3-7 at pin 7 of U3, and since the multiplier has a voltage of 10V (10 4 mV) that cannot be ignored, the voltage at the output W of the multiplier U7 is:

[0097] ;

[0098] The multiplier U8 is used to realize the product operation of the input voltage u and the voltage u 3-8 at pin 8 of U3, and since the multiplier has a voltage of 10V (10 4 mV) that cannot be ignored, the voltage at the output W of the multiplier U7 is:

[0099] .

[0100] The specific connection of the three integrated operational amplifiers U1, U2 and U3 is as follows:

[0101] As shown in Figure 2 , the first control chip in the integrated operational amplifier U1 adopts TL084, pin 1 is connected to pin 2 through resistor R2; pin 2 is connected to the memistor voltage u through resistor R1, pin 3 is grounded; pin 5 is grounded; pin 6 is connected to pin 14 through resistor R6; pin 7 is connected to pin 6 through resistor R7; pin 8 is connected to pin 9 through resistor R9; pin 9 is connected to pin 7 through resistor R8; pin 10 is grounded; pin 12 is grounded; pin 13 is connected to pin 14, the output -X1Y1 / 10 of the multiplier U4 and pin 1 through resistors R3, R4 and R5 respectively. 4 Pin 14 is connected to pin 13 through capacitor C1; pin 4 is connected to power supply VCC; pin 11 is connected to power supply VEE.

[0102] As shown in Figure 2 , the second control chip in the integrated operational amplifier U2 adopts TL084, pin 1 is connected to pin 2 through capacitor C2; pin 2 is connected to pin 1 and -u through resistors R10 and R11 respectively; pin 3 is grounded; pin 5 is grounded; pin 6 is connected to pin 1 through resistor R12; pin 7 is connected to pin 6 through resistor R13; pin 4 is connected to power supply VCC; pin 11 is connected to power supply VEE.

[0103] As shown in Figure 2 , the third control chip in the integrated operational amplifier U3 adopts TL084, pin 6 is connected to the output X1 2 / 10 4 of the multiplier U5 through resistor R14; pin 7 is connected to pin 6 through resistor R15; pin 9 is connected to the output Y1 2 / 10 4 of the multiplier U6 through resistor R16; pin 8 is connected to pin 9 through resistor R17; pin 2 is connected to the output -X2 2 u / 10 4 of the multiplier U7 and the output -Y2 2 u / 10 4 of the multiplier U8 through resistors R18 and R19 respectively; pin 1 is connected to pin 2 and the memistor current i through resistors R20 and R21 respectively; pins 3 and 5 are grounded; pin 4 is connected to power supply VCC; pin 11 is connected to power supply VEE.

[0104] As shown in Figure 2 , the multipliers U4, U5, U6, U7 and U8 all adopt AD633.

[0105] Pin 1 of multiplier U4 is connected to pin 8 of the first control chip to output X1; pin 3 is connected to pin 7 of the second control chip to output -Y1; pins 2, 4, and 6 are grounded; pin 8 is connected to power supply VCC; pin 5 is connected to power supply VEE; pin 7 outputs -X1Y1 / 10 4 .

[0106] Pin 1 of multiplier U5 is connected to pin 8 of the first control chip to output X1; pin 3 is connected to pin 8 of the first control chip to output X1; pins 2, 4, and 6 are grounded; pin 8 is connected to power supply VCC; pin 5 is connected to power supply VEE; pin 7 output is X1 2 / 10 4 .

[0107] Pin 1 of multiplier U6 is connected to pin 7 of the second control chip, output -Y1; pin 3 is connected to pin 7 of the second control chip, output -Y1; pins 2, 4, and 6 are grounded; pin 8 is connected to power supply VCC; pin 5 is connected to power supply VEE; pin 7 output is Y1 2 / 10 4 .

[0108] Multiplier U7 pin 1 is connected to the third control chip pin 7 output - X2 2 Pin 3 is connected to the memristor voltage u; Pins 2, 4, and 6 are grounded; Pin 8 is connected to the power supply VCC; Pin 5 is connected to the power supply VEE; Pin 7 outputs -X2 2 u / 10 4 .

[0109] Multiplier U8 pin 1 is connected to the third control chip pin 8 output - Y2 2 Pin 3 is connected to the memristor voltage u; Pins 2, 4, and 6 are grounded; Pin 8 is connected to the power supply VCC; Pin 5 is connected to the power supply VEE; Pin 7 outputs -Y2 2 u / 10 4 .

[0110] The actual simulation test using Multisim is as follows:

[0111] Assume that the input voltage is u=Msin(2πft), M=1mV, f=1000Hz, the waveform and hysteresis curve of the memristor output are as follows: Figures 3-5 As shown, Figure 3 In the figure, the blue curve corresponds to the current i of the memristor. According to the oscilloscope's unit conversion of 1V / mA, the current i of the memristor is 0.01mA at this time.

[0112] like Figure 4 As shown, the present invention meets the basic properties of a locally active memristor, has an 8-shaped hysteresis curve and a local active domain, can produce complex dynamic behaviors, and can be applied to the research and design of neuron circuits.

[0113] As Figure 5 shown, increasing the input voltage frequency f=3000Hz of the memristor, the hysteresis area of the hysteresis curve of the memristor can be obviously reduced, and the hysteresis curve of the memristor will shrink into a straight line by continuously increasing the frequency.

[0114] The application designs a mathematical model based on a second-order local active memristor, and establishes a simulator model according to the mathematical model, the simulator model contains three integrated operational amplifiers U1, U2 and U3, five multipliers U4, U5, U6, U7 and U8, and components resistors and capacitors used for connection, and realizes the volt-ampere characteristic of the second-order local active memristor through the simulator model. In the case that the actual memristor device cannot be obtained, the circuit design, experiment and application related to the memristor can be realized by replacing the actual memristor, and the application has important practical significance for the characteristic and application research of the memristor.

[0115] The application realizes the corresponding operation in the characteristic of the memristor by using integrated operational circuits and analog multipliers, wherein the integrated operational amplifier is mainly used to realize the inverse addition operation, integral operation and inverse amplifier of the voltage, and the analog multiplier is used to realize the product operation of the voltage. The voltage u of the memristor passes through the second inverse amplifier and the third inverse amplifier of the integrated operational amplifier U1 and the first integrator to obtain the internal state variable x of the memristor. After the voltage u passes through the first inverse amplifier of U1, the fourth inverse amplifier and the second integrator of the integrated operational amplifier U2 are used to obtain the internal state variable y of the memristor. After the internal state variables x and y pass through the inverse amplifiers of the integrated operational amplifiers U1 and U2 respectively, the product operation of the multiplier and the fifth inverse amplifier, the sixth inverse amplifier and the inverse adder of the integrated operational amplifier U3 are used to obtain the current i of the memristor.

[0116] Those skilled in the art should recognize that the above embodiments are only used to verify the application, and are not as a limitation of the application, as long as the changes and deformation of the above embodiments are within the scope of the application, and will fall within the protection scope of the application.

Claims

1. A simulator model based on a second-order locally active memristor, characterized by: Based on the mathematical model of the second-order local active memristor, a simulator model is constructed. The mathematical model based on the second-order local active memristor is as follows: ； Where i and u are the current and voltage of the memristor, x and y are the state variables of the memristor, and t is the corresponding time point; The simulator model includes integrated operational amplifier U1, integrated operational amplifier U2, integrated operational amplifier U3, multipliers U4, U5, U6, U7, U8 and components resistors and capacitors. The integrated operational amplifier U1 is used to implement inverting addition operation, inverting amplification operation and integration operation, which includes a first control chip, resistors R1-R9, and a capacitor C1. Pins 1, 2, and 3 of the first control chip and resistors R1 and R2 constitute a first inverting amplifier, pins 12, 13, and 14 of the first control chip and resistors R3, R4, and R5 and capacitor C1 constitute a first integrator, pins 5, 6, and 7 of the first control chip and resistors R6 and R7 constitute a second inverting amplifier, and pins 8, 9, and 10 of the first control chip and resistors R8 and R9 constitute a third inverting amplifier, wherein pin 1 outputs voltage -u, pin 7 outputs -X1, pin 8 outputs X1, and pin 14 outputs the internal state variable x of the memristor; The integrated operational amplifier U2 is used to implement inverting addition, inverting amplification, and integration operations. It includes a second control chip, resistors R10-13, and a capacitor C2. Pins 1, 2, and 3 of the second control chip, resistors R10, R11, and capacitor C2 form a second integrator. Pins 5, 6, and 7 of the second control chip, and resistors R12 and R13 form a fourth inverting amplifier. Pin 1 outputs the internal state variable y of the memristor, and pin 7 outputs -Y1. The integrated operational amplifier U3 is used to implement inverting addition and inverting amplification operations. It includes a third control chip and resistors R14-R20. Pins 5, 6, and 7 of the third control chip and resistors R14 and R15 constitute a fifth inverting amplifier. Pins 8, 9, and 10 of the third control chip and resistors R16 and R17 constitute a sixth inverting amplifier. Pins 1, 2, and 3 of the third control chip and resistors R18, R19, and R20 constitute an inverting adder. Pin 7 outputs -X2 2 , Pin 8 Output - Y2 2 , pin 1 output is the memristor current i; The multipliers U4, U5, U6, U7 and U8 are used to implement signal multiplication operations. The multiplier U4 is used to realize the voltage u1 pin 9 1-9 and U2 pin 7 voltage u 2-7 The voltage at the output terminal W of the multiplier U4 is: ； The multiplier U5 is used to realize the voltage u1 pin 7 1-7 The voltage at the output terminal W of the multiplier U5 is: ； The multiplier U6 is used to realize the voltage u at pin 7 of U2 2-7 The voltage at the output terminal W of the multiplier U6 is: ； The multiplier U7 is used to realize the input voltage u and the voltage u of U3 pin 7 3-7 The voltage at the output terminal W of the multiplier U7 is: ； The multiplier U8 is used to realize the input voltage u and the voltage u at pin 8 of U3. 3-8 The voltage at the output terminal W of the multiplier U7 is: 。 2. The simulator model based on the second-order local active memristor according to claim 1, characterized in that: The first control chip in the integrated operational amplifier U1 adopts TL084, pin 1 is connected to pin 2 through resistor R2; pin 2 is connected to the memristor voltage u through resistor R1, pin 3 is grounded; pin 5 is grounded; pin 6 is connected to pin 14 through resistor R6; pin 7 is connected to pin 6 through resistor R7; pin 8 is connected to pin 9 through resistor R9; pin 9 is connected to pin 7 through resistor R8; pin 10 is grounded; pin 12 is grounded; pin 13 is connected to pin 14 and multiplier U4 output -X1Y1 / 10 through resistor R3, resistor R4 and resistor R5 respectively. 4 , pin 1; pin 14 is connected to pin 13 through capacitor C1; pin 4 is connected to power supply VCC; pin 11 is connected to power supply VEE.

3. The simulator model based on the second-order local active memristor according to claim 1, characterized in that: The second control chip in the integrated operational amplifier U2 adopts TL084, pin 1 is connected to pin 2 through capacitor C2; pin 2 is connected to pin 1 and the first control chip pin 1 output -u through resistors R10 and R11 respectively; pin 3 is grounded; pin 5 is grounded; pin 6 is connected to pin 1 through resistor R12; pin 7 is connected to pin 6 through resistor R13; pin 4 is connected to power supply VCC; pin 11 is connected to power supply VEE.

4. The simulator model based on the second-order local active memristor according to claim 1, characterized in that: The third control chip in the integrated operational amplifier U3 adopts TL084, and pin 6 is connected to the output X1 of the multiplier U5 through the resistor R14. 2 / 10 4 Pin 7 is connected to pin 6 through resistor R15; Pin 9 is connected to multiplier U6 output Y1 through resistor R16 2 / 10 4 Pin 8 is connected to pin 9 through resistor R17; Pin 2 is connected to multiplier U7 output -X2 through resistors R18 and R19 respectively 2 u / 10 4 and multiplier U8 output - Y2 2 u / 10 4 Also includes a resistor R21, pin 1 is connected to pin 2 and the memristor current i through resistors R20 and R21 respectively; pin 3 and pin 5 are grounded; pin 4 is connected to the power supply VCC; pin 11 is connected to the power supply VEE.

5. The simulator model based on the second-order local active memristor according to claim 1, characterized in that: The multiplier U4 is controlled by an AD633 chip. Pin 1 of the multiplier U4 is connected to pin 8 of the first control chip to output X1; pin 3 is connected to pin 7 of the second control chip to output -Y1; pins 2, 4, and 6 are grounded; pin 8 is connected to the power supply VCC; pin 5 is connected to the power supply VEE; and pin 7 outputs -X1Y1 / 10. 4 .

6. The simulator model based on the second-order local active memristor according to claim 1, characterized in that: The multiplier U5 is controlled by the AD633 chip. Pin 1 of the multiplier U5 is connected to pin 8 of the first control chip to output X1; pin 3 is connected to pin 8 of the first control chip to output X1; pins 2, 4, and 6 are grounded; pin 8 is connected to the power supply VCC; pin 5 is connected to the power supply VEE; and pin 7 outputs X1. 2 / 10 4 .

7. The simulator model based on the second-order local active memristor according to claim 1, characterized in that: The multiplier U6 is controlled by the AD633 chip. Pin 1 of the multiplier U6 is connected to the pin 7 output of the second control chip -Y1; pin 3 is connected to the pin 7 output of the second control chip -Y1; pins 2, 4, and 6 are grounded; pin 8 is connected to the power supply VCC; pin 5 is connected to the power supply VEE; and pin 7 output is Y1 2 / 10 4 .

8. The simulator model based on the second-order local active memristor according to claim 1, characterized in that: The multiplier U7 is controlled by the AD633 chip, and the pin 1 of the multiplier U7 is connected to the pin 7 output of the third control chip -X2 2 Pin 3 is connected to the memristor voltage u; Pins 2, 4, and 6 are grounded; Pin 8 is connected to the power supply VCC; Pin 5 is connected to the power supply VEE; Pin 7 outputs -X2 2 u / 10 4 .

9. The simulator model based on the second-order local active memristor according to claim 1, characterized in that: The multiplier U8 is controlled by an AD633 chip, and the pin 1 of the multiplier U8 is connected to the pin 8 output of the third control chip -Y2 2 Pin 3 is connected to the memristor voltage u; Pins 2, 4, and 6 are grounded; Pin 8 is connected to the power supply VCC; Pin 5 is connected to the power supply VEE; Pin 7 outputs -Y2 2 u / 10 4 .

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