Formation method of semiconductor metal interconnection layer
By forming an initial metal layer in the semiconductor metal interconnect layer and performing thermal annealing treatment, the micro-void problem is solved, a void-free interconnect metal layer is formed, and the filling capacity and anti-electromigration performance are improved, which is suitable for modern semiconductor manufacturing.
Patent Information
- Application Number
- CN202510849438.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-23
- Publication Date
- 2025-09-12
AI Technical Summary
In the prior art, micro-voids exist in the metal interconnect layer of semiconductors, which leads to problems of early failure of metal connections and insufficient anti-electromigration capability.
By forming an initial metal layer in the through-hole and performing thermal annealing, microvoids are gathered and migrated to the surface, and then a second metal layer is formed and planarized to ensure that there are no microvoids in the interconnected metal layer. A combination of electrochemical deposition and thermal annealing is used to improve filling capacity and anti-electromigration performance.
It realizes an interconnected metal layer without micro-voids, significantly improves the filling capability and anti-electromigration capability, and is suitable for a wide range of applications in modern semiconductor manufacturing.
Smart Images
Figure CN120637320A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a method for forming a semiconductor metal interconnection layer. Background Art
[0002] As the feature size of integrated circuits decreases and the integration density increases, the proportion of back-end metal connections in the chip has gradually increased. Since the introduction of the Damascus process at the 180nm node, copper has replaced aluminum as the mainstream material for metal connections due to its excellent resistivity and anti-electromigration performance.
[0003] With the advancement of semiconductor technology, electrochemical plating (ECP) has replaced physical vapor deposition (PVD) as the preferred process for copper interconnects due to its excellent filling capability for high aspect ratio structures.
[0004] However, with the continuous advancement of technology nodes, the seed layer is distributed on the sidewalls and bottom of the through-hole, which is prone to seam problems during the first copper electroplating step. These micro-voids are concentrated at the top of the through-hole axis. These micro-voids may be caused by the contact interface of the grains during the electroplating process and cannot be eliminated during the final thermal annealing process. They often become weak points for electromigration and cause early failure of the metal connection.
[0005] Therefore, how to improve the formation quality of the back-end metal connections is a technical problem that urgently needs to be solved. Summary of the Invention
[0006] The technical problem solved by the present invention is to provide a method for forming a semiconductor metal interconnection layer, ensuring that there are no micropores in the interconnection metal layer, improving the filling capacity of the interconnection metal layer, and significantly improving the corresponding anti-electromigration ability, and having a wider range of applications.
[0007] To solve the above problems, the present invention provides a method for forming a semiconductor metal interconnect layer, comprising the following steps: providing a front layer, wherein the front layer has a metal conductive layer; forming a dielectric layer on the surface of the front layer; forming a through hole to be filled and an upper metal groove in the dielectric layer, wherein the upper metal groove is connected to the through hole, and the bottom of the through hole exposes the top surface of the metal conductive layer; forming a metal seed layer on the sidewall and bottom surfaces of the through hole and the sidewall surface of the upper metal groove; forming an initial metal layer on the surface of the metal seed layer in the through hole, wherein the initial metal layer grows from the sidewall and bottom of the through hole toward the center of the through hole and contacts the surface of the initial metal layer to form a first metal layer in the through hole; performing a thermal annealing treatment on the first metal layer; and after the thermal annealing treatment, further comprising: forming a second metal layer on the surface of the first metal layer, the surface of the metal seed layer on the surface of the upper metal groove, and the surface of the dielectric layer; planarizing the second metal layer until the surface of the dielectric layer is exposed, and forming an interconnect metal layer in the through hole and the upper metal groove.
[0008] Optionally, the process temperature of the thermal annealing treatment ranges from 200° C. to 250° C., the thermal annealing treatment time ranges from 0.5 hour to 1 hour, and the process temperature of the thermal annealing treatment adopts a gradient temperature increase.
[0009] Optionally, the first metal layer and the second metal layer are formed by electrochemical deposition.
[0010] Optionally, the first metal layer, the second metal layer and the thermal annealing treatment are performed in the same machine.
[0011] Optionally, the electrochemical deposition is performed using an electrochemical deposition machine, wherein the electrochemical deposition machine has a chamber for thermal annealing treatment.
[0012] Optionally, before forming the initial metal layer, the method further includes: forming a barrier layer on the bottom and sidewall surfaces of the through hole and the sidewall surface of the upper metal groove.
[0013] Optionally, the material of the metal seed layer is the same as the material of the interconnect metal layer, and the material of the interconnect metal layer includes copper, titanium, platinum, tungsten, ruthenium, and cobalt.
[0014] Optionally, the process for forming the through hole is a Damascus process.
[0015] Compared with the prior art, the technical solution of the present invention has the following advantages:
[0016] The method for forming a semiconductor metal interconnection layer of the present invention includes providing a front layer, wherein the front layer has a metal conductive layer; forming a dielectric layer on the surface of the front layer; forming a through hole to be filled and an upper metal groove in the dielectric layer, wherein the upper metal groove is connected to the through hole, and the bottom of the through hole exposes the top surface of the metal conductive layer; forming a metal seed layer on the side wall and bottom surface of the through hole and the side wall surface of the upper metal groove; forming an initial metal layer on the surface of the metal seed layer in the through hole, wherein the initial metal layer grows from the side wall and the bottom of the through hole toward the center of the through hole, contacts with each other from the surface of the initial metal layer, and forms a first metal layer in the through hole; performing a thermal annealing treatment on the first metal layer, and after the thermal annealing treatment, further comprising: A second metal layer is formed on the surface of the metal layer, the surface of the metal seed layer on the surface of the upper metal groove, and the surface of the dielectric layer. The second metal layer is flattened to expose the surface of the dielectric layer, and an interconnected metal layer is formed in the through hole and the upper metal groove. In the process of forming the first metal layer in the through hole, micro-holes are distributed along the central axis of the through hole and close to the top surface of the through hole in the first metal layer. After thermal annealing, the micro-holes gather and migrate to the surface of the first metal layer. There are no micro-holes inside the first metal layer. After the second metal layer is formed, it is flattened to form an interconnected metal layer, and finally it is ensured that there are no micro-holes in the interconnected metal layer, thereby improving the filling capacity of the interconnected metal layer and the corresponding anti-electromigration ability is significantly improved, and it has a wider range of applications. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] Figure 1 It is a schematic diagram of the structure of a semiconductor metal interconnect layer before chemical mechanical polishing;
[0018] Figure 2 yes Figure 1 TEM image of the failed sample after electromigration testing;
[0019] Figures 3 to 10 This is a structural schematic diagram of a process for forming a semiconductor metal interconnect layer according to an embodiment of the present invention;
[0020] Figure 11 TEM image of a semiconductor metal interconnection layer in one embodiment of the present invention. DETAILED DESCRIPTION
[0021] The formation quality of back-end metal connections in the prior art still needs to be improved.
[0022] First, please refer to Figure 1A semiconductor metal interconnection layer includes a front layer 100; a metal conductive layer 101 located on the front layer 100; a dielectric layer 102 located on the surface of the front layer, the dielectric layer 102 having a through hole 103 and an upper metal groove 105 connected to the through hole 103; an interconnection metal layer 104 located in the through hole 103 and the upper metal groove 105, the bottom of the interconnection metal layer 104 in the through hole 103 contacts the top surface of the metal conductive layer 101.
[0023] The inventors have found that there are a large number of micro holes in the interconnection metal layer of the semiconductor metal interconnection layer (please refer to Figure 1 and Figure 2 The circled part), and the interconnection metal layer is difficult to fill the through hole, and there are a large number of micro holes in the interconnection metal layer, which affects the anti-electromigration performance of the interconnection metal layer and limits the use of semiconductor metal interconnection layers to a certain extent.
[0024] After research, the inventor provides a method for forming a semiconductor metal interconnection layer, comprising providing a front layer, wherein the front layer has a metal conductive layer; forming a dielectric layer on the surface of the front layer; forming a through hole to be filled and an upper metal groove in the dielectric layer, wherein the upper metal groove is connected to the through hole, and the bottom of the through hole exposes the top surface of the metal conductive layer; forming a metal seed layer on the side wall and bottom surface of the through hole and the side wall surface of the upper metal groove; forming an initial metal layer on the surface of the metal seed layer in the through hole, wherein the initial metal layer grows from the side wall and the bottom of the through hole toward the center of the through hole, contacts with the surface of the initial metal layer, and forms a first metal layer in the through hole; performing thermal annealing on the first metal layer; and after the thermal annealing, further comprising: A second metal layer is formed on the surface of the first metal layer, the surface of the metal seed layer on the surface of the upper metal groove, and the surface of the dielectric layer. The second metal layer is flattened to expose the surface of the dielectric layer, and an interconnected metal layer is formed in the through hole and the upper metal groove. In the process of forming the first metal layer in the through hole, micro-holes are distributed along the central axis of the through hole and close to the top surface of the through hole in the first metal layer. After thermal annealing, the micro-holes gather and migrate to the surface of the first metal layer. There are no micro-holes inside the first metal layer. After the second metal layer is formed, it is flattened to form an interconnected metal layer, and finally it is ensured that there are no micro-holes in the interconnected metal layer, thereby improving the filling capacity of the interconnected metal layer and significantly improving the corresponding anti-electromigration ability. It has a wider range of applications.
[0025] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.
[0026] First, please refer to Figure 3 , providing a front layer 200, wherein the front layer 200 has a metal conductive layer 201.
[0027] In this embodiment, the front layer 200 includes the front-end process from providing a substrate to forming a logic device. The front layer 200 can start from forming the first zero-layer (M0) interconnection layer, or can start from forming the n-th layer (Mn) interconnection layer, and can be designed according to actual process requirements.
[0028] In this embodiment, the metal conductive layer 201 provides a stable electrical basis for the subsequently formed semiconductor metal interconnection layer. The metal conductive layer 201 can serve as a conductive channel for the subsequent interconnection structure to ensure that current can be effectively transmitted while improving the conductivity and stability of the semiconductor metal interconnection layer.
[0029] Please refer to Figure 4 , forming a dielectric layer 202 on the surface of the front layer 200 .
[0030] In this embodiment, the dielectric layer 202 is made of silicon oxide.
[0031] In some embodiments, the material of the dielectric layer 202 may also be silicon nitride, silicon carbide, silicon carbide nitride, etc.
[0032] In this embodiment, the dielectric layer 202 plays an insulating and isolating role, preventing short circuits between different metal conductive layers 201 or metal layers, thereby improving the reliability and stability of the semiconductor metal interconnect layer. At the same time, the dielectric layer 202 can also reduce parasitic capacitance.
[0033] Please refer to Figure 5 A through hole 203a to be filled and an upper metal groove 203b are formed in the dielectric layer 202, the bottom of the upper metal groove 203b is connected to the top of the through hole 203a, and the bottom of the through hole 203a exposes the top surface of the metal conductive layer 201.
[0034] In the figure, dotted lines are used to separate the through holes to be filled and the upper metal grooves for easy identification.
[0035] In this embodiment, the through hole 203a is formed by the Damascus process. The Damascus process can achieve high-precision and high-density production of the through hole 203a, providing a good foundation for the subsequent filling of the interconnection metal layer, thereby meeting the development needs of miniaturization and high performance of modern semiconductor metal interconnection layers.
[0036] In this embodiment, the through hole 203a provides a channel for subsequent metal interconnection, ensuring that current can be transmitted from the metal conductive layer 201 to the subsequent interconnected metal layer, realizing electrical connection between different levels, and improving the integration and performance of the semiconductor metal interconnection layer.
[0037] In this embodiment, a barrier layer 204 is formed on the bottom and sidewall surfaces of the through hole 203 a and the sidewall surfaces of the upper metal trench 203 b .
[0038] In this embodiment, the barrier layer 204 can effectively prevent adverse reactions, such as diffusion or chemical reactions, between the interconnect metal layer and the dielectric layer 202 or the front layer 200, thereby improving the adhesion and stability of the interconnect metal layer. Furthermore, the barrier layer 204 can provide better electrical conductivity and oxidation resistance, thereby extending the service life of the device.
[0039] Please refer to Figure 6 A metal seed layer 205 is formed on the sidewalls and bottom surfaces of the through hole 203 a and the sidewall surfaces of the upper metal groove 203 b .
[0040] Specifically, the metal seed layer 205 is formed on the surface of the barrier layer 204 .
[0041] In this embodiment, the metal seed layer 205 is made of copper.
[0042] In some embodiments, the material of the metal seed layer 205 may also be titanium, tungsten, ruthenium, cobalt, etc.
[0043] Please refer to Figure 7 An initial metal layer is formed on the surface of the metal seed layer 205 on the side walls and bottom surfaces of the through hole 203a. The initial metal layer grows from the side walls and the bottom of the through hole 203a toward the center of the through hole 203a, and the surfaces of the initial metal layers come into contact with each other to form a first metal layer 206 in the through hole 203a.
[0044] In this embodiment, the first metal layer 206 is formed by electrochemical deposition.
[0045] In this embodiment, an electrochemical deposition machine is used to perform the electrochemical deposition to form the first metal layer 206 . The electrochemical deposition machine has a chamber for thermal annealing treatment.
[0046] In this embodiment, an electrochemical deposition method is used to form an initial metal layer on the surface of the metal seed layer 205, allowing the initial metal layer to grow along the side walls and bottom of the through hole 203a toward the center of the through hole 203a, and converge at the surface to form the first metal layer 206, thereby preliminarily realizing the metal layer filling in the through hole 203a.
[0047] Figure 7 The tiny circles represent micropores.
[0048] In this embodiment, micro-holes 209 exist in the first metal layer 206 and are distributed along the central axis of the through-hole 203 a and close to the top surface of the through-hole 203 a.
[0049] Please refer to Figure 8 , performing thermal annealing treatment on the first metal layer 206.
[0050] The arrowed lines in the figure represent thermal annealing treatment.
[0051] In this embodiment, the thermal annealing process is performed in a chamber of the electrochemical deposition machine.
[0052] In this embodiment, the process temperature range of the thermal annealing treatment is 200°C to 250°C, and the thermal annealing treatment time range is 0.5 hour to 1 hour. The process temperature of the thermal annealing treatment adopts a gradient temperature increase, which helps to improve the crystal structure of the metal layer, reduce the resistivity, and enhance the adhesion between the metal layer and the dielectric layer 202 or the front layer 200, playing a key role in improving the performance of the interconnection metal layer.
[0053] In this embodiment, the gradient temperature increase can reduce thermal stress and improve the uniformity and stability of the first metal layer 206 .
[0054] In this embodiment, during the thermal annealing treatment, the metal atoms in the first metal layer 206 obtain sufficient thermal energy, the thermal motion of the atoms becomes more intense, the atoms can overcome the constraints of the lattice, diffuse and rearrange in the lattice, change the original crystal orientation, and repair the lattice, so that the micropores 209 in the first metal layer 206 can be transferred to the surface of the first metal layer 206, thereby helping to eliminate the micropores inside the first metal layer 206.
[0055] In this embodiment, the gradient temperature increase thermal annealing process can make the metal layer more regularly arranged and more fully filled within the through hole 203a, helping to reduce the increase in local resistance caused by microvoids and improve signal transmission. In addition, the gradient temperature increase allows the interface between the first metal layer 206 and the dielectric layer 202 to gradually adapt to temperature changes, reducing the interfacial stress concentration caused by differences in thermal expansion coefficients. This helps to improve the bonding strength between the first metal layer 206 and the dielectric layer 202, reduce the risk of delamination and peeling at the interface, and improve the stability and reliability of the through hole 203a structure.
[0056] Please refer to Figure 9After the thermal annealing treatment, the method further includes forming a second metal layer 207 on the surface of the first metal layer 206 , the surface of the metal seed layer 205 on the sidewall surface of the upper metal groove 203 b , and the surface of the dielectric layer 202 .
[0057] In this embodiment, the second metal layer 207 is formed by an electrochemical deposition process.
[0058] In this embodiment, the material of the second metal layer 207 is the same as that of the first metal layer 206 .
[0059] In this embodiment, the first metal layer 206, the second metal layer 207 and the thermal annealing treatment are all performed in the same machine, which reduces the number of transfers and cleanings between equipment, reduces the risk of contamination, improves production efficiency and product yield, and ensures the stability of the performance and quality of the first metal layer 206 and the second metal layer 207.
[0060] In this embodiment, the first metal layer 206 and the second metal layer 207 are formed by an electrochemical deposition process, which can accurately control the thickness and composition of the first metal layer 206 and the second metal layer 207, thereby improving the performance and reliability of the first metal layer 206 and the second metal layer 207.
[0061] Please refer to Figure 10 The second metal layer 207 is planarized until the surface of the dielectric layer 202 is exposed, and an interconnection metal layer 208 is formed in the through hole 203a and the upper metal groove 203b.
[0062] In this embodiment, before forming the second metal layer 207, after forming the first metal layer 206, the first metal layer 206 is first subjected to the thermal annealing treatment. The micro-voids distributed along the central axis of the through-hole 203a and close to the top surface of the through-hole 203a in the first metal layer 206 are gathered and migrated to the top surface of the first metal layer 206 through the thermal annealing treatment. As a result, no micro-voids are present in the first metal layer 206. In this way, after forming the second metal layer 207, planarization is performed to form the interconnection metal layer 208, and finally, it is ensured that there are no micro-voids in the interconnection metal layer 208 (please refer to reference). Figure 10 and Figure 11 ), the filling capacity of the interconnect metal layer 208 is improved, and the corresponding anti-electromigration capability is significantly improved, and it has a wider range of applications.
[0063] It should be noted that, generally, after the surface of the dielectric layer 202 is exposed, it is still necessary to continue polishing, so that the interconnect metal layer 208 and the top surface of the dielectric layer have a certain loss.
[0064] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.
Claims
1. A method for forming a semiconductor metal interconnection layer, characterized in that: Including steps: providing a front layer, wherein the front layer has a metal conductive layer therein; forming a dielectric layer on the surface of the front layer; forming a through hole to be filled and an upper metal groove in the dielectric layer, wherein the upper metal groove is connected to the through hole, and the bottom of the through hole exposes the top surface of the metal conductive layer; forming a metal seed layer on the sidewall and bottom surface of the through hole and the sidewall surface of the upper metal groove; forming an initial metal layer on the surface of the metal seed layer in the through hole, wherein the initial metal layer grows from the sidewalls and the bottom of the through hole toward the center of the through hole, and the surfaces of the initial metal layers come into contact with each other to form a first metal layer in the through hole; performing a thermal annealing treatment on the first metal layer; After the thermal annealing treatment is performed, the method further includes: forming a second metal layer on the surface of the first metal layer, the surface of the metal seed layer on the surface of the upper metal groove, and the surface of the dielectric layer; The second metal layer is planarized until the surface of the dielectric layer is exposed, and an interconnected metal layer is formed in the through hole and the upper metal groove.
2. The method for forming a semiconductor metal interconnection layer according to claim 1, wherein: The process temperature of the thermal annealing treatment is in the range of 200° C. to 250° C., the thermal annealing treatment time is in the range of 0.5 hour to 1 hour, and the process temperature of the thermal annealing treatment is increased in a gradient manner.
3. The method for forming a semiconductor metal interconnection layer according to claim 1, wherein: The first metal layer and the second metal layer are formed by electrochemical deposition.
4. The method for forming a semiconductor metal interconnection layer according to claim 3, wherein: The first metal layer, the second metal layer, and the thermal annealing process are performed in the same machine.
5. The method for forming a semiconductor metal interconnection layer according to claim 3, wherein: The electrochemical deposition is performed using an electrochemical deposition machine, which has a chamber for thermal annealing treatment.
6. The method for forming a semiconductor metal interconnection layer according to claim 1, wherein: Before forming the initial metal layer, the method further includes: forming a barrier layer on the bottom and sidewall surfaces of the through hole and the sidewall surface of the upper metal groove.
7. The method for forming a semiconductor metal interconnection layer according to claim 1, wherein: The material of the metal seed layer is the same as that of the interconnection metal layer, and the material of the interconnection metal layer includes copper, titanium, platinum, tungsten, ruthenium, and cobalt.
8. The method for forming a semiconductor metal interconnection layer according to claim 1, wherein: The process for forming the through hole is a Damascus process.