An automatic current-sharing control method for interleaved parallel BUCK converters

Abstract

The application discloses an automatic current sharing control method of an interleaved parallel BUCK converter, and belongs to the technical field of power electronics, and comprises the following steps: S1, acquiring an output voltage of a load end of the interleaved parallel BUCK converter, and a given output voltage; acquiring a current of each phase inductor; S2, acquiring an average value of the inductor current of each phase, and taking an average value of the average value of the inductor current of each phase as a reference value of a current loop; S3, calculating a duty cycle signal through the current loop; S4, calculating a duty cycle signal through a voltage loop; and S5, superimposing the duty cycle signal calculated by each phase current loop with the duty cycle signal calculated by the voltage loop, etc. The application makes the inductor current of each phase follow the average inductor current of three phases in real time, realizes high-precision current sharing control, improves the reliability of control, and thus controls the output current at an average level.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of power electronics, and particularly relates to an automatic current sharing control method for an interleaved parallel BUCK converter. BACKGROUND

[0002] With the rapid development of the electric vehicle industry, the development potential of high-power and high-efficiency switching power supply is huge, and the market demand is also increasing. A simple single-phase DC-DC converter has a large output ripple, and cannot meet the requirements in high-power, high-efficiency and high-performance application occasions. The interleaved parallel structure of the multi-phase parallel BUCK converter solves the problem of large output ripple, improves the output quality of the converter, speeds up the dynamic response of the converter, and reduces the size of the magnetic element.

[0003] In actual production, the actual values of inductance elements cannot be completely the same, and there are parasitic parameters, which directly lead to the fact that the parameters of each phase of the interleaved parallel converter are not completely symmetrical, and the switching tube devices have different internal resistances. Based on the above reasons, the interleaved parallel converter has the problem of imbalance between phases. Under this problem, the long-term work of the converter will affect the service life of the device and the low output quality. The current sharing control methods currently mainly include master-slave current sharing method, maximum current method, and output impedance method. The maximum current method is more dependent on the accuracy of current sampling, which may lead to poor current sharing effect; when the master phase of the master-slave current sharing method fails, the current sharing of the entire system is no longer stable; the output impedance method is affected by the parameters and parasitic parameters of the elements, and when the parameter difference is large, the current sharing effect is poor.

[0004] A Chinese patent application with the patent application number CN202410491023.0 and the name of an interleaved parallel buck converter and a current sharing control method thereof discloses a current sharing control method for an interleaved parallel BUCK converter, which uses the method of superimposing the duty cycle generated by the peak voltage difference of adjacent phases and the duty cycle generated by the voltage loop, which is equivalent to the current level of the latter phase following the current level of the former phase, to realize the current sharing control of the interleaved parallel BUCK converter. However, the current sharing control method has the problem that when the parasitic parameter of the mth phase is small and the parasitic parameter of the m+1th phase is large, the inductance current level difference of the two phases is large, and the inductance current of the m+1th phase needs to be increased a lot to follow the mth phase current, the inductance current of the m+2th phase follows the original inductance current of the m+1th phase, and the inductance current difference of the phases will be further widened, and the current sharing effect will be very poor. SUMMARY

[0005] In view of the above shortcomings and deficiencies of the prior art, the present application provides an automatic current sharing control method for an interleaved parallel BUCK converter, which makes the inductance current of each phase follow the average inductance current of the three phases in real time, realizes high-precision current sharing control, improves the reliability of control, and thus controls the output current at an average level.

[0006] To achieve the above object, the main technical scheme adopted by the present application comprises:

[0007] An automatic current sharing control method for interleaved parallel BUCK converter comprises the following steps:

[0008] Step S1, obtaining the output voltage of the load end of the interleaved parallel BUCK converter, and a given output voltage; obtaining the current of each phase inductor of the interleaved parallel BUCK converter;

[0009] Step S2, obtaining the average value of the inductor current of each phase BUCK converter in each sampling period, and adding the average values of the inductor currents of all phases to obtain the average value as the reference value of the current loop;

[0010] Step S3, inputting the difference between the average value of the inductor current of each phase and the reference value of the current loop into the current loop of each phase to calculate the duty cycle signal through the current loop;

[0011] Step S4, inputting the difference between the given output voltage and the voltage of the load end into the voltage loop of each phase to calculate the duty cycle signal through the voltage loop;

[0012] Step S5, superimposing the duty cycle signal calculated by each phase current loop with the duty cycle signal calculated by the voltage loop to obtain the duty cycle signal of each phase switching tube device;

[0013] Step S6, setting a carrier signal, comparing the duty cycle signal of each phase switching tube device with the carrier, and then generating the switching signal of each phase switching tube device through PWM modulation to realize current sharing of the phase current.

[0014] Further, in the step S2, the average value of the inductor current of each phase of the interleaved parallel BUCK converter is calculated according to the following formula:

[0015]

[0016] In the formula, I Lm is the average value of the inductor current of the mth phase, d m is the duty cycle of the mth phase switching tube device, i Lm (t) is the instantaneous value of the inductor current of the mth phase, T s is the switching period, and n is the total number of phases of the BUCK converter.

[0017] The reference value I ref of the current loop is calculated according to the following formula:

[0018]

[0019] Further, in the step S3, the difference between the average value of the inductor current of each phase and the reference value of the current loop is input into the PID regulator of the current loop of each phase.

[0020] Further, in the step S3, the duty cycle signal d im :

[0021]

[0022] d im is the duty cycle signal calculated by the mth phase current loop, G IPWM is the PWM modulation coefficient, G IPWM = 1, K Pi , K Ii are the proportional coefficient and the integral coefficient of the current loop PID controller respectively, and s is the Laplace operator.

[0023] Further, in the step S4, the difference between the given output voltage and the voltage of the load at the output end is input to the PID controller of the voltage loop.

[0024] Further, in the step S4, the voltage loop calculates the duty cycle signal according to the following formula:

[0025]

[0026] d u is the duty cycle signal calculated by the voltage loop, G UPWM is the voltage loop PWM modulation coefficient, U ref is the voltage loop reference value, K Pu , K Iu are the proportional coefficient and the integral coefficient of the voltage loop PID controller respectively, s is the Laplace operator, and U0 is the output voltage at the load end.

[0027] Further, in the step S5, the duty cycle signal d u calculated by the voltage loop is added to the duty cycle signal d im calculated by the mth phase current loop to obtain the modulated duty cycle signal d m of the mth phase, where 1≤m≤n, and n is the total number of phases of the BUCK converter.

[0028] Further, in the step S6, the method for generating the switching signal of the switching tube device of each phase by PWM modulation is as follows: when the duty cycle signal is greater than the carrier signal, output high level to drive the switching tube to turn on; when the duty cycle signal is less than the carrier signal, output low level to drive the switching tube to turn off.

[0029] The application has the beneficial effects that: the application adds a current sensor in the BUCK converter to collect the inductor current of each phase, takes the average value of the inductor current of each phase as the current reference value of the current loop, the voltage reference value of the voltage loop is given, the duty cycle signal after the operation of the current loop is superimposed with the duty cycle signal after the operation of the voltage loop to realize the inter-phase current sharing and output voltage stabilization control, without setting the master-slave module, the unbalanced current of each phase is followed in real time, and fast current sharing is realized.

[0030] The current sharing control method can make the inductor current of each phase close to the current loop reference current, and make the output current of each phase close to each other, so that the problem of imbalance of inter-phase inductor current is solved. BRIEF DESCRIPTION OF DRAWINGS

[0031] Figure 1 It is an automatic current sharing control method diagram of the interleaved parallel BUCK converter of the application.

[0032] Figure 2 It is a topology structure diagram of the interleaved parallel BUCK converter.

[0033] Figure 3 It is a topology structure diagram of the three-phase interleaved parallel BUCK converter in embodiment 1.

[0034] Figure 4 It is an automatic current sharing control block diagram of the three-phase interleaved parallel BUCK converter in embodiment 1.

[0035] Figure 5 It is the inductor current waveform of the three-phase interleaved parallel BUCK converter in embodiment 1 before current sharing control.

[0036] Figure 6 It is the inductor current waveform of the three-phase interleaved parallel BUCK converter in embodiment 1 after current sharing control.

[0037] Figure 7 It is the inductor current waveform diagram of the three-phase interleaved parallel BUCK converter in embodiment 1 in the 0.1s load mutation process.

[0038] Figure 8 It is the current waveform diagram of the three-phase interleaved parallel BUCK converter in embodiment 1 after load mutation. DETAILED DESCRIPTION

[0039] In order to better explain the application and facilitate understanding, the application is described in detail in combination with the drawings and specific embodiments.

[0040] The application provides an automatic current sharing control method for an interleaved parallel BUCK converter, and aims at solving the problem of imbalance of phase inductance current of the interleaved parallel BUCK converter. Figure 2 in o n L1 Ln L1 Ln o Co o Co n S1 Sn

[0041]

[0042] The application provides an automatic current sharing control method for an interleaved parallel BUCK converter, and aims at solving the problem of imbalance of phase inductance current of the interleaved parallel BUCK converter. Figure 1

[0043] Step S1, obtaining the output voltage of the above-mentioned interleaved parallel BUCK converter load end, given output voltage, and obtaining the phase inductance current through a current sensor;

[0044] ​​​​​​​​​​​​​​​​​Step S2, the average value of each phase BUCK converter inductor current is obtained in each sampling period, the average value of each phase inductor current is added and then averaged as the reference value of the current loop, the specific process is as follows:

[0045] The inductor current of each phase is sampled in the sampling period, and the average value of the inductor current of each phase is obtained after calculation, which is shown as follows:

[0046]

[0047] In the formula, I Lm is the average value of the inductor current of the mth phase, d m is the duty ratio of the mth phase switch tube device, i Lm (t) is the instantaneous value of the inductor current of the mth phase, T s is the switching period, and n is the total number of phases of the BUCK converter.

[0048] The average value of the inductor current of each phase is added and then averaged as the reference value I ref of the current loop, which is shown as follows:

[0049]

[0050] Step S3, the inductor current of each phase is subtracted from the reference value I ref of the current loop to obtain the current error signal of each phase current loop, and the error signal of the current loop is input to the PID regulator of the current loop to complete the corresponding PID compensation link, and the duty ratio signal of each phase is output, which is shown as follows:

[0051]

[0052] In the formula, d im is the duty ratio signal of the mth phase current loop, G IPWM is the PWM modulation coefficient, G IPWM =1, K Pi and K Ii are the proportional coefficient and integral coefficient of the current loop PID controller respectively, and s is the operator of Laplace transform.

[0053] Step S4, the difference between the given output voltage and the voltage of the output load is input to the PID controller of the voltage loop, the PID controller is adjusted, and the duty ratio signal after the voltage loop operation is output, which is shown as follows:

[0054]

[0055] In the formula, d u is the duty ratio signal of the voltage loop operation, G UPWM is the voltage loop PWM modulation coefficient, G UPWM =1, and Uref Kv Pu , K Iu are example proportional and integral coefficients of the voltage loop PID controller, s is the Laplace operator, U0 is the output voltage.

[0056] Step S5, the duty cycle signal d u of the voltage loop operation is added to the duty cycle signal d im of the mth phase current loop operation to obtain the modulated duty cycle signal d m of the mth phase, where 1≤m≤n, and n is the total number of phases of the BUCK converter.

[0057] Step S6, the carrier signal is set, where the angles of the carrier signals of each phase are different by n / 360°. After comparing the duty cycle signals of the switching tube devices of each phase with the carrier signals and then performing PWM modulation, the switching signals of the switching tube devices of each phase are generated to achieve current sharing of the phases.

[0058] Embodiment 1

[0059] Taking a three-phase interleaved parallel BUCK converter as an example, the topological structure diagram thereof is shown in Figure 3 , and the specific parameter settings are as follows: the input voltage Uin is 850V, the output voltage Uo is 750V, the inductance L1 is 2.98mH, the parasitic resistance R L1 of the inductance L1 is 0.06Ω, the inductance L2 is 3mH, the parasitic resistance R L2 of the inductance L2 is 0.07Ω, the inductance L3 is 3.02mH, the parasitic resistance R L3 of the inductance L3 is 0.05Ω, the parasitic resistance R S1 of the main switching tube S1 is 0.05Ω, the parasitic resistance R S2 of the main switching tube S2 is 0.06Ω, the parasitic resistance R S3 of the main switching tube S3 is 0.07Ω, the output capacitance C o is 1200μF, the parasitic resistance R o of the output capacitance C Co is 0.01Ω, the initial state output load R0 is 3.75Ω, the output load R0 is suddenly changed to 5Ω at 0.1s, and the switching frequency of the switching tube is 5kHz.

[0060] The automatic current sharing control block diagram of the three-phase interleaved parallel BUCK converter of this embodiment is shown in Figure 4 . In each current sampling period, the average values of the inductance currents of the three phases are obtained through discrete sampling of the three inductance currents, respectively. Then, the average value obtained by adding the average values of the three inductance currents is taken as the current reference value of the current loop. The current error signal obtained by subtracting the average values of the inductance currents of the three phases from the current reference value of the current loop is sent to the PID controller to obtain the duty cycle signals output by the three current loops after compensation. The expression is as follows:

[0061]

[0062] In the formula, d i1 , d i2 , d i3 are duty ratios of the first, second and third phase current loops respectively, G IPWM is a current loop PWM modulation coefficient, and G IPWM =1.

[0063] In each voltage sampling period, the error signal obtained by subtracting the given output voltage value from the discrete sampling of the output voltage value is sent to the PID controller for compensation to obtain the duty ratio signal of the voltage loop output, and the expression is as follows:

[0064]

[0065] In the formula, G UPWM is a voltage loop PWM modulation coefficient, and G UPWM =1.

[0066] The first phase carrier signal is set, the second and third phase carrier signals are delayed by 120° and 240° respectively, the duty ratio signal of the voltage loop output and the duty ratio signals of the three current loop outputs are superimposed and compared with the carrier signal, and then the switching signals of the switching tubes of each phase are generated through PWM modulation.

[0067] Through the above method, the large deviation of the phase inductance current is continuously corrected, the inductance current levels of each phase are close to each other, the output voltage level is stabilized, and good automatic current sharing effect is realized under the condition of imbalance of parameters among phases.

[0068] The inductance current waveform diagram of the three-phase interleaved parallel BUCK converter in the embodiment before current sharing control is as shown in Figure 5 .

[0069] The inductance current waveform diagram of the three-phase interleaved parallel BUCK converter in the embodiment after current sharing control is as shown in Figure 6 .

[0070] It can be seen from the comparison of Figure 5 and Figure 6 that the automatic current sharing control method of the interleaved parallel BUCK converter has good current sharing effect.

[0071] The inductance current waveform diagram of the three-phase interleaved parallel BUCK converter in the embodiment after load mutation is as shown in Figure 7 . It can be seen that the load is mutated at 0.1s, and under this disturbance, the three-phase interleaved parallel BUCK converter can still maintain good current sharing effect.

[0072] The automatic current sharing control method of the interleaved parallel BUCK converter provided in the embodiment has a simple control structure, reduces control cost to a certain extent, has strong anti-interference ability, fast response speed, and guarantees stable output of the system.

[0073] The double duty cycle control of the current sharing loop duty cycle and the voltage loop duty cycle is adopted in the embodiment, a master-slave module does not need to be set, fast current sharing can be realized, and the current sharing control is suitable for multi-module parallel in a high-power scene.

[0074] The above merely describes the preferred embodiments of the present application, but the protection scope of the present application is not limited thereto, any changes or replacements within the technical range disclosed in the present application can be easily thought of by any person skilled in the art, and all are covered within the protection scope of the present application.

Claims

1. An automatic current sharing control method for an interleaved parallel BUCK converter, characterized in that, Includes the following steps: Step S1: Obtain the output voltage at the load end of the interleaved parallel BUCK converter, given the output voltage; obtain the current of each phase inductor of the interleaved parallel BUCK converter; Step S2: Obtain the average value of the inductor current of each phase of the BUCK converter in each sampling period, add up the average values ​​of the inductor current of each phase, and take the average value as the reference value of the current loop. Step S3: Input the difference between the average value of the inductor current of each phase and the reference value of the current loop into the current loop of each phase, and calculate the duty cycle signal through the current loop; Step S4: Input the difference between the given output voltage and the voltage of the output load into each phase voltage loop, and calculate the duty cycle signal through the voltage loop; Step S5: The duty cycle signal of each phase current loop operation is superimposed with the duty cycle signal of the voltage loop operation to obtain the duty cycle signal of each phase switching device. Step S6: Set the carrier signal, compare the duty cycle signal of each phase switching device with the carrier, and then generate the switching signal of each phase switching device through PWM modulation to achieve phase current sharing. In step S2, the average inductor current of each phase of the interleaved parallel BUCK converter is calculated using the following formula: ； In the formula, Let m be the average inductor current of the m-th phase. Let m be the duty cycle of the switch device in phase m. This represents the instantaneous value of the inductor current in phase m. For the switching cycle, n This represents the total number of phases in the BUCK converter. Current loop reference value Calculate using the following formula: ； In step S3, the difference between the average value of the inductor current of each phase and the reference value of the current loop is input to the PID controller of the current loop of each phase. In step S3, the duty cycle signal of each phase is calculated by the current loop using the following formula. : ； In the formula: This is the duty cycle signal for the current loop operation of the m-th phase. For PWM modulation coefficients, , These are the proportional and integral coefficients of the current loop PID controller, respectively, and s is the Laplace transform operator; In step S4, the difference between the given output voltage and the voltage of the output load is input to the PID controller of the voltage loop. In step S4, the voltage loop calculates the duty cycle signal using the following formula: ； In the formula: This is the duty cycle signal for voltage loop operations. For voltage loop PWM modulation coefficients, This is the voltage loop reference value. , These are the proportional and integral coefficients of the voltage loop PID controller, respectively, and s is the Laplace transform operator. U 0 This is the output voltage at the load end.

2. The automatic current sharing control method for an interleaved parallel BUCK converter according to claim 1, characterized in that: In step S5, the duty cycle signal of the voltage loop operation is... Duty cycle signal of the m-th phase current loop operation The summation yields the duty cycle signal modulated by the m-th phase. , where 1≤m≤n, and n is the total number of phases of the BUCK converter.

3. The automatic current sharing control method for an interleaved parallel BUCK converter according to claim 1, characterized in that: In step S6, the method for generating the switching signals of each phase switching device using PWM modulation is as follows: when the duty cycle signal is greater than the carrier signal, a high level is output to drive the switching device to turn on; when the duty cycle signal is less than the carrier signal, a low level is output to drive the switching device to turn off.

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