Variable narrow pulse and high PRF control system and method based on microprocessor

Abstract

The invention discloses a variable narrow pulse and high PRF control system and method based on a microprocessor, the system comprises a master control ARM core module, a clock module and a timer module, the clock module and the timer module are respectively connected with the master control ARM core module, the timer module comprises at least two cascaded hardware timers, and the hardware timers are connected with the master control ARM core module. Wherein the first timer TIM5 is configured as a master mode timer, and the second timer TIM2 is configured as a slave mode timer; the trigger output end of the master mode timer is connected with the trigger input end of the slave mode timer to form a timer linkage structure; the master mode timer is configured to control pulse repetition frequency PRF, and the slave mode timer is configured to control pulse width; the clock module serves as a timer reference clock source through frequency multiplication of a phase-locked loop. The system can support generation of ultra-narrow pulses, output ultra-narrow pulses are small in width jitter, the pulse width can be adjusted, the cost is reduced, the size is small, modularization is achieved, and commercial integration application is facilitated.

Description

Technical Field

[0001] The present invention relates to the technical field of ultrasonic signal processing, in particular to a microprocessor-based variable narrow pulse and high PRF control system and method. Background Art

[0002] There are various methods to generate ultrasonic excitation pulses, and the pulse width and pulse repetition frequency (PRF) can be adjusted through different technologies.

[0003] 1. Use devices such as arbitrary waveform generators (AWGs) and direct digital synthesis (DDS) technology to generate arbitrary waveforms. The pulse width can be adjusted through software, and the pulse interval (PRF) can be adjusted in real time through programming.

[0004] 2. Use an avalanche transistor pulse circuit. The principle is to use the avalanche breakdown effect to generate nanosecond narrow pulses. The pulse width can be adjusted by adjusting the transistor operating point or load impedance; the PRF can be adjusted by controlling the frequency of the trigger signal.

[0005] 3. Based on a high-voltage pulse generator (HVP), a capacitor is charged and then rapidly discharged to generate short high-voltage pulses. Pulse width modulation can adjust the on-time of switching devices (such as MOSFETs and IGBTs); PRF adjustment can be controlled by the frequency of an external trigger signal.

[0006] 4. Based on the FPGA logic chip, the internal PLL generates a high-speed 400Mhz clock to achieve the output of 5ns pulses. By writing the internal logic program, the pulse frequency output of 80k high PRF is achieved.

[0007] The above four methods each have their own advantages and disadvantages. Sometimes they are used to quickly build a temporary test system; some are suitable for making circuit modules and used in ultrasonic instruments. The selection needs to follow the design requirements.

[0008] Among the above-mentioned current technologies, The first technology has the disadvantage that it requires a ready-made device as part of the system. High-end waveform generators usually cost more than hundreds of thousands of yuan, and the devices are large in size, making them inconvenient to integrate into ultrasound equipment as a module.

[0009] The second technology, avalanche tube, can generate very narrow pulses, but it is limited by the heat dissipation of the tube. Even with the tube plus active heat dissipation measures, it is difficult to achieve a high-frequency avalanche effect of 80k.

[0010] The third technology can produce a very narrow excitation pulse width, but once the device is fixed, the pulse width is also fixed. Pulse width control is difficult through charge and discharge, and software adjustment is not possible; it requires replacing the device. Furthermore, the pulse width is fixed, making it difficult to adjust.

[0011] The fourth technology is currently commonly used in larger instruments and equipment. FPGAs are relatively large, consume high power, generate high heat, and are therefore expensive. They also require an external USB controller chip and multiple modules. FPGAs require multiple voltages beyond the core, making power module design complex and unsuitable for integration in small, portable devices. A major issue is trigger signal output. Due to jitter deviation in the FPGA system clock, even extremely narrow pulses (e.g., 5ns-10ns) can cause some transmission jitter in the output signal.

[0012] Among the above-mentioned current technical implementation methods, either the pulse width and PRF dynamic adjustment functions cannot be realized; or it is a set of equipment itself and cannot be embedded in the ultrasound board design system; or it is high in cost, large in size, and high in power consumption, and is not suitable for integration into lightweight equipment.

[0013] Therefore, a low-cost and small-sized ultrasonic excitation source with high PRF and adjustable pulse is needed. Summary of the Invention

[0014] In view of this, an object of the present invention is to provide a microprocessor-based variable narrow pulse and high PRF control system and method, which utilizes a low-cost and small-sized microprocessor to generate an ultrasonic signal with high PRF and adjustable pulse width.

[0015] In order to achieve the above object, the present invention provides the following technical solutions: The microprocessor-based variable narrow pulse and high PRF control system provided by the present invention includes a main control ARM core module, a clock module, and a timer module. The clock module and the timer module are respectively connected to the main control ARM core module, and the clock module serves as a reference clock source for the timer. The timer module includes at least two cascaded hardware timers, wherein the first timer TIM5 is configured as a master mode timer and the second timer TIM2 is configured as a slave mode timer; The trigger output terminal of the master mode timer is connected to the trigger input terminal of the slave mode timer to form a timer linkage structure; The master mode timer is configured to control a pulse repetition frequency (PRF), and the slave mode timer is configured to control a pulse width.

[0016] Furthermore, the frequency division coefficient and the auto-reload register value of the master mode timer are calculated and determined according to the following formula: ARR*(PSC+1)=Ft / PRF; Where Ft is the timer reference clock frequency, PSC is the frequency division coefficient, ARR is the value of the auto-reload register, and PRF is the pulse repetition frequency.

[0017] Furthermore, the comparison register value of the slave mode timer is determined by iterative calculation, specifically including: Initially set the compare register value; Calculate the current pulse width pulsewidth=(PSC+1)*CCR / Ft; Among them, CCR represents the comparison register value; pulsewidth represents the current pulse width; When the calculated pulse width value falls within the target pulse width range, the iteration stops; otherwise, the CCR value is incremented to continue the calculation.

[0018] Furthermore, the overflow time of the master mode timer is calculated according to the following formula: T=(ARR+1)*(PSC+1) / Ft, Where T is the overflow time of the master mode timer.

[0019] Furthermore, the main control ARM core module adopts the Cortex-M7 core architecture; The first timer TIM5 is configured to have its clock source be a system clock generated by an internal phase-locked loop; The second timer TIM2 receives the trigger output signal TRGO of the first timer TIM5 as an enable signal; Set the pre-scaling coefficient PSC and the auto-reload register ARR value of the first timer TIM5; Setting the comparison register CCR value of the second timer TIM2 to determine the pulse width adjustable range value; The PWM output pin of the second timer TIM2 outputs a continuously adjustable narrow pulse signal.

[0020] Furthermore, the PWM output pin is configured as a push-pull output mode, and the output signal drives the high-voltage excitation generation module.

[0021] Furthermore, the clock module inputs a reference clock through an external crystal oscillator and multiplies the frequency to 120MHz-240MHz through a phase-locked loop.

[0022] Furthermore, it also includes a USB communication interface module, which is configured to receive pulse width and PRF parameter setting instructions from a host computer.

[0023] The present invention provides a microprocessor-based variable narrow pulse and high PRF control method, wherein the microprocessor adopts a Cortex-M7 core architecture, comprising the following steps: S1: Use the first timer TIM5 as the master mode timer and configure its clock source to be the system clock generated by the internal phase-locked loop; S2: Use the second timer TIM2 as a slave mode timer and receive the trigger output signal TRGO of the first timer TIM5 as an enable signal; S3: Set the prescaler coefficient PSC and the auto-reload register ARR value of the first timer TIM5 through the linkage configuration module to meet the formula: ARR×(PSC+1)=Ft / PRF, where Ft is the timer reference clock frequency and PRF is the pulse repetition frequency; S4: Dynamically set the comparison register CCR value of the second timer TIM2 through the pulse width calculation module to meet the narrow pulse width formula: pulsewidth=(PSC+1)×CCR / Ft, where the pulse width can be adjusted in the range of 5ns to 1000ns; S5: Output a continuous adjustable narrow pulse signal through the PWM output pin of the second timer TIM2.

[0024] Furthermore, the configuration process of the master mode timer parameters includes: Set the initial value of the frequency division coefficient; Calculate the auto-reload register value by ARR=Floor(Ft / (PRF*(PSC+1))); When the calculated overflow time exceeds the preset threshold, the PSC value is incremented and the ARR value is recalculated; The beneficial effects of the present invention are: The present invention provides a microprocessor-based variable narrow pulse and high PRF control system and method. The system includes a master ARM core module, a clock module, and a timer module. The clock module and the timer module are respectively connected to the master ARM core module. The timer module includes at least two cascaded hardware timers, wherein a first timer TIM5 is configured as a master mode timer, and a second timer TIM2 is configured as a slave mode timer. The trigger output of the master mode timer is connected to the trigger input of the slave mode timer to form a timer linkage structure. The master mode timer is configured to control the pulse repetition frequency (PRF), and the slave mode timer is configured to control the pulse width. The clock module uses a phase-locked loop (PLL) to multiply the frequency as a timer reference clock source. The system can support ultra-narrow pulse generation, output extremely narrow pulse width with low jitter, and the pulse width is adjustable, thereby reducing costs, being compact, modular, and convenient for commercial integrated applications.

[0025] Other advantages, objects, and features of the present invention will be described in part in the following description and, in part, will be apparent to those skilled in the art upon examination of the following description or may be learned from practice of the present invention. The objects and other advantages of the present invention may be realized and obtained through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to make the purpose, technical solutions and beneficial effects of the present invention more clear, the present invention provides the following drawings for illustration.

[0027] Figure 1 This is the system block diagram for implementing a narrow pulse source based on M7.

[0028] Figure 2 This is a circuit diagram for realizing square wave output with adjustable pulse width by linking timers TIM2 and TIM5.

[0029] Figure 3 The present invention is a flow chart of a method for determining timer frequency division parameters and comparison register values. DETAILED DESCRIPTION

[0030] The present invention will be further described below with reference to the accompanying drawings and specific embodiments so that those skilled in the art can better understand the present invention and implement it. However, the embodiments are not intended to limit the present invention.

[0031] Example 1 like Figure 1 As shown, Figure 1 The system block diagram for realizing the narrow pulse source based on M7 is shown. The variable narrow pulse and high PRF control system based on the microprocessor provided in this embodiment includes a main control ARM core module, a clock module and a timer module; The main control ARM core module is connected to the clock module and the timer module respectively; The timer module includes at least two cascaded hardware timers, wherein the first timer TIM5 is configured as a master mode timer and the second timer TIM2 is configured as a slave mode timer; The trigger output terminal of the master mode timer is connected to the trigger input terminal of the slave mode timer to form a timer linkage structure; The master mode timer is configured to control the pulse repetition frequency (PRF), and the slave mode timer is configured to control the pulse width; The clock module is multiplied by a phase-locked loop as a reference clock source for the timer.

[0032] The preferred solution of this embodiment is to multiply the frequency to 240MHz through a phase-locked loop, and the clock module is multiplied to 240MHz through a phase-locked loop as the timer reference clock source. The main control ARM core module adopts the Cortex-M7 core architecture; or a high-frequency processor is used. In order to generate a signal with a minimum pulse width of 5ns, the processor speed must be at least 200Mhz.

[0033] The frequency division coefficient and the auto-reload register value of the master mode timer in this embodiment are calculated and determined according to the following formula: ARR*(PSC+1)=Ft / PRF; Where Ft is the timer reference clock frequency; PSC is the frequency division coefficient; ARR is the automatic reload register; PRF is the pulse repetition frequency; The comparison register CCR value of the slave mode timer in this embodiment is determined by iterative calculation, specifically including: Initial setting CCR=1; Calculate the current pulse width pulsewidth=(PSC+1)*CCR / Ft; Among them, CCR represents the compare register value; When the calculated value falls within the range of ±10% of the target pulse width, the iteration stops; otherwise, the CCR value is incremented to continue the calculation.

[0034] The overflow time calculation formula of the master mode timer in this embodiment is T=(ARR+1)*(PSC+1) / Ft, The ARR value ensures that the overflow time does not exceed 1 second by cyclically adjusting the PSC value, that is, T≤1 second.

[0035] The output end of the timer module described in this embodiment is connected to a push-pull output circuit and is configured to output a pulse signal with an adjustable pulse width of 5ns-1000ns and an adjustable PRF of 100Hz-80kHz.

[0036] The clock module in this embodiment includes a crystal oscillator with an accuracy of 20 ppm and is connected to an external storage module via an AXI bus. The external storage module includes at least 128 KB Flash and 512 KB SRAM.

[0037] This embodiment further includes a USB communication interface module, which is configured to receive pulse width and PRF parameter setting instructions from a host computer.

[0038] The microprocessor-based variable narrow pulse and high PRF control method provided in this embodiment includes the following steps: Configure the clock division parameter PSC of the master mode timer TIM5 and the value of the automatic reload register ARR to set the pulse repetition frequency; Configure the compare register CCR value of slave mode timer TIM2 to set the pulse width; Establish a cascade trigger mechanism for master and slave timers so that the overflow signal of the master mode timer triggers the slave mode timer to work; Based on a 240MHz reference clock source, a pulse signal with adjustable pulse width and PRF is directly output through a hardware timer.

[0039] The configuration process of the master mode timer parameters in this embodiment includes: Set the initial value of the frequency division coefficient to 1; Calculate the auto-reload register value by ARR=Floor(Ft / (PRF*(PSC+1))); When the calculated overflow time exceeds 1 second, the PSC value is incremented and the ARR value is recalculated.

[0040] In the pulse width modulation process described in this embodiment, the master and slave timer frequency division coefficients are kept consistent; the slave mode timer ARR value is set to the maximum count value 0xFFFFFFFF; and the CCR value is iteratively adjusted so that the output pulse width falls within the target value ±10% error range.

[0041] Example 2 like Figure 1 As shown, Figure 1 This is a system block diagram based on the M7 narrow pulse source. This embodiment uses the M7 core as an example to illustrate the specific configuration process of implementing a variable narrow pulse and high PRF control system through this method. The overall system solution framework of the narrow pulse excitation source obtained by this method is shown in the figure. Figure 1 As shown, it mainly includes the main control ARM core module, clock module, internal timer module, power module, JTAG / SW module, external flash and other storage modules, internal FIFO module, serial port and SPI interface module; The main control ARM core module uses the Cortex-M7 core, which provides higher computing performance. It has a six-stage pipeline and a dual-issue superscalar architecture, can execute two instructions in a single clock cycle, supports double-precision floating-point operations, and has separate instruction and data caches. This effectively reduces latency between the processor and memory, improves processor performance, and provides a guarantee for ultra-narrow pulse source products.

[0042] The clock module uses a high-precision crystal oscillator with an error range of 20ppm, providing a stable baseline clock input for the entire system. The system clock is multiplied to 240Mhz by an internal phase-locked loop and provided to the timer and other modules.

[0043] The internal timer module is a hardware module that runs independently of the ARM. Its counting work does not require the participation of the MCU, so it is very suitable as a pulse trigger source. These timer modules can be used for a variety of applications, including time delay, event timing, PWM generation, etc. In this system, we mainly use the PWM function of the timer.

[0044] The JTAG / SW module is an ARM debugging / burning tool that supports both SWD (Serial Wire Debug) and JTAG interfaces and is suitable for development and debugging. The module circuit is relatively simple, and static protection is required for frequent plugging and unplugging.

[0045] The external storage module includes external flash and SRAM, etc. The M7 contains a rich peripheral configuration estimate, and performs some read and write management operations on these external storage devices through the AXI bus; the system is configured with 128KB of flash and 512KB of SRAM, which are mainly used to store programs and some business data.

[0046] The internal FIFO module includes various types of FIFO (First In, First Out) structures, which are used for various purposes, such as data transfer, caching, and event management. Direct memory access (DMA) controllers often have built-in FIFOs for efficient data transfer between main memory and peripherals. When peripherals (such as ADCs, SPI, and I2C) need to exchange data with main memory, the DMA controller can utilize the FIFOs to reduce CPU overhead and achieve high-speed data transfer.

[0047] The serial port and SPI interface modules are ARM peripherals. Serial communication (USART) is a method used for data transmission in microcontrollers. It supports full-duplex communication, that is, it can send and receive data at the same time. It also supports half-duplex and is mainly used for printing and debugging in the system. The SPI interface is a common interface for external devices. It is mainly used for interface interconnection and data reading and writing with external devices. It has relatively rich configuration firmware and can adapt to different SPI interface devices.

[0048] The power module converts 15V power into several different voltages such as 5V / 3.3V / 2.5V for use by various functional modules.

[0049] After the system is built, the timers of the system modules need to be configured and the operation of each module needs to be coordinated through programming. At the same time, the host computer software needs to be written to control the small modules through the USB interface and send various parameters.

[0050] Finally, a pulse excitation source with adjustable pulse width and adjustable output frequency is output through the hardware timer output port, which is used to drive the subsequent high-voltage excitation generation module.

[0051] This embodiment generates a long pulse by linking a clock timer: The ARM timer TIM includes a counter, prescaler, and auto-reload register. These three registers constitute the core of the timer, a circuit called a time base unit. All three registers are 16 bits, and 2 to the 16th power is 65536. This means that if the prescaler and auto-reload register are set to their maximum values, the maximum timer duration is 59.65 seconds, nearly one minute. The STM32 timer also supports cascade mode, where the output of one timer serves as the input of another. Adding these together, the maximum timer duration is 59.65 seconds × 65536 × 65536, which is approximately over 8,000 years.

[0052] Therefore, using a timer method cannot output a continuous pulse according to the PRF, and a timer linkage method is required to output continuous pulses.

[0053] The internal trigger input allows one timer to be used as a prescaler for another. The advanced control timer and general-purpose timer are internally connected in hardware, allowing for timer cascading. A master mode timer can reset, start, stop, or provide a clock to a slave mode timer.

[0054] In this system, timers TIM2 and TIM5 are linked to achieve square wave output with adjustable pulse width. The specific connection method is as follows Figure 2 As shown, Figure 2 This is a circuit diagram for realizing square wave output with adjustable pulse width by linkage between timer TIM2 and TIM5; timer 5 is in master mode, the counting clock comes from the system clock, timer 2 is in slave mode, and the timer enable operation of TIM5 is used as the trigger output signal, which is Figure 2 [TRGO] [TR1] in the PWM output pin triggers TIM2 and enables its counter, while outputting a PWM waveform with adjustable frequency, duty cycle, and pulse number. The specific configuration process is as follows: 1. Enable clock and GPIO configuration First, call the initialization function to start the clock for the corresponding GPIO port and configure the pull-up / pull-down settings and output mode for the relevant IO port. Here, push-pull output mode is used. TIM5 pins PA2 and PA3 are set as virtual pins and are not used. TIM2 pin PA5 is set as the final pulse output source.

[0055] 2. Timer initialization Call the timer initialization function to initialize Timer 2 and Timer 5. Parameters such as the timer clock frequency and count period (the value of the auto-reload register ARR) must be set. The PWM waveform output of TIM5 serves as the trigger input for TIM2, which is configured in Trigger Slave mode. TIM5 is configured in Master mode, triggered by the internal counter, with the clock source set to the internal clock. Finally, the pulse signal output is provided by TIM2's PA5 pin.

[0056] 3.PWM channel configuration Use the CubeMX tool to configure the PWM channel of the relevant timer, specifying parameters such as the output channel number, the initial value of the pulse width, and the positive and negative polarity of the PWM waveform.

[0057] 4. Start PWM output Finally, the hardware start output function is called to start the PWM output, enabling the timer's PWM signal generation and pin output.

[0058] The method for determining the timer division parameters and comparison register values ​​in this embodiment is as follows: After the two timers complete the basic configuration, it is also necessary to determine the timer division coefficient PSC, the automatic reloader ARR value and the comparison register CRR value based on the input pulse width and repetition frequency PRF.

[0059] According to the actual value range of PRF and the value of the latest pulse width, the counting frequency configuration parameter of timer 5 is PSC, so the counting frequency of timer 5 is set to Ft / PSC+1; The calculation mode is set to cumulative counting. When the calculation is full, an overflow signal is given and the counting starts again from 0.

[0060] The clock input is 16M, and after multiple internal clock PLL conversions, the clock used by the counter is 120Mhz, that is, Ft=120Mhz.

[0061] The timer count overflow time is determined by the configuration parameters ARR and PSC. The overflow time is T=T=(ARR+1)*(PSC+1) / Ft.

[0062] like Figure 3 As shown, Figure 3 This is a flow chart of a method for determining the timer frequency division parameter and the comparison register value. The method provided in this embodiment can more conveniently implement the ultrasonic pulse triggering mechanism. The specific process is as follows: Step 1: Try to set the frequency division coefficient PSC to 1, and calculate the automatic reloader ARR value of timer 5 by setting the user-set PRF value. The calculation formula is: ARR*(PSC+1)=Ft / PRF; Step 2: Calculate T = (ARR + 1) * (PSC + 1) / Ft, and determine whether its value is greater than 1s. If not, add PSC + 1 and return to step 1. If yes, proceed to step 3. Step 3: After determining the PSC value, calculate and determine the counting frequency F of timer 5 = Ft / (PSC+1); Step 4: Determine the output pulse width of timer 5 pulsewidth=(PSC+1)*CCR / Ft, the output compare register CCR takes the value 1, and determine whether the pulse width is greater than 300ns. If yes, proceed to the next step. If not, CCR+1, loop determination until the next step; Step 5: Determine the PSC value of Timer 2 and keep it consistent with Timer 5. Timer 5 is triggered, that is, it is triggered according to the input PRF value. Step 6: Set the ARR value of Timer 2 to the maximum value 0xFFFFFFFF. The purpose of setting the maximum value here is to obtain the minimum pulse width. Step 7: Determine the value of CCR by cyclic calculation and set CCR=1 first; The output pulse width of timer 2 is calculated using the formula pulsewidth=(PSC+1)*CCR / Ft. If it is between +10% of the set pulse width, it is considered appropriate. Otherwise, CCR+1 is used. The calculation is repeated until a suitable value is found.

[0063] In this embodiment, the excitation source pulse width obtained by the above steps is extremely narrow, around 5ns. Furthermore, the pulse width can be varied from 5ns to 1000ns. The pulse repetition frequency (PRF) is also adjustable over a wide range, from 100 to 80k. This means that a maximum of 80,000 excitation pulses can be generated within 1s, making it suitable for ultrasonic detection applications.

[0064] The above embodiments are merely preferred embodiments for the purpose of fully illustrating the present invention, and the scope of protection of the present invention is not limited thereto. Equivalent substitutions or modifications made by those skilled in the art based on the present invention are within the scope of protection of the present invention. The scope of protection of the present invention shall be subject to the claims.

Claims

1. A microprocessor-based variable narrow pulse and high PRF control system, comprising a main control ARM core module, a clock module, and a timer module, wherein the clock module and the timer module are respectively connected to the main control ARM core module, and the clock module serves as a reference clock source for the timer, and is characterized by: The timer module includes at least two cascaded hardware timers, wherein the first timer TIM5 is configured as a master mode timer and the second timer TIM2 is configured as a slave mode timer; The trigger output terminal of the master mode timer is connected to the trigger input terminal of the slave mode timer to form a timer linkage structure; The master mode timer is configured to control a pulse repetition frequency (PRF), and the slave mode timer is configured to control a pulse width.

2. The microprocessor-based variable narrow pulse and high PRF control system according to claim 1, characterized in that: The frequency division coefficient and auto-reload register value of the master mode timer are calculated and determined according to the following formula: ARR*(PSC+1)=Ft / PRF; Where Ft is the timer reference clock frequency, PSC is the frequency division coefficient, ARR is the value of the auto-reload register, and PRF is the pulse repetition frequency.

3. The microprocessor-based variable narrow pulse and high PRF control system according to claim 1, characterized in that: The comparison register value of the slave mode timer is determined by iterative calculation, specifically including: Initially set the compare register value; Calculate the current pulse width pulsewidth=(PSC+1)*CCR / Ft; Among them, CCR represents the comparison register value; pulsewidth represents the current pulse width; When the calculated pulse width value falls within the target pulse width range, the iteration stops; otherwise, the CCR value is incremented to continue the calculation.

4. The microprocessor-based variable narrow pulse and high PRF control system according to claim 1, characterized in that: The overflow time of the master mode timer is calculated according to the following formula: T=(ARR+1)*(PSC+1) / Ft, where T represents the overflow time of the master mode timer.

5. The microprocessor-based variable narrow pulse and high PRF control system according to claim 1, characterized in that: The main control ARM core module adopts the Cortex-M7 core architecture; The first timer TIM5 is configured to have its clock source be a system clock generated by an internal phase-locked loop; The second timer TIM2 receives the trigger output signal TRGO of the first timer TIM5 as an enable signal; Set the pre-scaling coefficient PSC and the auto-reload register ARR value of the first timer TIM5; Setting the comparison register CCR value of the second timer TIM2 to determine the pulse width adjustable range value; The PWM output pin of the second timer TIM2 outputs a continuously adjustable narrow pulse signal.

6. The microprocessor-based variable narrow pulse and high PRF control system according to claim 5, characterized in that: The PWM output pin is configured as a push-pull output mode, and the output signal drives the high-voltage excitation generation module.

7. The microprocessor-based variable narrow pulse and high PRF control system according to claim 1, characterized in that: The clock module inputs a reference clock through an external crystal oscillator and multiplies the frequency to 120MHz-240MHz through a phase-locked loop.

8. The microprocessor-based variable narrow pulse and high PRF control system according to claim 1, characterized in that: It also includes a USB communication interface module, which is configured to receive pulse width and PRF parameter setting instructions from a host computer.

9. A variable narrow pulse and high PRF control method based on a microprocessor, wherein the microprocessor adopts a Cortex-M7 core architecture, characterized in that: The following steps are involved: S1: Use the first timer TIM5 as the master mode timer and configure its clock source to be the system clock generated by the internal phase-locked loop; S2: Use the second timer TIM2 as a slave mode timer and receive the trigger output signal TRGO of the first timer TIM5 as an enable signal; S3: Set the prescaler coefficient PSC and the auto-reload register ARR value of the first timer TIM5 through the linkage configuration module to satisfy the formula: ARR × (PSC + 1) = Ft / PRF, where Ft is the timer reference clock frequency and PRF is the pulse repetition frequency; S4: Dynamically set the comparison register CCR value of the second timer TIM2 through the pulse width calculation module to meet the narrow pulse width formula: pulsewidth=(PSC+1)×CCR / Ft, where the pulse width can be adjusted in the range of 5ns to 1000ns; S5: Output a continuous adjustable narrow pulse signal through the PWM output pin of the second timer TIM2.

10. The microprocessor-based variable narrow pulse and high PRF control method according to claim 9, characterized in that: The configuration process of the master mode timer parameters includes: Set the initial value of the frequency division coefficient; Calculate the auto-reload register value by ARR=Floor(Ft / (PRF*(PSC+1))); When the calculated overflow time exceeds a preset threshold, the PSC value is incremented and the ARR value is recalculated.

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