Analog-to-digital converter and resolution improving method and common-mode voltage compensation method thereof

Abstract

The invention discloses an analog-to-digital converter and a resolution ratio improving method and a common-mode voltage compensation method thereof. The sampled # imgabs0 # and # imgabs1 # are subjected to pipeline-level M-level step-by-step quantization, n-bit binary digital codes are obtained through the Mth-level quantization, and n-bit non-binary digital codes are obtained through the other levels of quantization. The method comprises the following steps: under the condition of ensuring that first-stage quantization and second-stage quantization adopt # imgabs2 # with the same architecture for quantization, during first-stage quantization, adding one-bit successive approximation conversion to # imgabs3 # and # imgabs4 # after sampling; and the # imgabs5 # and the # imgabs6 # which are subjected to successive approximation conversion are converted into one-bit binary digital codes. And sequentially carrying out digital synthesis on each level of quantized digital code to form a # imgabs7 # binary digital code, and during digital synthesis, adding the 1-bit binary digital code before the highest bit of the # imgabs8 # binary digital code to form a # imgabs9 # binary digital code. The architecture improves the input swing of the analog-to-digital converter, thereby improving the least significant bit of the system.

Description

Technical Field

[0001] The present invention relates to an analog-to-digital converter in the field of integrated circuits and microelectronics, and in particular to a pipeline analog-to-digital converter (Pipeline ADC) and a resolution improvement method and a common-mode voltage compensation method thereof. Background Art

[0002] Pipeline ADCs have become core devices in fields such as communications, medical imaging, and high-speed data acquisition due to their advantages of high precision, high conversion rate, and low power consumption. Figure 1 , Figure 1 This is the architecture of a traditional pipelined analog-to-digital converter. Its core structure quantizes the analog signal step by step through multiple pipeline stages. Each stage uses a sub-ADC and a residual amplifier to achieve coarse quantization and residual amplification. However, its resolution is proportional to the number of system stages, so achieving higher resolution requires increasing the number of stages. Furthermore, the residual amplifier requires common-mode voltage calibration or compensation.

[0003] (1) Pursuit of high resolution like Figure 2 The pipelined ADC described in [Zheng, ISSCC'20] by Zihao Zheng et al. ('A Single-Channel 5.5mW 3.3GS / s 6b Fully Dynamic Pipelined ADC with Post-Amplification Residue Generation', IEEE ISSCC, 2020) is a pipelined ADC. In a traditional architecture, each stage of an ADC operates as follows: the ADC performs quantization, the DAC subtracts the quantized voltage from the quantization result to generate a residual voltage, and the amplifier amplifies the residual voltage and passes it to the next stage. In Zheng's architecture, each stage of the ADC operates as follows: the DAC subtracts the quantized voltage from the quantization result of the previous stage to generate a residual voltage. These two operations are then performed simultaneously: the residual voltage is quantized by the ADC and amplified by the amplifier before being passed to the next stage.

[0004] In terms of timing, Figure 3 As shown, the analog-to-digital converter in Zheng's architecture has only two operations and ( and Simultaneously), while the traditional architecture requires three operations ( , and In this way, Zheng solved the timing redundancy in the traditional architecture. However, Zheng did not consider the redundancy of the first stage of the pipeline analog-to-digital converter. As shown in the timing diagram, the sampling stage The pulse width interval of '0' and the amplification stage The pulse width intervals of '1's are strictly aligned, but the sampling phase of the first stage of the system does not need to be aligned with the amplification phase of the previous stage. Therefore, the first stage system uses the same clock as the remaining stages, which actually causes time redundancy in the first stage sampling phase. Furthermore, because the first stage and subsequent stages use the same timing and architecture, the quantization voltage intervals are exactly the same across all stages of the system. Therefore, with each additional stage in the system, the least significant bit (LSB) voltage decreases by a factor of two, affecting system accuracy.

[0005] (2) Compensation of common mode voltage See also Figure 4 Consider: clock feedthrough affects the common-mode voltage at the amplifier input; the different mobilities of holes and electrons lead to a mismatch in the intrinsic gain between PMOS and NMOS; and common-mode offset causes the differential voltage to approach the power rail, ultimately affecting the differential gain. Analog-to-digital converters typically use differential inputs to combat zero-point drift and even-order harmonics. However, this common-mode voltage offset affects the gain of the differential amplifier, thereby affecting the accuracy of the ADC. Therefore, common-mode voltage calibration or compensation is required at each stage of a pipelined ADC.

[0006] like Figure 5 MediaTek Inc. (publication numbers: CN114866049A; TW202232885A) has proposed a common-mode voltage compensation method. This method uses feedback resistors (Rfbp, Rfbn) to detect the common-mode signal and establishes a voltage divider mechanism using common-mode compensation resistors (RCMp, RCMn) to compensate for the output voltage's common-mode voltage. While this method effectively stabilizes the common-mode voltage, it introduces a feedback loop into the amplifier, reducing circuit bandwidth and limiting its application in high-speed systems. Summary of the Invention

[0007] To improve the accuracy of an analog-to-digital converter, the present invention provides a pipelined analog-to-digital converter and a method for improving its resolution. To reduce the impact of common-mode offset on residual voltage transfer, the present invention also provides a pipelined analog-to-digital converter and a method for compensating its common-mode voltage.

[0008] The present invention is implemented by the following technical solution: a method for improving the resolution of a pipelined analog-to-digital converter, wherein the pipelined analog-to-digital converter is used to: Sampling analog signal V in+ 、Vin- ; After sampling, V in+ 、V in- Perform M-level quantization in a pipelined manner: the M-th level quantization obtains an n-bit binary digital code, and each of the remaining levels of quantization obtains an n-bit non-binary digital code; The digital codes after each level of quantization are sequentially digitally integrated to form a binary digital code of M*(n-1)+1 bits; Among them, the resolution improvement method is used to ensure that the first-level quantization and the second-level quantization use the same architecture Flash-ADC for quantization. In the first-level quantization, the sampled V in+ 、V in- Add a 1-bit successive approximation conversion and convert the V in+ 、V in- Convert it into a 1-bit binary digital code; and during digital synthesis, add the 1-bit binary digital code before the highest bit of the M*(n-1)+1-bit binary digital code to form an M*(n-1)+2-bit binary digital code.

[0009] As a further improvement of the above solution, M is 5 and n is 2.

[0010] The present invention also provides a common-mode voltage compensation method for a pipelined analog-to-digital converter, wherein the pipelined analog-to-digital converter is used to: Sampling analog signal V in+ 、V in- ; After sampling, V in+ 、V in- Perform M-level quantization in a pipelined manner: the M-level quantization obtains an n-bit binary digital code, and each of the remaining levels obtains an n-bit non-binary digital code; in which, while ensuring that the first-level quantization and the second-level quantization use the same Flash-ADC architecture for quantization, in the first-level quantization, the sampled V in+ 、V in- Add a 1-bit successive approximation conversion; after the successive approximation conversion, V in+ 、V in- Convert to 1-bit binary digital code; The digital codes after each level of quantization are sequentially digitally integrated to form an M*(n-1)+1-bit binary digital code, and during the digital integration, the 1-bit binary digital code is added before the highest bit of the M*(n-1)+1-bit binary digital code to form an M*(n-1)+2-bit binary digital code; Wherein, the common mode voltage compensation method includes: Under the condition that the first-stage quantization and the second-stage quantization adopt the same Flash-ADC architecture for quantization, in the first-stage quantization, the sampled V in+ 、V in- Add a 1-bit successive approximation conversion; After successive approximation conversion, V in+ 、V in- Converting into a 1-bit binary digital code, and adding the 1-bit binary digital code before the most significant bit of the M*(n-1)+1-bit binary digital code during digital synthesis; For each level of quantization before the last two levels of quantization, common-mode detection is performed on the input signal before quantization by the corresponding Flash-ADC. And for each level of quantization between the first and last levels of quantization, voltage compensation is performed on the common-mode voltage detected by the previous level: when the common-mode voltage is too high, the common-mode voltage is compensated downward; when the common-mode voltage is too low, the common-mode voltage is compensated upward.

[0011] As a further improvement of the above solution, M is 5 and n is 2.

[0012] The present invention also provides a pipelined analog-to-digital converter, comprising: Sampling analog signal V in+ 、V in- Sampling circuit; After sampling, V in+ 、V in- An M-level quantization circuit for performing M-level quantization in a pipelined manner: the M-th level quantization circuit obtains an n-bit binary digital code, and each of the remaining levels of quantization circuits obtains an n-bit non-binary digital code; A digital synthesis module for sequentially digitally synthesizing the digital codes after each level of quantization to form an M*(n-1)+1-bit binary digital code; Under the condition that the first-stage quantization circuit and the second-stage quantization circuit adopt the same Flash-ADC architecture for quantization, in the first-stage quantization, the sampled V in+ 、V in- A successive approximation conversion circuit is added that performs successive approximation conversion of 1 bit at a time; After successive approximation conversion, V in+ 、V in- Comparator 1 converts the binary digital code into 1 bit; The digital synthesis module adds the 1-bit binary digital code before the highest bit of the M*(n-1)+1-bit binary digital code during digital synthesis.

[0013] As a further improvement of the above solution, the successive approximation conversion circuit includes four capacitors CP11~CP14 and four switches K11~K14; one end of CP11 and CP12 is used to receive the sampled V in+ The other end is connected to one end of K11 and K12 with an electric control switch key, and the other ends of K11 and K12 for selective connection of the corresponding electric control switch key are connected to the reference voltage V REF and ground; one end of CP13 and CP14 is used to receive the sampled V in- The other end is connected to one end of K13 and K14 with an electric control switch key, and the other ends of K13 and K14 for selective connection of the corresponding electric control switch key are connected to V REF and land; In the initial state of the pipelined ADC, one of K11, K12, and K13, K14 is grounded, and the other is connected to V REF When the binary code output by comparator 1 is 1, K11 and K12 are all grounded, and K13 and K14 are all connected to V REF When the binary code output by comparator 1 is 0, K11 and K12 are all connected to V REF , K13 and K14 are all grounded.

[0014] As a further improvement of the above solution, the pipelined analog-to-digital converter further includes: For each quantization stage before the last two stages of quantization, a common-mode detection circuit is added to perform common-mode detection on the input signal before quantization of the corresponding Flash-ADC. For each level of quantization between the first level of quantization and the last level of quantization, a voltage compensation circuit is added to compensate for the common-mode voltage output by the previous level of common-mode detection circuit: when the common-mode voltage is too high, the voltage compensation circuit compensates the common-mode voltage downward; when the common-mode voltage is too low, the voltage compensation circuit compensates the common-mode voltage upward.

[0015] Furthermore, each common mode detection circuit is a comparator 2, the two comparison terminals of the comparator 2 are respectively connected to the input signal before quantization of the corresponding Flash-ADC at this stage, and the output of the comparator 2 is also a 1-bit binary digital code; each voltage compensation circuit includes 4 compensation capacitors C i,1 ~C i,4 Each voltage compensation circuit is equipped with a decoder, i represents the level number of the quantization circuit; the input of each decoder is the 1-bit binary digital code CMi output by the comparator 2, which is converted into a 4-bit binary digital code and connected to the 4 compensation capacitors C of the i+1th level quantization circuit respectively. i+1,1 ~C i+1,4The lower plate; in the initial state of the pipelined ADC, the four compensation capacitors C i1 , C i3 The lower plate of C i2 , C i4 The lower plate of CM is connected to low level; i-1 =1, indicating that the common mode voltage VPi and VNi of the i-1th level are too high. i1 ~C i4 All are 0, realizing the downward compensation of common mode voltage VPi and VNi; when CMi=0, it means that the common mode voltage VPi and VNi of the i-1th level are too low. At this time, the compensation capacitor C i1 ~C i4 All are 1, achieving upward compensation of common-mode voltages VPi and VNi.

[0016] Furthermore, except for the last two stages of quantization circuits, each of the remaining stages of quantization circuits includes a residual amplifier that performs residual amplification on the input signal before quantization by the Flash-ADC of the current stage and then outputs VPi and VNi.

[0017] Furthermore, M is 5 and n is 2.

[0018] Compared with the prior art, the present invention has the following beneficial effects: (1) By adding a SAR conversion at the first level of quantization, the timing redundancy is reduced. At the same time, under the same post-stage Flash-ADC architecture, this architecture improves the input swing of the analog-to-digital converter. V pp , thereby increasing the system's least significant bit (LSB) , N is the resolution of the analog-to-digital converter), further improving the resolution of the entire system. The quantization interval of the Flash-ADC is [ Vref , Vref ], and the quantization interval of the SAR conversion part in the first-level quantization is [-Vref, Vref ]. Based on the above analysis, under the condition that the Flash-ADC structure is the same in each level of quantization, compared with the existing technology with the same LSB, the present invention can extend the resolution of the analog-to-digital converter by 1 bit.

[0019] (2) Common-mode voltage detection is performed at the current quantization stage, and corresponding common-mode voltage compensation is performed at the next quantization stage based on the results of the common-mode detection. This compensation method does not introduce a feedback loop and does not reduce the bandwidth of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 This is the architecture diagram of a traditional pipelined analog-to-digital converter.

[0021] Figure 2 This is an architectural diagram of an existing pipelined analog-to-digital converter.

[0022] Figure 3 yes Figure 1 、 2 The working timing comparison diagram of the two pipelined analog-to-digital converters is shown in the figure.

[0023] Figure 4 Schematic diagram of the common-mode voltage compensation mechanism of an existing pipeline analog-to-digital converter.

[0024] Figure 5 The present invention is a common-mode voltage compensation circuit diagram of an existing pipeline analog-to-digital converter.

[0025] Figure 6 It is a flow chart of the method for improving the resolution of the pipelined analog-to-digital converter of the present invention.

[0026] Figure 7 It is a flow chart of the common-mode voltage compensation method of the pipelined analog-to-digital converter of the present invention.

[0027] Figure 8 4 is a circuit architecture diagram of the pipeline analog-to-digital converter according to embodiment 1 of the present invention.

[0028] Figure 9 yes Figure 8 Circuit architecture diagram of the first-stage quantization circuit and its preceding circuit in the pipelined analog-to-digital converter.

[0029] Figure 10 yes Figure 8 Circuit architecture diagram of the second-stage quantization circuit of the pipelined analog-to-digital converter.

[0030] Figure 11 yes Figure 8 Circuit architecture diagram of the third-stage quantization circuit of the pipelined analog-to-digital converter.

[0031] Figure 12 yes Figure 8 Circuit architecture diagram of the fourth-stage quantization circuit of the pipelined analog-to-digital converter.

[0032] Figure 13 yes Figure 8 Circuit architecture diagram of the fifth-stage quantization circuit of the pipelined analog-to-digital converter.

[0033] Figure 14 yes Figure 8 Circuit architecture diagram of the digital synthesis module of the pipelined analog-to-digital converter.

[0034] Figure 15 yes Figure 8 Working timing diagram of the pipeline analog-to-digital converter.

[0035] Figure 16 yes Figure 8 Schematic diagram of the common-mode voltage compensation mechanism of the pipelined analog-to-digital converter.

[0036] Figure 17 for Figure 8 Circuit diagram of the common-mode detection module of the pipelined analog-to-digital converter.

[0037] Figure 18 for Figure 8 Schematic diagram of the common-mode compensation process for a pipelined analog-to-digital converter. DETAILED DESCRIPTION

[0038] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0039] See also Figure 6 , which is a flow chart of the method for improving the resolution of the pipelined analog-to-digital converter of the present invention. The method for improving the resolution of the present invention is specifically designed for the pipelined analog-to-digital converter and is a method for improving the resolution of the pipelined analog-to-digital converter. The pipelined analog-to-digital converter is used to: sample the analog signal V in+ 、V in- ; For the sampled V in+ 、V in- Perform M-level pipeline quantization: the M-th level quantization obtains an n-bit binary digital code, and each of the remaining levels of quantization obtains an n-bit non-binary digital code; the digital codes after each level of quantization are sequentially digitally integrated to form an M*(n-1)+1-bit binary digital code.

[0040] The method for improving the resolution includes: ensuring that the first-level quantization and the second-level quantization use the same architecture of Flash-ADC for quantization, in the first-level quantization, in+ 、V in- Add a 1-bit successive approximation conversion; after the successive approximation conversion, V in+ 、V in- Converted into a 1-bit binary digital code; during digital synthesis, the 1-bit binary digital code is added before the highest bit of the M*(n-1)+1-bit binary digital code to form an M*(n-1)+2-bit binary digital code.

[0041] By adding a SAR conversion in the first stage of quantization, the timing redundancy is reduced. At the same time, under the same post-stage Flash-ADC architecture, this architecture improves the input swing of the analog-to-digital converter. V pp , thereby increasing the system's least significant bit (LSB) , N is the resolution of the analog-to-digital converter), further improving the resolution of the entire system. The quantization interval of the Flash-ADC is [ Vref , Vref ], and the quantization interval of the SAR conversion part in the first-level quantization is [-Vref, Vref ]. Based on the above analysis, under the condition that the Flash-ADC structure is the same in each level of quantization, compared with the existing technology with the same LSB, the present invention can extend the resolution of the analog-to-digital converter by 1 bit.

[0042] The resolution improvement method of the present invention can realize the corresponding design concept by designing such a pipelined analog-to-digital converter. The corresponding pipelined analog-to-digital converter includes: a sampling circuit, an M-level quantization circuit, a digital synthesis module, a successive approximation conversion circuit, and a comparator.

[0043] The sampling circuit samples the analog signal V in+ 、V in- The M-level quantization circuit samples the V in+ 、V in- Perform M-level pipeline quantization: the M-level quantization circuit obtains an n-bit binary digital code, and the remaining quantization circuits each obtain an n-bit non-binary digital code. The successive approximation conversion circuit ensures that the first-level quantization circuit and the second-level quantization circuit use the same Flash-ADC architecture for quantization. In the first-level quantization, the sampled V in+ 、V in- Add a 1-bit successive approximation conversion. A pair of comparators after successive approximation conversion of V in+ 、V in- Converted into a 1-bit binary digital code. The digital synthesis module sequentially digitally synthesizes the digital code after each level of quantization to form an M*(n-1)+1-bit binary digital code. During the digital synthesis, the digital synthesis module adds the 1-bit binary digital code before the highest bit of the M*(n-1)+1-bit binary digital code, ultimately forming an M*(n-1)+2-bit binary digital code.

[0044] See also Figure 7, which is a flow chart of the common-mode voltage compensation method of the pipelined analog-to-digital converter of the present invention. The common-mode voltage compensation method of the present invention is also specially designed for the pipelined analog-to-digital converter and is used to compensate the common-mode voltage at each level of quantization. It should be noted that the common-mode voltage compensation method of the present invention can be used without superposition. Figure 5 The resolution improvement method in the present invention can also play the role of common-mode voltage compensation for the existing pipelined analog-to-digital converter. Of course, superimposing the resolution improvement method of the present invention can make the pipelined analog-to-digital converter of the present invention even better.

[0045] The common-mode voltage compensation method includes: for each quantization level before the last two levels of quantization, performing common-mode detection on the input signal before quantization of the corresponding Flash-ADC at the current level; and for each quantization level between the first and last levels of quantization, performing voltage compensation on the common-mode voltage detected at the previous level: when the common-mode voltage is too high, the common-mode voltage is compensated downward; when the common-mode voltage is too low, the common-mode voltage is compensated upward.

[0046] The current quantization stage performs common-mode voltage detection, and the next quantization stage performs corresponding common-mode voltage compensation based on the common-mode detection results. This compensation method does not introduce a feedback loop and does not reduce the system bandwidth.

[0047] The common-mode voltage compensation method of the present invention can realize the corresponding design concept by designing such a pipelined analog-to-digital converter. In this case, the corresponding pipelined analog-to-digital converter includes: a sampling circuit, an M-level quantization circuit, a digital synthesis module, M-2 common-mode detection circuits, and M-2 voltage compensation circuits.

[0048] The common-mode detection circuit performs common-mode detection on the input signal before quantization by the corresponding Flash-ADC at each quantization stage before the last two quantization stages. The voltage compensation circuit performs voltage compensation on the common-mode voltage output by the previous common-mode detection circuit at each quantization stage between the first and last quantization stages. When the common-mode voltage is too high, the voltage compensation circuit compensates for it downward; when the common-mode voltage is too low, the voltage compensation circuit compensates for it upward.

[0049] Next, we will take an example to better illustrate the essence of the present invention. The present invention takes M as 5 and n as 2 as an example to illustrate the pipeline analog-to-digital converter of the present invention. Figure 8 , Figure 8 This is a circuit architecture diagram of a pipelined analog-to-digital converter according to Example 1 of the present invention. Since the circuit diagram is relatively large, concentrating it in one figure will result in the content being too small and unclear. Therefore, it is shown in parts in this embodiment: Figure 8 1 is a circuit architecture diagram of a pipelined analog-to-digital converter according to embodiment 1 of the present invention; Figure 9 yes Figure 8The circuit architecture diagram of the first-stage quantization circuit and its pre-order circuit of the pipelined analog-to-digital converter; Figure 10 yes Figure 8 Circuit architecture diagram of the second-stage quantization circuit of the pipelined analog-to-digital converter; Figure 11 yes Figure 8 Circuit architecture diagram of the third-stage quantization circuit of the pipelined analog-to-digital converter; Figure 12 yes Figure 8 Circuit architecture diagram of the fourth-stage quantization circuit of the pipelined analog-to-digital converter; Figure 13 yes Figure 8 Circuit architecture diagram of the fifth-stage quantization circuit of the pipelined analog-to-digital converter; Figure 14 yes Figure 8 Circuit architecture diagram of the digital synthesis module of the pipelined analog-to-digital converter.

[0050] The pipeline analog-to-digital converter at this time includes a sampling circuit 1, an M-level quantization circuit, a digital synthesis module 2, a 1-bit successive approximation conversion circuit 11, and a comparator 12.

[0051] The sampling circuit 1 includes two circuits for respectively sampling the analog signal V in+ 、V in- The two sampling switches SH1 and SH2 are used for sampling. The successive approximation conversion circuit is only designed in the first stage quantization circuit. in+ 、V in- Add a 1-bit successive approximation conversion.

[0052] The successive approximation conversion circuit 11 includes four capacitors CP11 to CP14 and four switches K11 to K14. One end of CP11 and CP12 is used to receive the sampled V in+ The other end is connected to one end of K11 and K12 with an electric control switch key, and the other ends of K11 and K12 for selective connection of the corresponding electric control switch key are connected to the reference voltage V REF One end of CP13 and CP14 is used to receive the sampled V in- The other end is connected to one end of K13 and K14 with an electric control switch key, and the other ends of K13 and K14 for selective connection of the corresponding electric control switch key are connected to V REF and land.

[0053] In the initial state of the pipelined ADC, one of K11, K12, and K13, K14 is grounded, and the other is connected to V REF When the binary code output by comparator 12 is 1, K11 and K12 are all grounded, and K13 and K14 are all connected to V REFWhen the binary code output by comparator 12 is 0, K11 and K12 are all connected to V REF , K13 and K14 are all grounded.

[0054] The first-stage circuit includes a residual amplifier RA, a Flash-ADC 13, and a common-mode detection circuit 14. Each common-mode detection circuit can be a second comparator. Except for the first and last two stages, each stage has the same circuit structure, including a residual amplifier RA, a Flash-ADC 13, a common-mode detection circuit 14, a DAC switching circuit 16, a compensation circuit 18, a decoder 15, and a quantization decoder 17. Finally, the second-stage quantization circuit includes a residual amplifier RA, a Flash-ADC 13, a DAC switching circuit 16, a compensation circuit 18, a decoder 15, and a quantization decoder 17. The final-stage quantization circuit includes a DAC switching circuit 16, a third comparator 19, two registers 20, a comparator decoder 21, and a quantization decoder 17. The number of capacitors in the DAC switching circuit 16 of the final-stage quantization circuit can be adjusted based on the actual design requirements. This is because the final-stage quantization circuit generates a binary digital code, rather than the non-binary digital code of other quantization circuits.

[0055] Therefore, except for the last quantization stage, each quantization stage includes a residual amplifier RA and a flash-ADC 13 with the same architecture. Except for the last two quantization stages, each quantization stage also includes a common-mode detection circuit 14. Except for the first and last quantization stages, each quantization stage also includes a decoder 15 and a DAC switching circuit 16. Except for the first quantization stage, each quantization stage also includes a quantization decoder 15.

[0056] The two comparison terminals of the second comparator are connected to the input signal before quantization of the corresponding Flash-ADC at this stage, and the output of the second comparator is also a 1-bit binary digital code; each voltage compensation circuit includes 4 compensation capacitors C i，1 ~C i，4 Each voltage compensation circuit is equipped with a decoder, i represents the level number of the quantization circuit; the input of each decoder is the 1-bit binary digital code CMi output by the comparator 2, which is converted into a 4-bit binary digital code and connected to the 4 compensation capacitors C of the i+1th level respectively. i+1，1 ~C i+1，4 The lower plate.

[0057] In the initial state of the pipelined ADC, C i1 , C i3 The lower plate of C is connected to a high level (i.e. digital signal 1), i2 , C i4 The lower plate of CM is connected to a low level (i.e. digital signal 0).i-1 =1, indicating that the common mode voltage VPi and VNi of the i-1th level are too high. i1 ~C i4 All are 0, realizing the downward compensation of common mode voltage VPi and VNi; when CMi=0, it means that the common mode voltage VPi and VNi of the i-1th level are too low. At this time, the compensation capacitor C i1 ~C i4 All are 1, achieving upward compensation of common-mode voltages VPi and VNi.

[0058] Except for the last two stages of quantization circuits, each of the remaining stages of quantization circuits includes a residual amplifier that performs residual amplification on the input signal before quantization by the Flash-ADC of the current stage and then outputs VPi and VNi.

[0059] When M is 5 and n is 2, the DAC switching circuit 16 includes four capacitors CPi1 to CPi4, one end of which is connected to the residual amplified voltage output by the previous stage RA. Two capacitors CPi1 to CPi2 are connected to VPi output by the RA of the previous stage quantization circuit, and two capacitors CPi3 to CPi4 are connected to Vni output by the RA of the previous stage quantization circuit. The voltage compensation circuit 18 includes four compensation capacitors C i1 ~C i4 and a decoder. The first-stage quantization circuit includes a 1-bit SAR (successive approximation) logic, an RA (residual amplifier), and a 1.5-bit Flash-ADC (flash analog-to-digital converter). The SAR logic includes a comparator and a 1-bit DAC (digital-to-analog converter). The first-stage quantization circuit outputs three digital codes at the end of the conversion. The structures of the second, third, and fourth-stage circuits are exactly the same. Each stage of the circuit includes a DAC with common-mode compensation function, a residual amplifier, a sub-ADC (the sub-ADC architecture is a Flash ADC), and a common-mode detector. Each stage of the quantization circuit outputs two digital codes at the end of the conversion. The fifth-stage quantization circuit is a 2-bit SAR ADC (successive approximation analog-to-digital converter), including a comparator and a 1-bit DAC. At the end of the conversion, two digital codes are output.

[0060] The above 5-level quantization circuit outputs a total of 11 digital codes, which are synthesized by the digital synthesis module and finally output a 7-bit result. The timing of the first-level quantization circuit and the subsequent-level timing are as follows: Figure 15 As shown, it is a working timing diagram of the pipeline analog-to-digital converter.

[0061] The common-mode voltage compensation method of the present invention is a common-mode compensation technology that is completed by the cooperation of the previous and next-stage quantization circuits. The common-mode voltage detection is performed in the current-stage quantization circuit, and the corresponding common-mode voltage compensation is performed in the next-stage quantization circuit based on the result of the common-mode detection. This compensation method does not introduce a feedback loop and does not reduce the bandwidth of the system. Its mechanism is as follows Figure 16 As shown in the figure: Through the common-mode compensation technology coordinated with this two-stage quantization circuit, the common mode of the residual voltage is always stable near the ideal VCM, avoiding a deviation of the differential voltage toward the power rail (VDD or GND), thereby ensuring the correct transfer of the differential signal between each stage of the quantization circuit.

[0062] The working process and principle of the system are given here.

[0063] First, the first stage samples the differential signals vin+ and vin- through two sampling switches SH1 and SH2. At this time, the differential signal swing is [-Vref, Vref]. After the sampling is completed, the comparator 12 works to quantize the signal and obtain a single-digit code D1[2]. Then, according to the comparison result, DAC11 switches and subtracts the quantized voltage. At this time, the differential signal swing is reduced by half and becomes [ Vref , Vref ], in the quantization & amplification stage, the Flash-ADC continues to quantize the signal to obtain a 2-bit digital code D1[1:0], and at the same time the signal is amplified by the residual amplifier and transmitted to the next stage (second stage).

[0064] During the first-stage quantization and amplification phase, the second stage is in the sampling phase. Simultaneously with the second-stage sampling, the first stage performs common-mode detection and generates the common-mode detection result CM1. At the end of the second-stage sampling, signal DAC switching (switching the lower plate potentials of capacitors CP21, CP22, CP23, and CP24 based on the result of D1[1:0]) and common-mode compensation (switching the lower plate potentials of capacitors C21, C22, C23, and C24 based on the result of CM1) are simultaneously performed. During the second-stage quantization and amplification phase, the flash ADC quantizes the signal, generating a 2-bit digital code D2[1:0]. The signal is then amplified by the amplifier and transmitted to the next stage (the third stage).

[0065] During the second-stage quantization and amplification phase, the third stage is in the sampling phase. Simultaneously with the third-stage sampling, the second stage performs common-mode detection and obtains the common-mode detection result CM2. At the end of the third-stage sampling, signal DAC switching (based on the result of D2[1:0], the lower plates of capacitors CP31, CP32, CP33, and CP34 are switched) and common-mode compensation (based on the result of CM2, the lower plates of capacitors C31, C32, C33, and C34 are switched). During the second-stage quantization and amplification phase, the flash ADC quantizes the signal, generating a 2-bit digital code D3[1:0]. The signal is then amplified by the amplifier and transmitted to the next stage (the fourth stage).

[0066] During the third-stage quantization and amplification phase, the fourth stage is in the sampling phase. Simultaneously with the fourth-stage sampling, the third stage performs common-mode detection and obtains the common-mode detection result CM3. At the end of the fourth-stage sampling, signal DAC switching (based on the result of D3[1:0], the lower plates of capacitors CP41, CP42, CP43, and CP44 are switched) and common-mode compensation (based on the result of CM3, the lower plates of capacitors C41, C42, C43, and C44 are switched). During the second-stage quantization and amplification phase, the flash ADC quantizes the signal, generating a 2-bit digital code D4[1:0]. The signal is then amplified by the amplifier and transmitted to the next stage (the fifth stage).

[0067] During the fourth stage's quantization and amplification phase, the fifth stage is in the sampling phase. After sampling, the fifth stage switches to a DAC (subtracting the fourth stage's quantization voltage). The fifth stage then enters the quantization phase, where it performs a 2-bit SAR conversion to produce a 2-bit digital code, D5[1:0].

[0068] Finally, the five levels output a total of 11-bit digital codes, which are synthesized by the digital synthesis module to obtain the final 7-bit digital code.

[0069] Common mode detection module such as Figure 17As shown in the figure, its working process is as follows: the - terminal of the comparator is connected to the DC potential VCM. In the initial stage, switches K1, K2, and K3 of the common-mode detection module are closed, and switches K4 and K5 are opened. The top and bottom plates of the detection capacitors PC1 and NC1 are both connected to VCM, and the top plate potentials of PC1 and NC1 are reset to VCM. In the detection stage, switches K1, K2, and K3 are opened, and switches K4 and K5 are closed. The bottom plate of PC1 is connected to the P terminal of the differential signal, namely VP, and the bottom plate of NC1 is connected to the N terminal of the differential signal, namely VN. The top plates of PC1 and NC1 are both connected to the + terminal of the comparator. When the common-mode points of VP and VN shift, the shift will be coupled to the + terminal of the comparator through capacitors PC1 and NC1. Finally, the comparator compares the shifted common-mode voltage with the ideal DC potential VCM to obtain the result. When the common-mode voltage of the differential signal is greater than or equal to VCM, the comparator outputs a digital signal '1'; when the common-mode voltage of the differential signal is less than VCM, the comparator outputs a digital signal '0'.

[0070] The working process of common mode compensation is as follows Figure 18 RA_CM represents the common mode voltage of the differential signals VP1 and VN1 (i.e. ). Here we only analyze the case where RA_CM>VCM and VP1>VN1. The working process in other cases can be found in the figure. During the sampling phase, the bottom plates of CP21, C21, CN21, and C23 are connected to the reference voltage REF, and the bottom plates of CP22, C22, CN22, and C24 are connected to the bottom potential VSS. During the DAC switching phase, the capacitor bottom plates are switched according to the results of the previous stage (RA_CM>VCM, VP1>VN1). The switching results are: CP21, CP22, C21, and C22 are connected to the low potential VSS, C23 and C24 are connected to the low potential VSS, and CN21 and CN22 are connected to the high potential REF.

[0071] Since the system uses SAR logic for assistance at the first stage, it achieves 2.5-bit accuracy at the first stage, while doubling the input swing and quantization range of the system. Under the same system level and sub-ADC architecture conditions, the present invention achieves higher resolution (expanding the resolution by 1 bit and increasing the LSB to twice the original). The two-stage common-mode compensation technology proposed in the present invention compensates for the common-mode voltage offset by introducing a common-mode detection module and a common-mode compensation DAC, ensuring the correct transfer of the differential residual voltage. At the same time, compared with the method of compensation through feedback, the present invention avoids the introduction of a feedback loop and does not reduce the bandwidth of the system.

[0072] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the patent for this invention shall be determined by the appended claims.

Claims

1. A method for improving the resolution of a pipelined analog-to-digital converter, wherein the pipelined analog-to-digital converter is used to: Sampling analog signal V in+ 、V in- ; After sampling, V in+ 、V in- Perform M-level quantization in a pipelined manner: the M-th level quantization obtains an n-bit binary digital code, and each of the remaining levels of quantization obtains an n-bit non-binary digital code; The digital codes after each level of quantization are sequentially digitally integrated to form a binary digital code of M*(n-1)+1 bits; It is characterized by: The resolution improvement method comprises: Under the condition that the first-stage quantization and the second-stage quantization adopt the same Flash-ADC architecture for quantization, in the first-stage quantization, the sampled V in+ 、V in- Add a 1-bit successive approximation conversion; After successive approximation conversion, V in+ 、V in- Convert to 1-bit binary digital code; During digital synthesis, the 1-bit binary digital code is added before the highest bit of the M*(n-1)+1-bit binary digital code to form an M*(n-1)+2-bit binary digital code.

2. The method for improving the resolution of a pipelined analog-to-digital converter according to claim 1, wherein: M is 5 and n is 2.

3. A common-mode voltage compensation method for a pipelined analog-to-digital converter, the pipelined analog-to-digital converter being used for: Sampling analog signal V in+ 、V in- ; After sampling, V in+ 、V in- Perform M-level quantization in a pipelined manner: the M-th level quantization obtains an n-bit binary digital code, and each of the remaining levels of quantization obtains an n-bit non-binary digital code; The digital codes after each level of quantization are sequentially digitally integrated to form a binary digital code of M*(n-1)+1 bits; It is characterized by: The common-mode voltage compensation method comprises: Under the condition that the first-stage quantization and the second-stage quantization adopt the same Flash-ADC architecture for quantization, in the first-stage quantization, the sampled V in+ 、V in- Add a 1-bit successive approximation conversion; After successive approximation conversion, V in+ 、V in- Converting into a 1-bit binary digital code, and adding the 1-bit binary digital code before the most significant bit of the M*(n-1)+1-bit binary digital code during digital synthesis; For each level of quantization before the last two levels of quantization, common-mode detection is performed on the input signal before quantization by the corresponding Flash-ADC. And for each level of quantization between the first and last levels of quantization, voltage compensation is performed on the common-mode voltage detected by the previous level: when the common-mode voltage is too high, the common-mode voltage is compensated downward; when the common-mode voltage is too low, the common-mode voltage is compensated upward.

4. The common-mode voltage compensation method of the pipelined analog-to-digital converter according to claim 3, characterized in that: M is 5 and n is 2.

5. A pipelined analog-to-digital converter, comprising: Sampling analog signal V in+ 、V in- Sampling circuit; as well as After sampling, V in+ 、V in- An M-level quantization circuit for performing M-level quantization in a pipelined manner: the M-th level quantization circuit obtains an n-bit binary digital code, and each of the remaining levels of quantization circuits obtains an n-bit non-binary digital code; A digital synthesis module for sequentially digitally synthesizing the digital codes after each level of quantization to form an M*(n-1)+1-bit binary digital code; It is characterized by further comprising: Under the condition that the first-stage quantization circuit and the second-stage quantization circuit adopt the same Flash-ADC architecture for quantization, in the first-stage quantization, the sampled V in+ 、V in- A successive approximation conversion circuit is added that performs successive approximation conversion of 1 bit at a time; After successive approximation conversion, V in+ 、V in- Comparator 1 converts the binary digital code into 1 bit; The digital synthesis module adds the 1-bit binary digital code before the highest bit of the M*(n-1)+1-bit binary digital code during digital synthesis.

6. The pipelined analog-to-digital converter according to claim 5, wherein: The successive approximation conversion circuit includes four capacitors CP11~CP14 and four switches K11~K14; one end of CP11 and CP12 is used to receive the sampled V in+ The other end is connected to one end of K11 and K12 with an electric control switch key, and the other ends of K11 and K12 for selective connection of the corresponding electric control switch key are connected to the reference voltage V REF and ground; one end of CP13 and CP14 is used to receive the sampled V in- The other end is connected to one end of K13 and K14 with an electric control switch key, and the other ends of K13 and K14 for selective connection of the corresponding electric control switch key are connected to V REF and land; In the initial state of the pipelined ADC, one of K11, K12, and K13, K14 is grounded, and the other is connected to V REF When the binary code output by comparator 1 is 1, K11 and K12 are all grounded, and K13 and K14 are all connected to V REF When the binary code output by comparator 1 is 0, K11 and K12 are all connected to V REF , K13 and K14 are all grounded.

7. The pipelined analog-to-digital converter according to claim 5, wherein: The pipelined analog-to-digital converter further comprises: For each quantization stage before the last two stages of quantization, a common-mode detection circuit is added to perform common-mode detection on the input signal before quantization of the corresponding Flash-ADC. For each level of quantization between the first level of quantization and the last level of quantization, a voltage compensation circuit is added to compensate for the common-mode voltage output by the previous level of common-mode detection circuit: when the common-mode voltage is too high, the voltage compensation circuit compensates the common-mode voltage downward; when the common-mode voltage is too low, the voltage compensation circuit compensates the common-mode voltage upward.

8. The pipelined analog-to-digital converter according to claim 7, wherein: Each common mode detection circuit is a comparator 2, the two comparison terminals of which are respectively connected to the input signal before quantization by the corresponding Flash-ADC of the current stage, and the output of which is also a 1-bit binary digital code; each voltage compensation circuit includes 4 compensation capacitors C i,1 ~C i,4 Each voltage compensation circuit is equipped with a decoder, i represents the level number of the quantization circuit; the input of each decoder is the 1-bit binary digital code CMi output by the comparator 2, which is converted into a 4-bit binary digital code and respectively connected to the 4 compensation capacitors C of the i+1th level quantization circuit i+1,1 ~C i+1,4 The lower plate; in the initial state of the pipelined ADC, the four compensation capacitors C i1 , C i3 The lower plate of C i2 , C i4 The lower plate of CM is connected to low level; i-1 =1, indicating that the common mode voltage VPi and VNi of the i-1th level are too high. i1 ~C i4 All are 0, achieving downward compensation of common mode voltages VPi and VNi; When CMi=0, it means that the common mode voltage VPi and VNi of the i-1th level are too low. At this time, the compensation capacitor C i1 ~C i4 All are 1, achieving upward compensation of common-mode voltages VPi and VNi.

9. The pipelined analog-to-digital converter according to claim 8, wherein: Except for the last two stages of quantization circuits, each of the remaining stages of quantization circuits includes a residual amplifier that performs residual amplification on the input signal before quantization by the Flash-ADC of the current stage and then outputs VPi and VNi.

10. The pipelined analog-to-digital converter according to claim 8, wherein: M is 5 and n is 2.

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