SOM memory device and manufacturing method thereof
By optimizing the etching process and using multiple repeated OTS etching and post-etching rinses, the initial element segregation problem of SOM memory devices was solved, the reliability and stability were improved, and the power consumption was reduced.
Patent Information
- Application Number
- CN202510761312.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-09
- Publication Date
- 2025-09-12
AI Technical Summary
Existing SOM memory devices have element segregation in the initial state, which causes threshold voltage difference fluctuation and narrowing of the operating window, affecting reliability and stability.
By optimizing the etching process and adopting a cyclic process of repeated OTS etching and post-etching rinsing, charge accumulation and internal electric field interference are eliminated, and uniform distribution of elements is promoted.
The reliability and stability of SOM memory devices are significantly improved, the read and write margin and the stability of the operation window are enhanced, and the power consumption is reduced.
Smart Images
Figure CN120640694A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular to a SOM memory device and a manufacturing method thereof. Background Art
[0002] With the rapid development of artificial intelligence technology, computing systems have increasingly stringent requirements on memory performance, especially in terms of high speed, high density, low power consumption and non-volatility, which have put forward higher requirements for DRAM and new non-volatile memories. In this context, selector only memory devices (SOM memory devices) have become a highly promising solution due to their unique performance advantages. Compared with traditional 3D XPoint (3D XPT) memory, SOM memory devices have the characteristics of simple structure, high scalability (down to 10nm node), ultra-fast SET / RESET speed, excellent cycle life (cycle life>10^8 times), vertical stacking capability and no thermal effect write crosstalk. They have shown significant advantages in high-bandwidth storage scenarios such as CXL (Compute ExpressLink) and HBM (High Bandwidth Memory).
[0003] like Figure 1 As shown, the three-dimensional stackable SOM memory device is based on oxide threshold switch (Ovonic Threshold Switch, referred to as OTS) materials. By applying reverse voltage / current pulses, it can switch between SET (low resistance state) and RESET (high resistance state). Its state distinction depends on the threshold voltage difference (ΔVt) between the two states. Its core working mechanism is: in SET operation, the internal elements (such as elements A and B) undergo directional migration under the drive of the electric field (such as element A enriched at the top and element B migrated to the bottom), forming an asymmetric distribution; while in RESET operation, the elements reverse migration to restore a nearly uniform distribution, thereby achieving reversible resistance state switching.
[0004] However, SOM memory devices manufactured using existing preparation processes already have abnormal element segregation (i.e., uneven distribution of elements A and B) when in an unoperated state (i.e., initial state). The unevenness of the elements in the initial state seriously interferes with the element migration baseline of the SET / RESET operation, resulting in fluctuations in the threshold voltage difference of the SOM memory device and a narrowing of the operating window, which seriously affects the reliability and stability of the SOM memory device. Summary of the Invention
[0005] Based on the above problems, the present application provides a SOM memory device and a manufacturing method thereof, the purpose of which is to optimize the etching process steps of the SOM memory device, eliminate charge accumulation and internal electric field interference during the etching process, thereby improving the uniformity of the initial state element distribution of the SOM memory device, and thus enhancing the reliability and stability of the SOM memory device.
[0006] The embodiments of this application disclose the following technical solutions:
[0007] In a first aspect of the present application, a method for manufacturing a SOM memory device is provided, the method comprising:
[0008] Preparing an initial stacked structure; the initial stacked structure includes a first wire layer, a first electrode layer, an OTS layer, and a second electrode layer stacked along a first direction;
[0009] Performing a first etching operation on the initial stacked structure to form a plurality of intermediate stacked structures from the initial stacked structure; the plurality of intermediate stacked structures extend along a second direction and are parallel to each other in a third direction, and the first direction, the second direction, and the third direction are perpendicular to each other;
[0010] performing a second etching operation on the plurality of intermediate stacked structures to form a plurality of memory cells spaced apart from each other in the second direction;
[0011] The second etching operation includes: performing repeated OTS etching on the OTS layers in the plurality of intermediate stacked structures along a direction opposite to the first direction using a target bias voltage.
[0012] In an optional implementation, after the first etching operation and before the second etching operation, the manufacturing method further includes:
[0013] preparing a second conductive line layer on the plurality of intermediate laminate structures;
[0014] The second etching operation further includes:
[0015] The second conductive line layer is etched into a plurality of second conductive lines extending along the second direction and spaced apart in the third direction, so that the second conductive lines connect the plurality of storage units.
[0016] In an optional implementation, the OTS etching includes dry etching and post-etching rinsing.
[0017] In an optional implementation, during the multiple repeated OTS etchings, a target bias voltage of a subsequent dry etching is smaller than a target bias voltage of a previous dry etching.
[0018] In an optional implementation, during the multiple repeated OTS etchings, the etching time of the subsequent dry etching is longer than the etching time of the previous dry etching.
[0019] In an optional implementation, the post-etch rinse is used to:
[0020] The etched intermediate stack structure is flushed by introducing an inert gas to dissipate the charge accumulated in the hard mask of the etched intermediate stack structure.
[0021] In an optional implementation, the gas flow rate of the inert gas ranges from 100 sccm to 200 sccm.
[0022] In an optional implementation, the duration of the post-etching rinse is in the range of 2.5s-10s.
[0023] In an optional implementation, before performing a second etching operation on the plurality of intermediate stacked structures to form the plurality of intermediate stacked structures into a plurality of memory cells spaced apart from each other in the second direction, the method further includes:
[0024] The number of etching times of the OTS etching is determined based on the thickness and material properties of the OTS layer.
[0025] In a second aspect of the present application, a SOM memory device is provided. The SOM memory device is manufactured by the method for manufacturing the SOM memory device described in any one of the above embodiments.
[0026] Compared with the existing technology, this application has the following beneficial effects:
[0027] In the technical solution of the present application, an initial stacked structure is first prepared, wherein the initial stacked structure includes a first wire layer, a first electrode layer, an OTS layer, and a second electrode layer stacked along a first direction; secondly, a first etching operation is performed on the initial stacked structure to form a plurality of intermediate stacked structures from the initial stacked structure, wherein the plurality of intermediate stacked structures extend along a second direction and are parallel to each other in a third direction, and the first direction, the second direction, and the third direction are perpendicular to each other; then, a second etching operation is performed on the plurality of intermediate stacked structures to form a plurality of storage cells spaced from each other in the second direction; because the second etching operation uses a target bias voltage to perform multiple repeated OTS etchings on the OTS layers in the plurality of intermediate stacked structures in a direction opposite to the first direction, the charge accumulation and internal electric field interference of the SOM memory device are effectively eliminated through the multi-step cyclic etching process, thereby promoting the uniform distribution of elements within the SOM memory device, thereby significantly improving the reliability and stability of the SOM memory device.
[0028] In addition, the present application performs a cyclic etching process of multiple dry etching and post-etching flushing in steps, which can gradually reduce the target bias voltage during the etching stage to suppress charge injection, and performs post-etching flushing after each step of dry etching to remove residual charge, thereby eliminating charge accumulation and internal electric field interference in the SOM memory device during the etching process, thereby effectively improving the uniformity of the initial state element distribution of the SOM memory device, and further improving the read and write margin and operating window stability of the SOM memory device, thereby significantly improving the reliability of the SOM memory device.
[0029] This application achieves a performance breakthrough in SOM memory devices through process optimization rather than structural modification. It does not require additional processes and has a low impact on costs, thereby providing a highly consistent and low-power technical solution for SOM memory device manufacturing scenarios. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.
[0031] Figure 1 A schematic structural diagram of a three-dimensionally stackable SOM memory device provided in an embodiment of the present application;
[0032] Figure 2a A schematic diagram of the distribution of elements A and B in an unoperated SOM memory device provided in an embodiment of the present application;
[0033] Figure 2b A schematic diagram of the distribution of elements A and B in a SOM memory device after BL etching provided in an embodiment of the present application;
[0034] Figure 2c A schematic diagram of the distribution of elements A and B in a SOM memory device after WL etching provided in an embodiment of the present application;
[0035] Figure 3 A flow chart of an existing one-step WL etching process provided in an embodiment of the present application;
[0036] Figure 4 A flow chart of a method for manufacturing a SOM memory device provided in an embodiment of the present application;
[0037] Figure 5 A flowchart of another method for manufacturing a SOM memory device provided in an embodiment of the present application;
[0038] Figure 6 A flowchart of a method for manufacturing a SOM memory device according to an embodiment of the present application;
[0039] Figure 7 A flow chart of a two-step etching process for a SOM memory device provided in an embodiment of the present application. DETAILED DESCRIPTION
[0040] As described above, the SOM memory devices manufactured by the current preparation process already have abnormal element segregation (i.e., uneven element distribution) when in the non-operated state (i.e., initial state). The unevenness of the elements in the initial state seriously interferes with the element migration baseline of the SET / RESET operation, resulting in fluctuations in the threshold voltage difference of the SOM memory device and a narrowing of the operating window, which seriously affects the reliability and stability of the SOM memory device.
[0041] After research, the inventors found that the root cause of element segregation is the defect of WL (full name: Word Line) etching process. First, the inventors found that the A and B elements in the unoperated SOM memory device have obvious segregation phenomenon: Figure 2a As shown in the figure, element A is enriched in the lower part of the SOM memory device, while element B is enriched in the upper part of the SOM memory device. Secondly, the inventors found that after BL (full name Bit Line, i.e. bit line) etching, there is no obvious segregation of elements A and B: Figure 2b As shown in FIG, the two elements AB are evenly distributed in the SOM memory device; however, after WL etching, the inventors found that the two elements A and B showed obvious segregation phenomenon: Figure 2c As shown, elements A and B showed obvious segregation and aggregation in the SOM memory device, and their segregation direction was similar to that of the SOM memory device in the initial state, that is, the content of element A was higher at the bottom of the SOM memory device, while the content of element B was higher at the top of the SOM memory device.
[0042] The inventor found that the existing technology uses Figure 3 The one-step WL etching process shown in the figure rapidly etches the OTS layer of the SOM memory device at a relatively high bias voltage (e.g., 200V-400V), causing a large amount of charge to accumulate at the top of the word line and become unable to be extracted. Moreover, the one-step etching process cannot effectively neutralize the residual charge, resulting in charge accumulation and strong internal electric field interference, which drives the charged elements (such as A / B) in the OTS material to migrate even without external operation, causing the initial state of the SOM memory device to exhibit a non-uniform distribution, further exacerbating the electric field-induced element segregation. This not only reduces the stability of the operating window of the SOM memory device, but also leads to increased electrical parameter variations between SOM memory devices, seriously affecting the reliability and stability of the SOM memory device.
[0043] To solve the above problems, the inventors have proposed a method for manufacturing a SOM memory device, which includes first preparing an initial stacked structure, wherein the initial stacked structure includes a first wire layer, a first electrode layer, an OTS layer, and a second electrode layer stacked along a first direction; secondly performing a first etching operation on the initial stacked structure to form a plurality of intermediate stacked structures from the initial stacked structure, wherein the plurality of intermediate stacked structures extend along a second direction and are parallel to each other in a third direction, and the first direction, the second direction, and the third direction are perpendicular to each other; then performing a second etching operation on the plurality of intermediate stacked structures to form a plurality of memory cells spaced apart from each other in the second direction; because the second etching operation uses a target bias voltage to perform multiple repeated OTS etchings on the OTS layers in the plurality of intermediate stacked structures in a direction opposite to the first direction, the multi-step cyclic etching process effectively eliminates charge accumulation and internal electric field interference in the SOM memory device, promotes uniform distribution of elements within the SOM memory device, and thus significantly improves the reliability and stability of the SOM memory device.
[0044] In addition, the present application performs a cyclic etching process of multiple dry etching and post-etching flushing in steps, which can gradually reduce the target bias voltage during the etching stage to suppress charge injection, and performs post-etching flushing after each step of dry etching to remove residual charge, thereby eliminating charge accumulation and internal electric field interference in the SOM memory device during the etching process, thereby effectively improving the uniformity of the initial state element distribution of the SOM memory device, and further improving the read and write margin and operating window stability of the SOM memory device, thereby significantly improving the reliability of the SOM memory device.
[0045] This application achieves a performance breakthrough in SOM memory devices through process optimization rather than structural modification. It does not require additional processes and has a low impact on costs, thereby providing a highly consistent and low-power technical solution for SOM memory device manufacturing scenarios.
[0046] The manufacturing method of a SOM memory device provided in the present application can be applied to the field of semiconductor technology. The above is only an example and does not limit the application field of the manufacturing method of a SOM memory device provided in the present application.
[0047] It should be noted that the manufacturing method of a SOM memory device provided in this application can be applied to a novel three-dimensionally stackable SOM memory array, and can also be applied to other SOM memory devices with an OTS layer, so no specific limitation is made here.
[0048] The terms "first", "second", "third" and "fourth" in the specification, claims and drawings of this application are used to distinguish different objects rather than to limit a specific order.
[0049] In the embodiments of this application, words such as "as an example" or "for example" are used to indicate examples, illustrations, or explanations. Any embodiment or design described in the embodiments of this application as "as an example" or "for example" should not be interpreted as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "as an example" or "for example" is intended to present the relevant concepts in a concrete manner.
[0050] The terms used in the implementation section of this application are only used to explain the specific embodiments of this application and are not intended to limit this application.
[0051] Keyword definitions:
[0052] OTS (ovonic threshold switching) is a core component of three-dimensional high-density memory devices, playing a key role in suppressing crosstalk and driving memory cells. Typical compositions include Ge-Se-Sb (such as GeSe / SbTe), As-Te-Si-based chalcogenides, and may be doped with elements such as Sn and N to optimize stability.
[0053] In order to help those skilled in the art better understand the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of this application.
[0054] See also Figure 4 , which is a flow chart of a method for manufacturing a SOM memory device provided in an embodiment of the present application, the process includes the following steps:
[0055] Step S401: preparing an initial stacked structure.
[0056] In step S401 , an initial stacked structure includes a first wire layer, a first electrode layer, an OTS layer, and a second electrode layer stacked along a first direction.
[0057] In the embodiment of the present application, the initial stacked structure includes a first conductor layer stacked along a first direction layer (i.e., the Z-axis direction in the three-dimensional coordinate system, which is perpendicular to the horizontal plane). Figure 1 The BL layer shown in FIG, the first electrode layer is Figure 1 The BE:CN layer shown in FIG, the second electrode layer is Figure 1 In the TE (i.e., Top Electrode) layer shown in FIG, the OTS layer is located between the BE:CN layer and the TE layer.
[0058] Step S402 : performing a first etching operation on the initial stacked structure to form a plurality of intermediate stacked structures from the initial stacked structure.
[0059] In step S402, a plurality of intermediate stacked structures extend along the second direction (ie, the Y-axis direction in the three-dimensional coordinate system) and are parallel to each other in the third direction (ie, the X-axis direction in the three-dimensional coordinate system), and the first direction, the second direction, and the third direction are perpendicular to each other.
[0060] In the embodiment of the present application, by performing a first etching operation (such as dry etching) on the initial stacked structure, the initial stacked structure can be formed into Figure 3 Several intermediate stacked structures are shown in Figure b.
[0061] Furthermore, after the first etching operation is performed, a second conductive line layer (ie Figure 1 The WL layer shown in ).
[0062] Step S403 , performing a second etching operation on the plurality of intermediate stacked structures to form the plurality of intermediate stacked structures into a plurality of memory cells spaced apart from each other in a second direction.
[0063] In step S403, the second etching operation includes: performing multiple repeated OTS etchings along the direction opposite to the first direction on the OTS layers in the plurality of intermediate stacked structures using a target bias voltage, wherein the OTS etching includes dry etching and post-etching rinsing.
[0064] In an embodiment of the present application, a second etching operation can be performed on a plurality of intermediate stacked structures by a dry etching device (e.g., an ICP device, full name Inductively Coupled Plasma, inductively coupled plasma etcher). Specifically, the OTS layer in the intermediate stacked structure is subjected to repeated OTS etching in a direction opposite to the first direction using a target bias voltage by the dry etching device, so that the intermediate stacked structures form a plurality of storage cells in which the internal elements are in a uniformly distributed state, thereby achieving a multi-step cyclic etching process to effectively eliminate the charge accumulation and internal electric field interference of the SOM memory device, promote the uniform distribution of the internal elements of the SOM memory device, and thus significantly improve the reliability and stability of the SOM memory device.
[0065] In an optional implementation, the second etching operation further includes etching the second conductive line layer into a plurality of second conductive lines extending along the second direction and spaced apart in the third direction, so that the second conductive lines connect a plurality of storage units.
[0066] In the embodiment of the present application, a second conductor layer (i.e., WL layer) is subjected to repeated OTS etching in the direction opposite to the first direction by using a dry etching device with a target bias voltage, thereby forming a plurality of second conductors (i.e., WL layers) extending in the second direction and spaced apart in the third direction on the plurality of intermediate stacked structures. Figure 1 ), so that the second conductive line connects several memory cells, avoiding the problems of over-etching and structural damage, thereby improving the reliability of the word line connection, and further improving the reliability and stability of the SOM memory device.
[0067] Optionally, in an embodiment of the present application, during the process of performing multiple repeated OTS etchings, the target bias voltage of the subsequent dry etching is less than the target bias voltage of the previous dry etching, wherein the target bias voltage ranges from 100V to 200V.
[0068] In order to solve the technical problem that a large amount of charge is accumulated on the top of the word line and cannot be extracted by rapidly etching the OTS layer of the SOM memory device at a relatively high bias voltage (e.g., 200V-400V) in the prior art, in the embodiment of the present application, the dry etching equipment can perform a multi-step etching process and a low bias voltage (i.e., a target bias voltage in the range of 100V-200V) on the word line. Figure 5 The OTS layers of the several intermediate stacked structures shown are dry-etched. For example, if the target bias voltage of the ICP device during the first dry etching is set to 200V, the target bias voltage during the second dry etching is set to 150V, and the target bias voltage during the third dry etching is set to 100V, thereby reducing the power of the dry etching, reducing the ion generation rate during the etching process, and reducing the ion bombardment energy. Further, when forming several storage units on the several intermediate stacked structures, charge injection is suppressed, and charge accumulation and internal electric field interference of the SOM storage device are eliminated.
[0069] Optionally, in the process of performing multiple repeated OTS etchings, the etching time of the subsequent dry etching is longer than the etching time of the previous dry etching. For example, if the etching time of the ICP equipment for the first dry etching is 10 minutes, the etching time for the second dry etching can be 15 minutes, thereby avoiding the problem of over-etching of the OTS layer (i.e., excessive removal of the OTS layer) due to too fast an etching rate, thereby improving the reliability, stability and manufacturing yield of the SOM memory device.
[0070] In order to effectively neutralize the residual charge on the intermediate stacked structure after etching, so as to further eliminate the charge accumulation of the SOM memory device during the etching process, in an embodiment of the present application, the dry etching equipment can perform a flushing operation on the intermediate stacked structure after etching through chemical substances or physical methods to remove the residual charge on the intermediate stacked structure after etching.
[0071] Specifically, if the flushing operation is performed by a physical method, the dry etching equipment can flush the etched intermediate stack structure by introducing an inert gas to dissipate the charge accumulated in the hard mask of the etched intermediate stack structure. Figure 5 Gases such as Ar, He, and N2 are shown in FIG.
[0072] Optionally, when the device performs the flushing operation by a physical method, the gas flow rate of the inert gas ranges from 100 sccm to 200 sccm, and the flushing time of the post-etching flushing ranges from 2.5 s to 10 s.
[0073] To address the charge accumulation issue caused by existing one-step WL etching and effectively balance etching efficiency with SOM memory device reliability, in an embodiment of the present application, the dry etching equipment can determine the number of OTS etching passes based on the thickness and material properties of the OTS layer before performing a second etching operation on the plurality of intermediate stacked structures to form a plurality of memory cells spaced apart in a second direction. For example, if the OTS layer is 100 nanometers thick and its material properties indicate a high etching rate at a high bias voltage but a high tendency to cause charge accumulation, the ICP equipment can set the number of etching passes to 2 based on this data, gradually reducing the bias voltage to reduce the impact of charge and ensure uniformity of the WL etching.
[0074] In an optional embodiment, the dry etching equipment performs two-step etching: Figure 6 As shown, the dry etching is performed by a first target bias voltage for a first dry etching and a second target bias voltage for a second dry etching, wherein the first target bias voltage is greater than the second target bias voltage, and the etching time of the second dry etching is greater than the etching time of the first dry etching. The method specifically includes the following steps:
[0075] Step S601: preparing an initial stacked structure.
[0076] In step S601 , an initial stacked structure includes a first wire layer, a first electrode layer, an OTS layer, and a second electrode layer stacked along a first direction.
[0077] In the embodiment of the present application, the initial stacked structure includes a first conductor layer stacked along a first direction layer (ie, the Z-axis direction in the three-dimensional coordinate system, which is perpendicular to the horizontal plane). Figure 1 The BL layer shown in FIG, the first electrode layer is Figure 1 The BE:CN layer shown in FIG, the second electrode layer is Figure 1 In the TE (i.e., Top Electrode) layer shown in FIG, the OTS layer is located between the BE:CN layer and the TE layer.
[0078] Step S602 : performing a first etching operation on the initial stacked structure to form a plurality of intermediate stacked structures from the initial stacked structure.
[0079] In step S602, a plurality of intermediate stacked structures extend along the second direction (i.e., the Y-axis direction in the three-dimensional coordinate system) and are parallel to each other in the third direction (i.e., the X-axis direction in the three-dimensional coordinate system), and the first direction, the second direction, and the third direction are perpendicular to each other.
[0080] In the embodiment of the present application, by performing a first etching operation (such as dry etching) on the initial stacked structure, the initial stacked structure can be formed into Figure 3 Several intermediate stacked structures are shown in Figure b.
[0081] Furthermore, after the first etching operation, a second conductive line layer (ie Figure 1 The WL layer shown in ).
[0082] In step S603, a first target bias voltage is used to perform a first dry etching on the OTS layer of the plurality of intermediate stacked structures in a direction opposite to the first direction, and an inert gas is introduced to flush the plurality of intermediate stacked structures after the first etching to remove residual charges on the plurality of intermediate stacked structures after etching.
[0083] In the embodiment of the present application, the dry etching equipment can perform a first dry etching on the OTS layer of the plurality of intermediate stacked structures along the opposite direction of the first direction by using a first target bias voltage to form Figure 7 Then, an inert gas is introduced to flush the plurality of intermediate stacked structures after the first etching to remove residual charges on the plurality of intermediate stacked structures after etching.
[0084] Optionally, the first target bias voltage ranges from 100V to 200V.
[0085] It should be noted that by dry etching the OTS layers of several intermediate stacked structures using a low bias voltage (i.e., a first target bias voltage in the range of 100V-200V), the etching power is reduced, thereby reducing the ion generation rate during the etching process, reducing the ion bombardment energy, and then suppressing charge injection, eliminating charge accumulation in the SOM memory device.
[0086] In an embodiment of the present application, the dry etching equipment may perform a flushing operation on the plurality of intermediate stacked structures after the first etching by using chemical substances or physical methods to remove residual charges on the plurality of intermediate stacked structures after the first etching.
[0087] Alternatively, if the flushing operation is performed by a physical method, the dry etching apparatus may flush the intermediate stacked structures after the first etching by introducing an inert gas such as Ar, He, or N2 to remove residual charge on the intermediate stacked structures after the first etching. The inert gas flow rate range is 100 sccm-200 sccm.
[0088] It should be noted that flushing the intermediate stacked structures formed after the first etching by chemical substances or physical methods effectively neutralizes the residual charges on the intermediate stacked structures after the first etching, further eliminating the charge accumulation of the SOM memory device during the etching process.
[0089] In step S604, a second target bias voltage is used to perform a second dry etching on the OTS layer of the plurality of intermediate stacked structures after flushing in a direction opposite to the first direction, and an inert gas is introduced to flush the plurality of intermediate stacked structures after the second etching, so that the plurality of intermediate stacked structures form a plurality of storage cells spaced apart from each other in the second direction.
[0090] In the embodiment of the present application, the dry etching equipment can perform a second dry etching on the OTS layer of the washed intermediate stacked structures in the opposite direction of the first direction through a second target bias voltage, and introduce an inert gas to wash the intermediate stacked structures after the second etching, so that the intermediate stacked structures are formed. Figure 7 Several memory cells are shown spaced apart from each other in the second direction.
[0091] Optionally, the second target bias voltage ranges from 100 V to 200 V. The second target bias voltage is smaller than the first target bias voltage.
[0092] It should be noted that the bias voltage is gradually reduced during the etching stage to suppress charge injection, and a flushing operation is performed after each etching step to remove residual charge, thereby eliminating charge accumulation and internal electric field interference in the SOM memory device during the etching process, thereby improving the uniformity of the initial state element distribution of the SOM memory device, and further improving the read and write margin and operating window stability of the SOM memory device, significantly improving the reliability of the SOM memory device.
[0093] In an optional embodiment, the two-step etching method in the embodiment of the present application has a significant improvement in the top-bottom content difference of element A and element B compared to the traditional one-step etching method. For details, see the element content difference shown in Table 1. The difference of element A is optimized from 33% to 11%, and the difference of element B is optimized from 30% to 5%.
[0094] Table 1
[0095]
[0096] The manufacturing method of the SOM memory device provided by the embodiment of the present application effectively eliminates the charge accumulation and internal electric field interference of the SOM memory device through a multi-step cyclic etching process, promotes the uniform distribution of elements within the SOM memory device, and thus significantly improves the reliability and stability of the SOM memory device. In addition, the present application performs a cyclic etching process of multiple etching and post-etching flushing in steps, which can gradually reduce the target bias voltage during the etching stage to suppress charge injection, and performs a post-etching flush after each etching step to remove residual charge, eliminating the charge accumulation and internal electric field interference of the SOM memory device during the word line etching process, thereby effectively improving the uniformity of the initial state element distribution of the SOM memory device, thereby improving the read and write margin and operating window stability of the SOM memory device, and significantly improving the reliability of the SOM memory device.
[0097] In addition, this application achieves a performance breakthrough in SOM memory devices through process optimization rather than structural modification, does not require additional processes, and has a low impact on costs, thereby providing a highly consistent, low-power technical solution for SOM memory device manufacturing scenarios.
[0098] An embodiment of the present application further provides a SOM memory device, wherein the SOM memory device can be manufactured by the method for manufacturing the SOM memory device described in any of the above embodiments.
[0099] It should be noted that the various embodiments in this specification are described in a progressive manner. The same or similar parts between the various embodiments can be referred to in detail. Each embodiment focuses on the differences from other embodiments. Ordinary technicians in this field can understand and implement them without any creative work.
[0100] The above is only one specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.
Claims
1. A method for manufacturing a SOM memory device, characterized in that: include: Preparing an initial stacked structure; the initial stacked structure includes a first wire layer, a first electrode layer, an OTS layer, and a second electrode layer stacked along a first direction; Performing a first etching operation on the initial stacked structure to form a plurality of intermediate stacked structures from the initial stacked structure; the plurality of intermediate stacked structures extend along a second direction and are parallel to each other in a third direction, and the first direction, the second direction, and the third direction are perpendicular to each other; performing a second etching operation on the plurality of intermediate stacked structures to form a plurality of memory cells spaced apart from each other in the second direction; The second etching operation includes: performing repeated OTS etching on the OTS layers in the plurality of intermediate stacked structures along a direction opposite to the first direction using a target bias voltage.
2. The manufacturing method according to claim 1, characterized in that After the first etching operation and before the second etching operation, the method further includes: preparing a second conductive line layer on the plurality of intermediate laminate structures; The second etching operation further includes: The second conductive line layer is etched into a plurality of second conductive lines extending along the second direction and spaced apart in the third direction, so that the second conductive lines connect the plurality of storage units.
3. The manufacturing method according to claim 1, characterized in that The OTS etching includes dry etching and post-etching rinsing.
4. The manufacturing method according to claim 3, characterized in that During the multiple repeated OTS etchings, the target bias voltage of the subsequent dry etching is smaller than the target bias voltage of the previous dry etching.
5. The manufacturing method according to claim 4, characterized in that During the multiple repeated OTS etchings, the etching time of the subsequent dry etching is longer than the etching time of the previous dry etching.
6. The manufacturing method according to claim 3, characterized in that The post-etch rinse is used to: The etched intermediate stack structure is flushed by introducing an inert gas to dissipate the charge accumulated in the hard mask of the etched intermediate stack structure.
7. The manufacturing method according to claim 6, characterized in that The gas flow rate of the inert gas is in the range of 100 sccm-200 sccm.
8. The manufacturing method according to claim 6, characterized in that The duration of the post-etching rinse is in the range of 2.5s-10s.
9. The manufacturing method according to claim 1, characterized in that Before performing a second etching operation on the plurality of intermediate stacked structures to form the plurality of intermediate stacked structures into a plurality of memory cells spaced apart from each other in the second direction, the method further includes: The number of etching times of the OTS etching is determined based on the thickness and material properties of the OTS layer.
10. A SOM memory device, characterized in that: The method is prepared by any one of claims 1 to 9.