Flip high-voltage light-emitting diode chip and preparation method thereof

Abstract

The invention relates to the technical field of LED chips, and discloses a flip high-voltage light-emitting diode chip and a preparation method thereof.The flip high-voltage light-emitting diode chip comprises a substrate and an epitaxial structure stacked on the substrate, the epitaxial structure comprises an epitaxial layer, an N-type conductive step and an isolation groove are formed in the epitaxial layer, and the N-type conductive step and the isolation groove are formed in the epitaxial layer; the epitaxial structure is provided with an isolation groove, the isolation groove divides the epitaxial structure into a plurality of independent light-emitting units, the adjacent light-emitting units are electrically connected through a connecting layer, a reflecting layer and an insulating layer are arranged on the epitaxial layer, the insulating layer covers the reflecting layer and is filled in the isolation groove, the included angle between every two adjacent light-emitting units and the included angle of the isolation groove are alpha, the insulating layer comprises a first insulating layer located in the isolation groove, the included angle of the first insulating layer is theta, and alpha is larger than theta. According to the invention, the antistatic breakdown capability of the LED chip can be greatly improved on the basis of improving the luminance of the LED chip.

Description

Technical Field

[0001] The present invention relates to the technical field of LED chips, and in particular to a flip-chip high-voltage light-emitting diode chip and a preparation method thereof. Background Art

[0002] Light-emitting diode (LED) chips, with their advantages of high energy efficiency, long lifespan, and environmental friendliness, have found widespread application in fields such as lighting, displays, and automotive electronics. With the development of the LED industry, and to reduce packaging costs, the industry has gradually shifted from connecting multiple LED chips in series during the packaging process to a series structure formed by directly integrating multiple LED chips during the chip preparation phase. While this integration method simplifies the packaging process, connecting multiple LED chips in series at the chip end reduces the spacing between individual LED chips, resulting in more severe electrostatic interference issues for the entire LED chip during operation. Improving the anti-static breakdown capabilities of these integrated LED chips has become a key technical challenge that the industry urgently needs to address.

[0003] Currently, some researchers are trying to improve the anti-static breakdown capability of LED chips by reducing the angle of the isolation grooves between adjacent individual light-emitting units. However, this method significantly compresses the effective light-emitting area of ​​each light-emitting unit, resulting in a decrease in the overall brightness of the chip, making it difficult to simultaneously meet the market's dual demands for high anti-static performance and high brightness in LED chips. Therefore, how to improve the anti-static breakdown capability of LED chips while maximizing the actual light-emitting area and overall brightness of each light-emitting unit is a technical bottleneck that urgently needs to be overcome in the current LED chip field. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a flip-chip high-voltage light-emitting diode chip and a preparation method thereof, which can significantly improve the anti-static breakdown capability of the LED chip while improving its luminous brightness.

[0005] In order to solve the above technical problems, the present invention provides a first aspect of a flip-chip high-voltage light-emitting diode chip, comprising a substrate and an epitaxial structure stacked on the substrate; The epitaxial structure includes an epitaxial layer, an N-type conductive step and an isolation trench formed on the epitaxial layer, the isolation trench separating the epitaxial structure into a plurality of independent light-emitting units, adjacent light-emitting units being electrically connected via a connection layer, a reflective layer and an insulating layer provided on the epitaxial layer, the insulating layer covering the reflective layer and filling the isolation trench, a first opening penetrating through the N-type conductive step and a second opening penetrating through the reflective layer in an adjacent light-emitting unit formed on the insulating layer, one end of the connection layer being connected to the N-type conductive step via the first opening, and the other end being connected to the reflective layer via the second opening; A Bragg reflective layer and a pad layer are provided on the insulating layer, and the pad layer passes through the Bragg reflective layer and contacts the reflective layer and the epitaxial layer in the adjacent light emitting unit respectively; The included angle of the isolation trench between two adjacent light-emitting units is α, the insulating layer includes a first insulating layer located in the isolation trench, the included angle of the first insulating layer is θ, and α>θ.

[0006] As an improvement of the above solution, the epitaxial layer includes an N-type semiconductor layer, an active layer and a P-type semiconductor layer stacked in sequence on the substrate; The pad layer includes a P-type pad layer and an N-type pad layer, wherein the P-type pad layer and the N-type pad layer are located on two adjacent light-emitting units and are electrically connected via a connecting layer; A third opening penetrating the reflective layer and a fourth opening penetrating the N-type semiconductor layer in an adjacent light-emitting unit are formed on the Bragg reflective layer. The P-type pad layer contacts the reflective layer through the third opening. The N-type pad layer is arranged along the Bragg reflective layer, with one end thereof being located on the Bragg reflective layer corresponding to the second opening, and the other end being in contact with the N-type semiconductor layer in the adjacent light-emitting unit through the fourth opening.

[0007] As an improvement to the above solution, the following is satisfied: 40°≤α-θ≤60°.

[0008] As an improvement of the above solution, the angle α is 65°-85°.

[0009] As an improvement of the above solution, the angle θ is 15°-40°.

[0010] As an improvement of the above solution, the insulating layer is a SiO2 layer; The connection layer includes an Al layer, a Ti layer, a Ni layer, an Au layer and a Ti layer stacked in sequence.

[0011] Accordingly, the second aspect of the present invention further provides a method for preparing the flip-chip high-voltage light-emitting diode chip, comprising: providing a substrate, and preparing an epitaxial layer on the substrate; preparing a reflective layer on the epitaxial layer; Etching the epitaxial layer not covered by the reflective layer to form an N-type conductive step; Etching the surface of the N-type conductive step to form an isolation groove with an angle of α, thereby separating the epitaxial layer into a plurality of independent light-emitting units; An insulating layer is prepared on the reflective layer and the area uncovered by the reflective layer, and the insulating layer is subjected to photolithography and etching to form a first opening penetrating the N-type conductive step and a second opening penetrating the reflective layer in an adjacent light-emitting unit, and a first insulating layer with an angle θ is formed in the isolation trench, where α>θ; A continuous connection layer is formed on the surface of the region between the first opening, the first insulating layer, and the second opening to electrically connect adjacent light-emitting units; preparing a Bragg reflection layer on the surfaces of the insulating layer and the connecting layer; A pad layer is prepared on the Bragg reflection layer.

[0012] As an improvement to the above solution, the insulating layer is subjected to photolithography and etching to form a first opening penetrating to the N-type conductive step and a second opening penetrating to the reflective layer in an adjacent light-emitting unit, and a first insulating layer with an angle θ is formed in the isolation trench, including: coating a photoresist on the surface of the insulating layer and performing an exposure process using a photomask; The photoresist after exposure is removed by development, and a sloped photoresist opening is formed on the insulating layer filled in the isolation groove; Etching the insulating layer to remove the remaining photoresist, thereby forming a first opening extending through the N-type conductive step and a second opening extending through the reflective layer; Etching the sloped photoresist opening to obtain a first insulating layer with an angle of θ; In which, the light mask includes a fully transparent area, a semi-transparent area and a shading area, the fully transparent area includes a first fully transparent area and a second fully transparent area, the first fully transparent area is used to form the first opening, the second fully transparent area is used to form the second opening, the semi-transparent area is used to form the first insulating layer with an angle, and the semi-transparent area is composed of transparent units and shading units arranged alternately.

[0013] As an improvement to the above solution, the width of the light-transmitting unit is equal to the width of the light-shielding unit, and the width is 2 μm-5 μm.

[0014] As an improvement to the above solution, the angle of the sloped photoresist opening is β, which satisfies: 5°≥β-θ≥-5°.

[0015] The implementation of the present invention has the following beneficial effects: In the present invention, the flip-chip high-voltage light-emitting diode chip includes a substrate and an epitaxial structure stacked on the substrate. The epitaxial structure includes an epitaxial layer, on which an N-type conductive step and an isolation trench are formed. The isolation trench separates the epitaxial structure into a plurality of independent light-emitting units. A reflective layer and an insulating layer are provided on the epitaxial layer. The insulating layer covers the reflective layer and fills the isolation trench. The isolation trench has an angle α between two adjacent light-emitting units. The insulating layer includes a first insulating layer located in the isolation trench, and the angle of the first insulating layer is θ, where α>θ. Based on this design, the isolation trench has a slope, which can improve the antistatic ability of the flip-chip high-voltage LED chip. The insulating layer with a sloped upper surface is provided thereon, forming the first insulating layer with an angle θ, and its slope angle is smaller than the slope angle of the isolation trench. This compensates for the problem of the reduced light-emitting area caused by the slope of the isolation trench, thereby effectively improving the luminous brightness of the flip-chip high-voltage LED chip and reducing the operating voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 : A schematic structural diagram of a flip-chip high-voltage light-emitting diode chip in the present invention; Figure 2 : Figure 1 A partial enlarged view of middle A; Figure 3 : A schematic structural diagram of the structure obtained after step (1) in the present invention is completed; Figure 4 : A schematic structural diagram of the structure obtained after step (2) in the present invention is completed; Figure 5 : A schematic structural diagram of the structure obtained after step (3) in the present invention is completed; Figure 6 : A schematic structural diagram of the structure obtained after step (4) of the present invention is completed; Figure 7 : A schematic diagram of the operation of step (52) in the present invention; Figure 8 : A schematic structural diagram of the photomask used in step (52) of the present invention; Figure 9 : A schematic structural diagram of the structure obtained after step (53) of the present invention is completed; Figure 10 : A schematic structural diagram of the structure obtained after step (54) of the present invention is completed; Figure 11 : A schematic structural diagram of the structure obtained after step (6) of the present invention is completed; Figure 12 : A schematic structural diagram of the structure obtained after step (72) in the present invention is completed.

[0017] Figure numerals: 10-substrate; 11-epitaxial layer; 111-N-type semiconductor layer; 112-active layer; 113-P-type semiconductor layer; 114-N-type conductive step; 12-reflective layer; 13-isolation groove; 14-insulating layer; 141-first insulating layer; 142-first opening; 143-second opening; 15-connecting layer; 16-Bragg reflection layer; 161-third opening; 162-fourth opening; 17-pad layer; 171-P-type pad layer; 172-N-type pad layer; 18-mask; 181-semi-transparent area; 182-first fully transparent area; 183-second fully transparent area. DETAILED DESCRIPTION

[0018] In order to make the objectives, technical solutions and advantages of the present invention more clear, the present invention will be further described in detail with reference to specific embodiments below.

[0019] To solve the above problems, the first aspect of the present invention provides a flip-chip high-voltage light-emitting diode chip, including a substrate 10 and an epitaxial structure stacked on the substrate 10, wherein the epitaxial structure includes an epitaxial layer 11, an N-type conductive step 114, an isolation groove 13, a reflective layer 12, an insulating layer 14, a connecting layer 15, a Bragg reflective layer 16, and a pad layer 17.

[0020] See also Figure 1 The epitaxial structure includes an epitaxial layer 11, on which an N-type conductive step 114 and an isolation groove 13 are formed. The isolation groove 13 separates the epitaxial structure into a plurality of independent light-emitting units. Adjacent light-emitting units are electrically connected via a connecting layer 15. A reflective layer 12 and an insulating layer 14 are provided on the epitaxial layer 11. The insulating layer 14 covers the reflective layer 12 and fills the isolation groove 13. A second conductive layer 114 extending through the N-type conductive step 114 is formed on the insulating layer 14. An opening 142 and a second opening 143 in an adjacent light-emitting unit that penetrates the reflective layer 12, one end of the connecting layer 15 is connected to the N-type conductive step 114 through the first opening 142, and the other end is connected to the reflective layer 12 through the second opening 143; a Bragg reflective layer 16 and a pad layer 17 are provided on the insulating layer 14, and the pad layer 17 passes through the Bragg reflective layer 16 and contacts the reflective layer 12 and the epitaxial layer 11 in the adjacent light-emitting unit respectively.

[0021] Specifically, the epitaxial layer 11 includes an N-type semiconductor layer 111, an active layer 112, and a P-type semiconductor layer 113 stacked in sequence on the substrate 10. The pad layer 17 includes a P-type pad layer 171 and an N-type pad layer 172. The P-type pad layer 171 and the N-type pad layer 172 are located on two adjacent light-emitting units and are electrically connected through the connecting layer 15. A third opening 161 penetrating the reflective layer 12 and a fourth opening 162 in the adjacent light-emitting unit penetrating the N-type semiconductor layer 111 are formed on the Bragg reflector 16. The P-type pad layer 171 contacts the reflective layer 12 through the third opening 161. The N-type pad layer 172 is arranged along the Bragg reflector 16, one end of which is located on the Bragg reflector 16 corresponding to the second opening 143, and the other end contacts the N-type semiconductor layer 111 in the adjacent light-emitting unit through the fourth opening 162. In this application, the heights of the P-type pad layer 171 and the N-type pad layer 172 are made close by setting the N-type pad layer 172, which can balance the lateral electric field gradient, significantly reduce the current crowding effect, reduce the difficulty of preparing the pad layer 17, and evenly distribute the electric field strength between adjacent light-emitting units. Combined with the insulating layer 14, the anti-static ability of the flip-chip high-voltage LED chip can be improved.

[0022] Preferably, see Figure 2 , between two adjacent light-emitting units, the angle of the isolation groove 13 is α, and the insulating layer 14 includes a first insulating layer 141 located in the isolation groove 13, and the angle of the first insulating layer 141 is θ, α>θ, and the isolation groove 13 has a slope, which can improve the antistatic ability of the flip-chip high-voltage LED chip, and the insulating layer 14 with a slope on the upper surface is arranged thereon to form a first insulating layer 141 with an angle θ, and its inclination angle is smaller than the inclination angle of the isolation groove 13, which compensates for the problem of reduced light-emitting area caused by the slope setting of the isolation groove 13, and helps to evenly distribute and dissipate heat, thereby effectively improving the luminous brightness of the flip-chip high-voltage LED chip and reducing the operating voltage. It should be noted that the angle α of the isolation groove 13 in this application refers to the angle between the left part of the isolation groove 13 and the upper horizontal line, and the angle θ of the first insulating layer 141 refers to the angle between the slope of the upper surface of the first insulating layer 141 and the upper horizontal line.

[0023] Furthermore, the angle α of the isolation trench 13 affects the angle θ of the first insulating layer 141. 40°≤α-θ≤60°. In this case, the interface between the isolation trench 13 and the insulating layer 14 is clearer, the electric field distribution is more uniform, and the area of ​​electric field concentration is reduced, which helps prevent current from flowing through unintended paths and reduces the path of current leakage, thereby improving the operating voltage of the LED chip and the anti-static ability of the LED chip, optimizing the current flow path, reducing the area of ​​current congestion, and allowing current to be more evenly injected into the active layer, improving the luminous efficiency and brightness of the LED chip. If α-θ is less than 40°, the improvement in anti-static breakdown capability is not significant. If α-θ is greater than 60°, the improvement in luminous intensity is too small.

[0024] In some specific and preferred embodiments, the angle α is between 65° and 85°. While ensuring the etching yield of the isolation trench 13, this can significantly reduce the electric field concentration at the electrode edge, improving the antistatic capability of the flip-chip high-voltage LED chip. Furthermore, it can minimize the proportion of the light-emitting area blocked by the insulating layer 14, reducing light efficiency loss. If α is less than 65°, the inclination angle of the sidewall of the isolation trench 13 is too low, requiring the insulating layer 14 to cover a longer side surface. In this case, the angle θ is forced to decrease, increasing the contact distance between the insulating layer 14 and the sidewall, forming a localized weak coverage area and increasing the risk of electrostatic breakdown. For example, α is 65°, 70°, 75°, 80°, 85°, etc.

[0025] In some specific and preferred embodiments, the angle θ is 15°-40°, which can adapt to mainstream deposition processes, achieve uniform coverage in the isolation trench 13, and further increase the effective light-emitting area, thereby improving the brightness and anti-static breakdown capability of the LED chip. If the angle θ is greater than 40°, heat concentration will occur in the isolation trench 13, and the anti-static breakdown capability will not meet expectations. If the angle θ is less than 15°, the thickness of the insulating layer 14 will be reduced locally, making this area more susceptible to current breakdown, thereby increasing the risk of electrical short circuits and leakage, and affecting the insulation performance and safety of the LED chip. More preferably, the angle θ is 30°-35°.

[0026] Preferably, the insulating layer 14 is a SiO2 layer, which can effectively isolate the pad layer 17 from the epitaxial layer through its high resistivity and low dielectric constant, reduce the lateral leakage current density, and in high-voltage scenarios, its breakdown field strength can prevent the risk of LED chip short circuit caused by insulation failure. Moreover, it covers the surface of the P-type semiconductor layer 113, which can reduce carrier recombination loss and improve luminous efficiency.

[0027] Preferably, the connecting layer 15 includes an Al layer, a Ti layer, a Ni layer, an Au layer and a Ti layer stacked in sequence, has high conductivity and high reflectivity, has high adhesion on the N-type semiconductor layer 111, and has low contact resistance, and can support high current density operation. The Ni layer can inhibit the metal interdiffusion between Al and Au and maintain interface stability.

[0028] Accordingly, the present invention also provides a method for preparing the flip-chip high-voltage light-emitting diode chip, comprising the following steps: (1) providing a substrate 10 and preparing an epitaxial layer 11 on the substrate 10; (2) preparing a reflective layer 12 on the epitaxial layer 11; (3) Etching is performed on the epitaxial layer 11 not covered by the reflective layer 12 to form an N-type conductive step 114; (4) etching the surface of the N-type conductive step 114 to form an isolation groove 13 with an angle α, thereby separating the epitaxial layer 11 into a plurality of independent light-emitting units; (5) preparing an insulating layer 14 on the reflective layer 12 and the area not covered by the reflective layer 12, performing photolithography and etching on the insulating layer 14 to form a first opening 142 penetrating the N-type conductive step 114 and a second opening 143 penetrating the reflective layer 12 in the adjacent light-emitting unit, and forming a first insulating layer 141 with an angle θ in the isolation trench 13, where α>θ; (6) Preparing a continuous connection layer 15 on the surface of the area between the first opening 142, the first insulating layer 141 and the second opening 143 to electrically connect adjacent light-emitting units; (7) Preparing a Bragg reflection layer 16 on the surface of the insulating layer 14 and the connecting layer 15; (8) A pad layer 17 is prepared on the Bragg reflection layer 16 .

[0029] Each step is described in detail below. Figure 3-Figure 12 .

[0030] Regarding step (1), a substrate 10 is provided, and an epitaxial layer 11 is prepared on the substrate 10; This step specifically includes: A substrate 10 is provided, and an N-type semiconductor layer 111, an active layer 112 and a P-type semiconductor layer 113 are sequentially formed on the substrate 10. Figure 3 .

[0031] Specifically, the N-type semiconductor layer 111 , the active layer 112 and the P-type semiconductor layer 113 may be prepared by a deposition method or other conventionally known methods, exemplified by metal organic chemical vapor deposition (MOCVD), which will not be described in detail herein.

[0032] Optionally, the substrate 10 may be a sapphire substrate, etc., the N-type semiconductor layer 111 may be an N-type GaN layer, an N-type AlGaN layer, or an N-type GaAs layer, but is not limited thereto; the active layer 112 may be an InGaN / GaN layer, an InGaN / AlGaN layer, or an AlGaN / AlGaN layer, but is not limited thereto; the P-type semiconductor layer 113 may be a P-type GaN layer, a P-type AlGaN layer, or a P-type GaAs layer, but is not limited thereto.

[0033] Regarding step (2), a reflective layer 12 is prepared on the epitaxial layer 11; This step specifically includes: A photoresist is coated on the surface of the P-type semiconductor layer 113. After exposure and development, a portion of the photoresist is removed to expose a portion of the P-type semiconductor layer 113. Then, the material of the reflective layer 12 is deposited. Finally, a lift-off process is used to remove the material of the reflective layer 12 on the photoresist, and the photoresist is removed to form the reflective layer 12. Figure 4 .

[0034] Optionally, the reflective layer 12 includes an ITO layer, an Ag layer and a TiW layer stacked in sequence on the P-type semiconductor layer 113, wherein the ITO layer mainly forms an ohmic contact with the P-type semiconductor layer 113, and the deposition thickness of the ITO layer is 50Å-150Å. The Ag layer mainly plays a light reflection role, and the deposition thickness of the Ag layer is 1200Å-2000Å. The TiW layer mainly provides protection for the Ag layer to prevent Ag in the Ag layer from migrating, and the deposition thickness of the TiW layer is 3000Å-5000Å.

[0035] Furthermore, the deposition method of the reflective layer 12 includes but is not limited to magnetron sputtering.

[0036] Regarding step (3), etching is performed on the epitaxial layer 11 not covered by the reflective layer 12 to form an N-type conductive step 114; This step specifically includes: A photoresist is coated on the surface of the reflective layer 12 and the P-type semiconductor layer 113 not covered by the reflective layer 12. After exposure and development, a portion of the P-type semiconductor layer 113 is exposed. The exposed portion is etched to expose the N-type semiconductor layer 111. The photoresist is removed to form an N-type conductive step 114. Figure 5 .

[0037] Optionally, the etching process can be exemplarily dry etching, wet etching, etc. More preferably, the etching process is dry etching, which can better control the size of the N-type conductive step 114. The dry etching can specifically be inductively coupled plasma etching (ICP) etching, reactive ion etching (RIE) etching, etc.

[0038] Regarding step (4), etching is performed on the surface of the N-type conductive step 114 to form an isolation groove 13 with an angle α, thereby separating the epitaxial layer 11 into a plurality of independent light-emitting units; This step specifically includes: Photoresist is coated on the surfaces of the reflective layer 12, the P-type semiconductor layer 113 not covered by the reflective layer 12, and the N-type conductive step 114. After exposure and development, a portion of the N-type conductive step 114 is exposed, and the exposed portion is etched until the substrate 10 is exposed. The photoresist is removed to form an isolation groove 13 with an angle α, thereby separating the epitaxial structure into several independent light-emitting units.

[0039] See also Figure 6 In one embodiment, the isolation trench 13 separates the epitaxial layer 11 into two independent light-emitting units, namely a first light-emitting unit and a second light-emitting unit.

[0040] Optionally, the etching process may be dry etching or wet etching. More preferably, the etching process is dry etching, specifically preferably ICP etching, which can accurately form the desired inclined sidewall morphology and precisely control the angle of the isolation trench 13.

[0041] Regarding step (5), an insulating layer 14 is prepared on the reflective layer 12 and the area not covered by the reflective layer 12, and the insulating layer 14 is subjected to photolithography and etching to form a first opening 142 penetrating the N-type conductive step 114 and a second opening 143 penetrating the reflective layer 12 in the adjacent light-emitting unit, and a first insulating layer 141 with an angle θ is formed in the isolation trench 13, where α>θ; This step specifically includes: Step (51) depositing insulating layer 14 material on the surface of the reflective layer 12, the P-type semiconductor layer 113 not covered by the reflective layer 12, the N-type conductive step 114 and the isolation groove 13 to form an insulating layer 14; Optionally, the insulating layer 14 is deposited by a method including but not limited to PECVD.

[0042] Step (52) is to coat the surface of the insulating layer 14 with photoresist and perform exposure processing using a photomask 18. Figure 7 ; Preferably, a positive photoresist is coated on the surface of the insulating layer 14, and the mask 18 used in the subsequent exposure process is as follows: Figure 8 As shown, the mask 18 includes a fully transparent area, a semi-transparent area 181, and a light-shielding area. The fully transparent area includes a first fully transparent area 182 and a second fully transparent area 183. The first fully transparent area 182 is used to form the first opening 142, and the second fully transparent area 183 is used to form the second opening 143. The semi-transparent area 181 is used to form the first insulating layer 141 with an included angle. The semi-transparent area 181 is composed of light-transmitting units and light-shielding units arranged alternately. By arranging the light-transmitting units and light-shielding units in the semi-transparent area 181 alternately, a sloped opening can be formed on the first insulating layer 141 corresponding to the isolation trench 13, facilitating subsequent etching to form the first insulating layer 141 with an included angle θ.

[0043] Furthermore, the angle formed between the sloped photoresist opening and the upper horizontal plane is β. In the semi-transparent region 181, the width of the light-transmitting unit and the width of the light-shielding unit determine the size of β. The larger the width of the light-transmitting unit or the light-shielding unit, the smaller the angle β formed. Conversely, the smaller the width of the light-transmitting unit or the light-shielding unit, the larger the angle β formed. More preferably, the width of the light-transmitting unit and the width of the light-shielding unit are equal, and the width is 2μm-5μm. When an exposure process is performed under the mask 18 of this structure, the exposed light forms diffraction on the semi-transparent region 181 corresponding to the isolation trench 13 between adjacent light-emitting units. Only after development can a sloped photoresist opening be formed on the insulating layer 14 filled in the isolation trench 13 between adjacent light-emitting units, facilitating the formation of the first insulating layer 141 with an angle of θ.

[0044] Step (53) developing and removing the exposed photoresist, and forming a sloped photoresist opening on the insulating layer 14 filled in the isolation groove 13; Specifically, after the development process, the photoresist in the light-transmitting unit area of ​​the first fully light-transmitting area 182, the second fully light-transmitting area 183, and the semi-light-transmitting area 181 is removed, exposing the insulating layer 14 below, and a sloped photoresist opening is formed on the insulating layer 14 filled in the isolation groove 13. Figure 9 .

[0045] Step (54) etching the insulating layer 14 to remove the remaining photoresist, forming a first opening 142 penetrating the N-type conductive step 114 and a second opening 143 penetrating the reflective layer 12 in the adjacent light-emitting unit, and etching the sloped photoresist opening to obtain a first insulating layer 141 with an angle θ, and removing the photoresist; Specifically, in the first light-emitting unit, the insulating layer 14 exposed in the first fully light-transmitting area 182 is etched until the N-type conductive step 114 is exposed, forming a first opening 142. In the second light-emitting unit, the insulating layer 14 exposed in the second fully light-transmitting area 183 is etched until the reflective layer 12 is exposed, forming a second opening 143. Then, the sloped photoresist opening is etched to remove the portion of the photoresist. A first insulating layer 141 with an angle θ is formed on the isolation groove 13 between the first light-emitting unit and the second light-emitting unit. Finally, the photoresist is removed. Please refer to Figure 10 .

[0046] Furthermore, the angle θ of the insulating layer 14 also depends on the angle β of the sloped photoresist opening. The larger β is, the larger θ is, and the smaller β is, the smaller θ is. The following conditions are met: 5°≥β-θ≥-5°. More preferably, β=θ.

[0047] Optionally, the etching process may be dry etching, preferably ICP etching.

[0048] Regarding step (6), a continuous connection layer 15 is prepared on the surface of the area between the first opening 142, the first insulating layer 141 and the second opening 143 to electrically connect adjacent light-emitting units; This step specifically includes: Photoresist is coated on the surface of the first opening 142, the insulating layer 14 and the second opening 143. After exposure and development, part of the photoresist is removed to expose the area between the first opening 142, the first insulating layer 141 and the second opening 143. Then, the connecting layer 15 material is deposited. Finally, the connecting layer 15 material and the photoresist on the photoresist are removed by a blue film stripping process to form the connecting layer 15. Figure 11 At this time, one end of the connecting layer 15 is connected to the N-type conductive step 114 through the first opening 142 in the first light-emitting unit, and the other end is connected to the reflective layer 12 through the second opening 143 in the second light-emitting unit, completing the electrical connection between the first light-emitting unit and the second light-emitting unit.

[0049] Optionally, the deposition process of the connecting layer 15 includes but is not limited to electron beam evaporation. Al, Ti, Ni, Au, and Ti can be sequentially evaporated in the area exposed after development to form the connecting layer 15. The thickness of the connecting layer 15 can be reasonably adjusted according to actual needs.

[0050] Regarding step (7), a Bragg reflection layer 16 is prepared on the surface of the insulating layer 14 and the connecting layer 15; This step specifically includes: Step (71) depositing a Bragg reflection layer 16 material on the surface of the insulating layer 14 and the connecting layer 15 to form a Bragg reflection layer 16; Optionally, the Bragg reflective layer 16 includes SiO 2 layers and TiO 2 layers that are periodically and alternately stacked, with the number of periods being 20-40. The deposition process of the Bragg reflective layer 16 includes but is not limited to electron beam evaporation.

[0051] Step (72) is to coat photoresist on the Bragg reflector layer 16, and after exposure and development, to etch the exposed portion to form a third opening 161 and a fourth opening 162, see Figure 12 ; Specifically, after the development treatment, part of the photoresist on the Bragg reflective layer 16 is removed to expose part of the Bragg reflective layer 16 located in the first light-emitting unit and the second light-emitting unit. The Bragg reflective layer 16 of the first light-emitting unit is etched until the reflective layer 12 is exposed to form a third opening 161, and the Bragg reflective layer 16 of the adjacent second light-emitting unit is etched until the N-type semiconductor layer 111 is exposed to form a fourth opening 162.

[0052] Optionally, the etching process may be dry etching or wet etching. More preferably, the etching process is dry etching, and more preferably, ICP etching.

[0053] Regarding step (8), a pad layer 17 is prepared on the Bragg reflection layer 16; This step specifically includes: Photoresist is coated on the surfaces of the Bragg reflector layer 16 and the third and fourth openings 161 and 162. After exposure and development, the photoresist in the third and fourth openings 161 and 162 is removed, exposing the Bragg reflector layer 16 from the position corresponding to the second opening 143 to the position corresponding to the fourth opening 162. Then, the material of the pad layer 17 is deposited. Finally, the material of the pad layer 17 and the photoresist on the photoresist are removed by a blue film stripping process, forming a P-type pad layer 171 at the third opening 161 and an N-type pad layer 172 at the fourth opening 162. One end of the N-type pad layer 172 is located on the Bragg reflector layer 16 corresponding to the second opening 143, and the other end contacts the N-type semiconductor layer 111 through the fourth opening 162 in the adjacent second light-emitting unit. Please refer to FIG. Figure 1 At this time, the P-type pad layer 171 of the first light emitting unit and the N-type pad layer 172 of the adjacent second light emitting unit are connected in series.

[0054] Optionally, the deposition process of the pad layer 17 includes but is not limited to electron beam evaporation. The pad layer 17 includes an Al layer / Ti layer / Pt layer / Ti layer / Ni layer / Au layer stacked in sequence.

[0055] The present invention will be further described below with specific embodiments: Example 1 This embodiment provides a flip-chip high-voltage light-emitting diode chip, comprising a substrate and an epitaxial structure stacked on the substrate; The epitaxial structure includes an epitaxial layer, an N-type conductive step and an isolation trench formed on the epitaxial layer, the isolation trench separating the epitaxial structure into a plurality of independent light-emitting units, adjacent light-emitting units being electrically connected via a connection layer, a reflective layer and an insulating layer provided on the epitaxial layer, the insulating layer covering the reflective layer and filling the isolation trench, a first opening penetrating through the N-type conductive step and a second opening penetrating through the reflective layer in an adjacent light-emitting unit formed on the insulating layer, one end of the connection layer being connected to the N-type conductive step via the first opening, and the other end being connected to the reflective layer via the second opening; A Bragg reflector layer and a pad layer are provided on the insulating layer. A third opening penetrating the reflector layer and a fourth opening penetrating the N-type semiconductor layer in an adjacent light-emitting unit are formed on the Bragg reflector layer. The pad layer includes a P-type pad layer and an N-type pad layer. The P-type pad layer and the N-type pad layer are located on two adjacent light-emitting units and are electrically connected through a connecting layer. The P-type pad layer contacts the reflector layer through the third opening. The N-type pad layer is arranged along the Bragg reflector layer, one end of which is located on the Bragg reflector layer corresponding to the second opening, and the other end contacts the N-type semiconductor layer through the fourth opening.

[0056] Between two adjacent light-emitting units, the included angle of the isolation groove is α, α=85°, and the insulating layer includes a first insulating layer located in the isolation groove, and the included angle of the first insulating layer is θ, θ=40°.

[0057] The insulating layer is a SiO2 layer; the connecting layer includes an Al layer, a Ti layer, a Ni layer, an Au layer and a Ti layer stacked in sequence.

[0058] Accordingly, this embodiment also provides a method for preparing a flip-chip high-voltage light-emitting diode chip, comprising the following steps: S1. Providing a substrate, and sequentially preparing epitaxial layers on the substrate using an MOCVD process, wherein the epitaxial layers include an N-type semiconductor layer, an active layer, and a P-type semiconductor layer arranged in sequence; S2, coating the P-type semiconductor layer with a photoresist, exposing and developing the P-type semiconductor layer to expose a portion of the P-type semiconductor layer, then sequentially sputtering an ITO layer, an Ag layer, and a TiW layer using a magnetron sputtering process, and finally removing the reflective layer material on the photoresist using a lift-off process, and removing the photoresist to form a reflective layer; S3, coating a photoresist on the surface of the reflective layer and the P-type semiconductor layer not covered by the reflective layer, exposing and developing the surface to expose a portion of the P-type semiconductor layer, and etching the exposed portion using an ICP etching process to expose the N-type semiconductor layer, removing the photoresist, and forming an N-type conductive step; S4, coating photoresist on the surface of the reflective layer, the P-type semiconductor layer not covered by the reflective layer, and the N-type conductive step; after exposure and development, exposing a portion of the N-type conductive step; and etching the exposed portion using an ICP etching process until the substrate is exposed, removing the photoresist, forming an isolation trench with an angle α, and separating the epitaxial layer into a plurality of independent light-emitting units; S5, depositing an insulating layer material on the surface of the reflective layer, the P-type semiconductor layer not covered by the reflective layer, the N-type conductive step, and the isolation trench using a PECVD process to form an insulating layer; Then, photoresist is coated on the surface of the insulating layer. Figure 8 The photomask is subjected to exposure processing, wherein the width of the light-transmitting unit in the photomask is equal to the width of the light-shielding unit, and the width is 2 μm; Next, the exposed photoresist is removed by development, and a sloped photoresist opening is formed on the insulating layer filled in the isolation trench, wherein the angle formed between the sloped photoresist opening and the upper horizontal plane is β, β=θ; Finally, the insulating layer is etched using an ICP etching process to remove the remaining photoresist, forming a first opening penetrating to the N-type conductive step, and the insulating layer of the adjacent light-emitting unit is etched to form a second opening penetrating to the reflective layer, and the sloped photoresist opening is etched to obtain a first insulating layer with an angle of θ, and the photoresist is removed; S6. Coating a photoresist on the surface between the first opening, the insulating layer, and the second opening; removing a portion of the photoresist after exposure and development to expose the area between the first opening, the first insulating layer, and the second opening; then sequentially depositing Al, Ti, Ni, Au, and Ti using an electron beam evaporation device; and finally removing the connecting layer material and the photoresist on the photoresist using a blue film stripping process to form a connecting layer. S7. Alternately evaporating SiO2 layers and TiO2 layers on the surfaces of the insulating layer and the connecting layer using an electron beam evaporation device to form a Bragg reflector layer; subsequently, coating the Bragg reflector layer with photoresist, exposing and developing the Bragg reflector layer to expose portions of the Bragg reflector layer on the left and right sides of the isolation trench; and etching the Bragg reflector layer of one of the light-emitting units using an ICP etching process until the reflector layer is exposed to form a third opening, and etching the Bragg reflector layer of the adjacent light-emitting unit until the N-type semiconductor layer is exposed to form a fourth opening; S8. Coating photoresist on the surface of the Bragg reflection layer and the third and fourth openings; removing the photoresist in the third and fourth openings after exposure and development, and exposing the Bragg reflection layer from the corresponding position of the second opening to the fourth opening; then sequentially vapor-depositing an Al layer, a Ti layer, a Pt layer, a Ti layer, a Ni layer, and an Au layer using electron beam evaporation equipment; finally, removing the pad layer material and the photoresist on the photoresist using a blue film stripping process; forming a P-type pad layer at the third opening and an N-type pad layer at the fourth opening, wherein one end of the N-type pad layer is located on the Bragg reflection layer corresponding to the second opening, and the other end is in contact with the N-type semiconductor layer through the fourth opening.

[0059] Example 2 This embodiment provides a flip-chip high-voltage light-emitting diode chip, which is basically the same as the first embodiment, except that: The included angle of the isolation trench is α, α=70°, and the included angle of the first insulating layer is θ, θ=30°.

[0060] The width of the light-transmitting unit in the mask is equal to the width of the light-shielding unit, which is 3.2 μm. The angle of the sloped photoresist opening is β, where β=α.

[0061] Example 3 This embodiment provides a flip-chip high-voltage light-emitting diode chip, which is basically the same as the first embodiment, except that: The included angle of the isolation trench is α, α=65°, and the included angle of the first insulating layer is θ, θ=15°.

[0062] The width of the light-transmitting unit in the mask is equal to the width of the light-shielding unit, and the width is 5 μm. The angle formed by the sloped photoresist opening and the upper horizontal plane is β, and β=θ.

[0063] Example 4 This embodiment provides a flip-chip high-voltage light-emitting diode chip, which is basically the same as the first embodiment, except that: The included angle of the isolation trench is α, α=75°, and the included angle of the first insulating layer is θ, θ=15°.

[0064] The width of the light-transmitting unit in the mask is equal to the width of the light-shielding unit, and the width is 4 μm. The angle formed by the sloped photoresist opening and the upper horizontal plane is β, and β=θ.

[0065] Comparative Example 1 This comparative example provides a flip-chip high-voltage light-emitting diode chip, which is basically the same as Example 2, except that: The included angle of the isolation groove is α, α=70°.

[0066] Accordingly, during the preparation of the flip-chip high-voltage light-emitting diode chip, a conventional photomask is used for exposure. Specifically: S5, depositing an insulating layer material on the surface of the reflective layer, the P-type semiconductor layer not covered by the reflective layer, the N-type conductive step, and the isolation trench using a PECVD process to form an insulating layer; Subsequently, photoresist is coated on the surface of the insulating layer, and an exposure process is performed using a conventional photomask; Next, the photoresist after exposure is removed by development; Finally, the insulating layer is etched using an ICP etching process to remove the remaining photoresist to form a first opening penetrating the N-type conductive step, and the insulating layer of the adjacent light-emitting unit is etched to form a second opening penetrating the reflective layer.

[0067] Performance Testing 1. Luminous Performance: After the flip-chip high-voltage light-emitting diode chips obtained in the examples and comparative examples were prepared, their brightness and operating voltage were tested. The flip-chip high-voltage light-emitting diode chip had a size of 230 μm*400 μm and included two light-emitting units. The test results are shown in Table 1 below.

[0068] 2. Antistatic Capability: After the flip-chip high-voltage LED chips obtained in the Examples and Comparative Examples were prepared, their brightness and voltage at a current of 5 mA, as well as their antistatic capability in human body mode, were tested. The flip-chip high-voltage LED chip had a size of 230 μm*400 μm and included two light-emitting units. The test results are shown in Table 1 below.

[0069] Table 1 Performance test results of examples and comparative examples

[0070] It can be seen from the above results that the angle of the isolation groove between two adjacent light-emitting units in this application is α, and the insulating layer includes a first insulating layer located in the isolation groove, and the angle of the first insulating layer is θ. Controlling α>θ can improve the anti-static ability of the flip-chip high-voltage LED chip, compensate for the problem of reduced light-emitting area caused by the slope setting of the isolation groove, and contribute to uniform distribution of heat and effective heat dissipation, thereby effectively improving the luminous brightness of the flip-chip high-voltage LED chip and reducing the operating voltage.

[0071] The above disclosure is only a preferred embodiment of the present invention and certainly cannot be used to limit the scope of the present invention. Therefore, equivalent changes made according to the claims of the present invention are still within the scope of the present invention.

Claims

1. A flip-chip high-voltage light-emitting diode chip, characterized in that: comprising a substrate and an epitaxial structure stacked on the substrate; The epitaxial structure includes an epitaxial layer, an N-type conductive step and an isolation trench formed on the epitaxial layer, the isolation trench separating the epitaxial structure into a plurality of independent light-emitting units, adjacent light-emitting units being electrically connected via a connection layer, a reflective layer and an insulating layer provided on the epitaxial layer, the insulating layer covering the reflective layer and filling the isolation trench, a first opening penetrating through the N-type conductive step and a second opening penetrating through the reflective layer in an adjacent light-emitting unit formed on the insulating layer, one end of the connection layer being connected to the N-type conductive step via the first opening, and the other end being connected to the reflective layer via the second opening; A Bragg reflective layer and a pad layer are provided on the insulating layer, and the pad layer passes through the Bragg reflective layer and contacts the reflective layer and the epitaxial layer in the adjacent light emitting unit respectively; The included angle of the isolation trench between two adjacent light-emitting units is α, the insulating layer includes a first insulating layer located in the isolation trench, the included angle of the first insulating layer is θ, and α>θ.

2. The flip-chip high-voltage light-emitting diode chip according to claim 1, wherein: The epitaxial layer includes an N-type semiconductor layer, an active layer and a P-type semiconductor layer stacked in sequence on the substrate; The pad layer includes a P-type pad layer and an N-type pad layer, wherein the P-type pad layer and the N-type pad layer are located on two adjacent light-emitting units and are electrically connected via a connecting layer; A third opening penetrating the reflective layer and a fourth opening penetrating the N-type semiconductor layer in an adjacent light-emitting unit are formed on the Bragg reflective layer. The P-type pad layer contacts the reflective layer through the third opening. The N-type pad layer is arranged along the Bragg reflective layer, with one end thereof being located on the Bragg reflective layer corresponding to the second opening, and the other end being in contact with the N-type semiconductor layer in the adjacent light-emitting unit through the fourth opening.

3. The flip-chip high-voltage light-emitting diode chip according to claim 1, wherein: Satisfies: 40°≤α-θ≤60°.

4. The flip-chip high-voltage light-emitting diode chip according to claim 3, characterized in that: The α is 65°-85°.

5. The flip-chip high-voltage light-emitting diode chip according to claim 3 or 4, characterized in that: The θ is 15°-40°.

6. The flip-chip high-voltage light-emitting diode chip according to claim 1, wherein: The insulating layer is a SiO2 layer; The connection layer includes an Al layer, a Ti layer, a Ni layer, an Au layer and a Ti layer stacked in sequence.

7. A method for preparing a flip-chip high-voltage light-emitting diode chip according to any one of claims 1 to 6, characterized in that: include: providing a substrate, and preparing an epitaxial layer on the substrate; preparing a reflective layer on the epitaxial layer; Etching the epitaxial layer not covered by the reflective layer to form an N-type conductive step; Etching the surface of the N-type conductive step to form an isolation groove with an angle of α, thereby separating the epitaxial layer into a plurality of independent light-emitting units; An insulating layer is prepared on the reflective layer and the area uncovered by the reflective layer, and the insulating layer is subjected to photolithography and etching to form a first opening penetrating the N-type conductive step and a second opening penetrating the reflective layer in an adjacent light-emitting unit, and a first insulating layer with an angle θ is formed in the isolation trench, where α>θ; A continuous connection layer is formed on the surface of the region between the first opening, the first insulating layer, and the second opening to electrically connect adjacent light-emitting units; preparing a Bragg reflection layer on the surfaces of the insulating layer and the connecting layer; A pad layer is prepared on the Bragg reflection layer.

8. The method for preparing a flip-chip high-voltage light-emitting diode chip according to claim 7, wherein: The insulating layer is subjected to photolithography and etching to form a first opening penetrating to the N-type conductive step and a second opening penetrating to the reflective layer in an adjacent light-emitting unit, and a first insulating layer with an included angle θ is formed in the isolation trench, including: Coating photoresist on the surface of the insulating layer and performing exposure processing using a photomask; The photoresist after exposure is removed by development, and a sloped photoresist opening is formed on the insulating layer filled in the isolation groove; Etching the insulating layer to remove the remaining photoresist, thereby forming a first opening extending through the N-type conductive step and a second opening extending through the reflective layer; Etching the sloped photoresist opening to obtain a first insulating layer with an angle of θ; In which, the light mask includes a fully transparent area, a semi-transparent area and a shading area, the fully transparent area includes a first fully transparent area and a second fully transparent area, the first fully transparent area is used to form the first opening, the second fully transparent area is used to form the second opening, the semi-transparent area is used to form the first insulating layer with an angle, and the semi-transparent area is composed of transparent units and shading units arranged alternately.

9. The method for preparing a flip-chip high-voltage light-emitting diode chip according to claim 8, wherein: The width of the light-transmitting unit is equal to the width of the light-shielding unit, and the width is 2 μm-5 μm.

10. The method for preparing a flip-chip high-voltage light-emitting diode chip according to claim 9, wherein: The included angle of the sloped photoresist opening is β, which satisfies the following: 5°≥β-θ≥-5°.

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