Power control of a computing device

Abstract

A method for power control includes receiving first power consumption data for a first computing device based on measurements of the first computing device, and receiving second power consumption data for a second computing device based on measurements of the second computing device. The method also includes receiving system power data to obtain a system power limit. The method further includes calculating a power budget threshold for the first computing device and the second computing device based on the first power consumption data, the second power consumption data, and the system power limit. The method includes controlling performance of the first computing device to operate within a power budget threshold, and controlling performance of the second computing device to operate within the power budget threshold.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. patent application No. 18 / 507,955, filed on November 13, 2023, entitled “POWER CONTROL OF COMPUTING DEVICES,” and claims the benefit of U.S. provisional patent application No. 63 / 447,572, filed on February 22, 2023, entitled “POWER CONTROL OF COMPUTING DEVICES,” the disclosures of which are expressly incorporated herein by reference in their entireties. background Technical Field

[0003] Aspects of the present disclosure relate to computing devices, and more particularly to power control of computing devices based on system-level power measurements. Background Art

[0004] Mobile or portable computing devices include mobile phones, laptops, palmtops and tablet computers, portable digital assistants (PDAs), portable game consoles, and other portable electronic devices. Mobile computing devices are composed of many electronic components that consume power and generate heat. Components (or computing devices) can include system-on-chip (SoC) devices, graphics processing units (GPUs), neural processing units (NPUs), digital signal processors (DSPs), and modems, among others.

[0005] Power management technologies conserve power and manage thermal constraints in mobile devices. During operation, computing devices within mobile devices generate heat or thermal energy, which, at excessive levels, can be harmful to the mobile device's internal circuitry. The amount of thermal energy generated can vary depending on operating conditions. For example, when operating at high workload levels, a processor may generate significant amounts of thermal energy.

[0006] Techniques are known to dynamically adjust power supply voltage to attempt to maximize battery life, control heat generation, or provide other power management benefits. It would be desirable to have a system for managing power consumption of a computing device of a mobile device to limit the maximum average power of the computing device based on various scenarios. Summary of the Invention

[0007] In various aspects of the present disclosure, a method for power control includes receiving first power consumption data of a first computing device based on measurements of the first computing device. The method also includes receiving second power consumption data of a second computing device based on measurements of the second computing device. The method also includes receiving system power data to obtain a system power limit. The method also includes calculating power budget thresholds for the first computing device and the second computing device based on the first power consumption data, the second power consumption data, and the system power limit. The method includes controlling the performance of the first computing device to operate within the power budget threshold, and controlling the performance of the second computing device to operate within the power budget threshold.

[0008] Other aspects of the present disclosure relate to an apparatus. The apparatus has at least one memory and one or more processors coupled to the at least one memory. The processor is configured to receive first power consumption data of a first computing device based on measurements of the first computing device and second power consumption data of a second computing device based on measurements of the second computing device. The processor is further configured to receive system power data to obtain a system power limit. The processor is further configured to calculate power budget thresholds for the first computing device and the second computing device based on the first power consumption data, the second power consumption data, and the system power limit. The processor is configured to control the performance of the first computing device to operate within the power budget threshold and to control the performance of the second computing device to operate within the power budget threshold.

[0009] Other aspects of the present disclosure relate to an apparatus. The apparatus includes components for receiving first power consumption data of a first computing device based on measurements of the first computing device, and components for receiving second power consumption data of a second computing device based on measurements of the second computing device. The apparatus also includes components for receiving system power data to obtain a system power limit. The apparatus includes components for calculating power budget thresholds for the first computing device and the second computing device based on the first power consumption data, the second power consumption data, and the system power limit. The apparatus also includes components for controlling the performance of the first computing device to operate within the power budget threshold. The apparatus includes components for controlling the performance of the second computing device to operate within the power budget threshold.

[0010] In other aspects of the present disclosure, a non-transitory computer-readable medium includes program code for receiving first power consumption data of a first computing device based on measurements of the first computing device and program code for receiving second power consumption data of a second computing device based on measurements of the second computing device. The program code also includes program code for receiving system power data to obtain a system power limit. The program code also includes program code for calculating power budget thresholds for the first computing device and the second computing device based on the first power consumption data, the second power consumption data, and the system power limit. The program code also includes program code for controlling the performance of the first computing device to operate within the power budget threshold. The program code also includes program code for controlling the performance of the second computing device to operate within the power budget threshold.

[0011] This has broadly outlined the features and technical advantages of the present disclosure so that the detailed description that follows may be better understood. Additional features and advantages of the present disclosure will be described below. It will be understood by those skilled in the art that the present disclosure may be readily used as a basis for modifying or designing other structures for carrying out the same purposes as the present disclosure. It will also be recognized by those skilled in the art that such equivalent constructions do not depart from the teachings of the present disclosure as set forth in the appended claims. The novel features that are believed to be characteristic of the present disclosure, both in terms of its organization and method of operation, together with further objects and advantages, will be better understood when the following description is considered in conjunction with the accompanying drawings. However, it is to be expressly understood that each of the figures is provided for illustration and description purposes only and is not intended to be a definition of limitations of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] For a more complete understanding of the present disclosure, reference is now made to the following description taken in conjunction with the accompanying drawings.

[0013] Figure 1 is a block diagram illustrating an example implementation of a host system-on-chip (SoC) including a power limiting driver according to certain aspects of the present disclosure.

[0014] Figure 2 is a block diagram illustrating a power limiting architecture according to aspects of the present disclosure.

[0015] Figure 3 is a flow chart illustrating an example process performed, for example, by a power limiting driver, according to various aspects of the present disclosure.

[0016] Figure 4 is a flow diagram illustrating an example process, eg, performed by a mobile device, according to various aspects of the present disclosure.

[0017] Figure 5 is a block diagram illustrating an exemplary wireless communication system in which configurations of the present disclosure may be advantageously employed.

[0018] Figure 6 is a block diagram illustrating a design workstation used for circuit, layout, and logic design of components according to various aspects of the present disclosure. DETAILED DESCRIPTION

[0019] The detailed description set forth below in conjunction with the accompanying drawings is intended as a description of various configurations and is not intended to represent the only configurations in which the described concepts may be practiced. The detailed description includes specific details to provide a comprehensive understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form to avoid obscuring such concepts.

[0020] As described, the use of the term "and / or" is intended to mean "inclusive or", and the use of the term "or" is intended to mean "exclusive or". As described, the term "exemplary" as used throughout the description means "serving as an example, instance, or illustration" and is not necessarily to be construed as preferred or advantageous over other exemplary configurations. As described, the term "coupled" as used throughout the description means "directly or indirectly connected through an intervening connection (e.g., a switch), electrically, mechanically, or otherwise, and is not necessarily limited to physical connections. Additionally, a connection may be such that the objects are permanently connected or releasably connected. The connection may be made through a switch. As described, the term "proximate" as used throughout the description means "adjacent, very close, immediately adjacent, or proximate". As described, the term "on..." as used throughout the description means "directly on..." in some configurations and "indirectly on..." in other configurations.

[0021] It's desirable to limit system or system-on-chip (SoC) power based on various use cases. For example, an SoC may have peak and / or sustained power draws that exceed the specifications for how much power the battery system can deliver. For certain use cases, such as managing battery discharge, power may be limited. Other use cases include limiting power to accommodate charger output capacity for damaged batteries, balancing power between the SoC and a discrete graphics processing unit (dGPU), limiting power to manage heat pipe capacity, limiting power to extend battery life, and limiting power to manage fan acoustics.

[0022] Aspects of the present disclosure control and manage the maximum average power consumption of a computing device by implementing a feedback loop that uses system-level power measurements to periodically select the highest performance state while keeping the system within fixed power constraints / thresholds. Actual power consumption depends on the workload of the computing device. In some aspects of the present disclosure, power limits are based on digital power meters. In these aspects, a digital power meter in a subsystem (e.g., a computing device) measures each power domain. The digital power meter also measures power rail levels. The power rail levels provide rail power levels for total SoC power measurement. The digital power meter can estimate the dynamic and leakage power consumed by subsystems such as the central processing unit (CPU) (also known as the SoC) and the GPU. A power peak regulator can be implemented in a closed loop with the digital power meter. The peak power regulator limits peak power draw to a programmable value. A hardware tracker collects data from sensors and / or estimators (e.g., from the CPU) and applies mitigation via actuators to perform power or thermal management.

[0023] Certain aspects of the subject matter described in this disclosure can be implemented to achieve one or more of the following potential advantages. In some examples, the described techniques (such as calculating power budget thresholds and controlling device performance) enable limiting system and SoC power to manage various use cases, such as those related to battery power and thermal limitations. Other advantages include improved visibility into subsystem-level power and energy.

[0024] Figure 1 An example implementation of a host system-on-chip (SoC) 100 including a power limiting driver according to aspects of the present disclosure is illustrated. The host SoC 100 includes processing blocks tailored for specific functions, such as a connectivity block 110. The connectivity block 110 may include fifth generation (5G) connectivity, fourth generation long term evolution (4G LTE) connectivity, Wi-Fi connectivity, universal serial bus (USB) connectivity, Bluetooth connectivity, and the like. ® connection, Secure Digital (SD) connection, etc.

[0025] In this configuration, the host SoC 100 includes various processing units that support multi-threaded operations. Figure 1In the configuration shown, host SoC 100 includes a multi-core central processing unit (CPU) 102, a graphics processor unit (GPU) 104, a digital signal processor (DSP) 106, and a neural processor unit (NPU) 108. Host SoC 100 may also include a sensor processor 114, an image signal processor (ISP) 116, a navigation module 120, which may include a global positioning system (GPS), and memory 118. Multi-core CPU 102, GPU 104, DSP 106, NPU 108, and multimedia engine 112 support various functions such as video, audio, graphics, gaming, artificial intelligence, and more. Each processor core of multi-core CPU 102 may be a reduced instruction set computing (RISC) machine, an advanced RISC machine (ARM), a microprocessor, or some other type of processor. NPU 108 may be based on the ARM instruction set.

[0026] As mentioned above, it's desirable to limit system or system-on-chip (SoC) power based on various use cases. For example, an SoC may have peak and / or sustained power draws that exceed specifications for how much power the battery system can deliver. For certain use cases, such as managing battery discharge, this power may be limited. Other use cases include limiting power to accommodate charger output capacity for damaged batteries, balancing power between an SoC and a discrete graphics processing unit (dGPU), limiting power to manage heat pipe capacity, limiting power to extend battery life, and limiting power to manage fan acoustics.

[0027] Various aspects of the present disclosure control and manage the maximum average power consumption of a computing device by implementing a feedback loop that uses system-level power measurements to periodically select the highest performance state while maintaining the system within fixed power constraints / thresholds. In some aspects, multiple control loops operate for different average power durations. For example, a power limit driver (PLD) can monitor the system's continuous average power (CAP) limit and burst average power (BAP) limit. The BAP limit is associated with a burst duration, i.e., the length of time that power is averaged and controlled. Furthermore, CAP and BAP limits may exist for individual packages / SoCs.

[0028] Actual power consumption depends on the workload of the computing device. Actual power consumption may temporarily exceed the threshold until performance adjustments are completed. For example, consider a system with minimum and maximum potential power consumption values ​​of 500 W and 700 W, respectively. A power budget threshold can be specified to reduce power consumption to 525 W. When this power budget is configured, the performance of the system is dynamically adjusted to maintain a power consumption of 525 W or less. In some aspects of the present disclosure, power limiting is based on digital power meters. In these aspects, digital power meters in all major subsystems (e.g., computing devices) measure each power domain. The digital power meters also measure power rail levels. The power rail levels provide rail power levels to achieve total SoC power measurement.

[0029] The digital power meter estimates the dynamic and leakage power consumed by subsystems such as the CPU (also more generally referred to as the SoC) and GPU. A power peak regulator can be set up in a closed loop with the digital power meter. The peak power regulator limits the peak power draw to a programmable value. The hardware tracker collects data from sensors and / or estimators and applies mitigation via actuators. In some implementations, a maximum average power (MAP) limit hardware tracker collects data from the CPU. The MAP tracker can be configured to monitor power over a moving average window. The average value can be an exponentially weighted moving average or a simple average. The duration is configurable. The actuator can be implemented as a finite state machine that implements the hardware control loop in the entire system.

[0030] On the CPU, the CPU subsystem power and clock management controller (e.g., the power management controller (PMC) firmware) can implement power or thermal management for the CPU cluster, specifically the performance control software loop that manages the cluster's power-performance states (P-states). This firmware periodically reads the event monitoring (EMON) registers and makes the CPU power data available to the power limit driver (PLD). In some aspects, the power limit driver can be implemented on the audio digital signal processor (ADSP) via shared memory. The EMON registers may go beyond performance monitoring unit (PMU) events, as they include non-core information such as CPU and GPU caches and memories (e.g., last-level cache (LLC)), bus interface unit (BIU) information, and more. The EMON registers also track power, dynamic, leakage, and total power at a per-core or per-cluster granularity. Similar approaches can be applied to subsystems beyond the CPU subsystem.

[0031] Advantages of the proposed solution include the ability to meet accuracy specifications because the proposed solution improves visibility into power and energy at the subsystem level. Other advantages include low area penalty power efficiency, more predictable characterization, more robust digital verification, and less complex silicon implementation. By using hardware trackers, firmware can perform power or thermal management on a per-cluster or subsystem basis, particularly performance control software loops that manage the P-states of the cluster. Dynamic power can be calculated as a weighted sum of microarchitectural events across a finite set of samples. The weights can be workload-dependent. The digital power meter can be extended to high-, mid-, and value-tier chipsets.

[0032] Figure 2 is a block diagram illustrating a power limiting architecture 200 according to aspects of the present disclosure. In the power limiting architecture 200, a power limiting driver (PLD) 202 manages system and SoC power limits by setting power caps on central processing units (CPUs) (also known as system-on-chip (SoCs), chips, or packages) and graphics processing units (GPUs). Other computing devices may also be controlled (e.g., Figure 1 The NPU 108, DSP 106, or ISP 116 of the SoC, or any discrete processing unit), but for ease of explanation, only these two computing devices are described. A power limit can be defined for the entire SoC.

[0033] The allocated power limit can be controlled by adjusting the power consumption of one or more components. In some aspects, the SoC performance and power consumption are adjusted. For example, the PLD 202 can balance power between the SoC and the discrete GPU (dGPU) 204 by setting a power cap on the central processing unit (CPU) of the SoC and the dGPU 204. When the dGPU 204 is not utilized, the PLD 202 can manipulate power between the CPU and GPU within the SoC by setting a power cap on the CPU and GPU. Figure 2 In the example of , the GPU may be dGPU 204 or a GPU (not shown) within GPU subsystem (GPUSS) 260 .

[0034] The PLD 202 may reside within a battery protection domain (BattPD) 206, although such a location is non-limiting. The battery protection domain 206 may include battery charging software and USB software for monitoring USB devices. Figure 2 In the example of FIG. 4 , the battery protection domain 206 resides within an audio digital signal processor (ADSP) 208 .

[0035] The system's power limits may originate from an external controller (EC) 210, a service layer 212, a power management controller (PMC) 216 (e.g., a power engine plug-in (PEP)), a unified extensible firmware interface (UEFI) 218, and / or PLD 202. In some aspects, the power limit may indicate how much power can be allocated to the SoC and / or GPU. EC 210 may monitor and manage platform power, for example, based on whether cooling fans are running. EC 210 may communicate with PLD 202 via an inter-integrated circuit (I2C) link. Service layer 212 may be a high-level operating system (HLOS) kernel, such as the Microsoft Windows operating system kernel. Kernel 212 may include a kernel-mode driver (KMD) 214, an operating system software driver that configures and transmits commands to GPUSS 260. KMD 214 may communicate with PLD 202 via a GLINK interface. KMD 214 offloads processing to dGPU 204, which has its own driver (not shown). PMC 216 may be a power limit driver that acts as a gateway for core 212 to communicate with the SoC. PMC 216 runs on CPU subsystem (CPUSS) 250 and assists in setting the operating state (e.g., clock and voltage) of CPUSS 250. UEFI 218 and PMC 216 communicate with PLD 202 via a GLINK interface. UEFI 218 may initialize PLD 202. Graphics card drivers, such as discrete GPU driver (GPU DRV) 220, may communicate with external graphics cards (e.g., dGPU 204) via a peripheral component interconnect express (PCIe) interface. When dGPU 204 is operating, discrete GPU driver 220 receives power limits from dGPU 204 and transmits this information to PLD 202 to balance power between CPUSS 250 and dGPU 204.

[0036] Battery Charge Limiter (BCL) 222 of charger 224 communicates with PLD 202. BCL 222 monitors the battery and manages it during voltage drops and excessive current draw. While monitoring the battery, BCL 222 can provide an indication of power limits, which can trigger further constraints on system power consumption (e.g., SoC and GPU). PLD 202 can measure system power by reading current and voltage data from the charger. In some aspects (not shown), the power monitor is an external third-party power monitor.

[0037] Shared memory 226 can communicate with GPU subsystem (GPUSS) 260 and CPU subsystem (CPUSS) 250. Shared memory 226 can store graphics management unit power data (GMU Pwr) 232 and central processing unit power unit data (CPU Pwr) 234. Graphics management unit power data (GMU Pwr) 232 includes GPU power limit 236. Central processing unit power unit data (CPU Pwr) 234 includes CPU power limit 238.

[0038] GPU subsystem (GPUSS) 260 includes a GPU (not shown), a digital current estimator (DCE) 240, and a graphics management unit (GMU) 242. Graphics management unit (GMU) 242 may operate as a power and clock manager for the graphics core and may control the GPU based on graphics management unit power data (GMU Pwr) 232 and GPU power limit 236. Digital current estimator (DCE) 240 may operate as a power monitor, measuring the power consumed by the GPU.

[0039] The CPU subsystem (CPUSS) 250 includes a CPU (not shown), a digital power monitor (DPM) 244, and a CPU for each cluster ( Figure 2 The power management debug processor (PMC) 246 can be configured to manage the three clusters shown in the example. The power management debug processor (PMC) 246 can operate as a power and clock manager for the SoC core and can control the SoC based on the CPU power data (CPUPwr) 234 and the CPU power limit 238. Each digital power monitor (DPM) 244 can operate as a power monitor, measuring the power consumed by the SoC cluster.

[0040] Based on the power limit, system power, CPU power, and GPU power, PLD 202 calculates a budget for the CPU and GPU. The CPU and GPU limit the amount of power consumed within the budget by reducing performance. This performance reduction can be achieved using firmware or hardware mechanisms (e.g., a maximum average power limiter). In some aspects, power is balanced between the SoC and the GPU.

[0041] A battery may have several requirements related to average discharge current or discharge power. For example, the peak discharge current managed by BCL 222 in charger 224 may be approximately 10 ms. Discharge current or discharge power may be managed by PLD 202 every second. Discharge power may be managed continuously by PLD 202. BCL 222 also manages very short-duration battery voltage drops, approximately every 10 µs.

[0042] In some implementations, the BCL 222 measures the current and / or power at the battery every 100 ms. The BCL 222 may also send the measurements to the core 212 at the same period. Based on the measurements, the BCL 222 may indicate that the current power limit should be updated to further constrain power consumption.

[0043] The process for calculating the power limit budget is now described. In some aspects of the present disclosure, power can be managed based on CPU power consumption. The budgeting process can track multiple power limits and determine the worst-case limiter. Power limits are set to manage multiple potential limiters. For example, continuous battery discharge can be monitored. In some implementations, a 54 W continuous discharge rating can be a limiter. Battery burst discharge can also be a limiter. In some implementations, the battery burst discharge limit is 7.5 A for 10 seconds. Other potential limiters can include heat pipe capacity and platform thermal design power (TDP). TDP can correspond to SoC limits based on system settings, such as fan acoustics, whether the device is docked, etc.

[0044] According to aspects of the present disclosure, a power limit is set to one of four limits. The first limit is based on the total allowable system power for continuous operation. The second limit is based on the total allowable system power for a specified duration. The third limit is based on the total allowable SoC system power for continuous operation. The fourth limit is based on the total allowable SoC system power for a specified duration.

[0045] As mentioned above, in some aspects, both GPU and CPU power can be controlled. However, in other aspects, only SoC power is controlled. In those aspects where only the CPU is controlled, a minimum CPU power limit is specified to enable the available devices. If the CPU minimum is reached, the GPU is throttled.

[0046] Figure 3 This is a flow chart illustrating an example process 300, for example, performed by a power limit driver (PLD), according to various aspects of the present disclosure. In this example, process 300 consists of two threads. The first thread will now be described. The first thread (thread #1) is the main PLD loop. After initializing the periodic budget thread at block s302, at block s304, process 300 waits for a signal to start the process, or alternatively, a timer to start the process. In some implementations, initialization may be triggered by the Unified Extensible Firmware Interface (UEFI). At block s306, a determination is made as to whether a timer has expired or a communication (comms) has arrived indicating an updated power limit. The timer triggers the periodic update of the power limit. When the timer expires, the first thread runs. The communication may be an asynchronous wakeup signal arriving from the second thread (thread #2) in response to another process communicating a new limit.

[0047] If a communication indicating an updated power limit has arrived, the power limit is updated in shared memory 226 at block s308, and process 300 continues at block s314. If the timer expires, process 300 reads the power data for the CPU and GPU at block s310 and determines, based on the system power data, which configured power limit has the most stringent constraints at block s312. At block 314, a proportional-integral-derivative (PID) control process is executed. At block s316, process 300 selects the minimum power limit. More specifically, the PLD monitors more than one limit, such as the system's continuous average power (CAP) and burst average power (BAP) limits. Furthermore, a package / SoC may have both CAP and BAP limits. The BAP limit is also associated with a burst duration, e.g., the length of time over which power is averaged and controlled. In the example of block s314, four instances of the control loop monitor average power consumption relative to the limits. At block s316, the limit with the least headroom is selected to apply the power budget to the CPU and GPU. Note that the average calculation can be an exponentially weighted moving average or a simple moving average. In some implementations, the burst window can be five seconds, and a streak can be defined as a sufficiently long duration that the moving average represents a value close to the consecutive specified limit of the limit in question.

[0048] Based on the constraints and power limits in shared memory 226, the budgeting process generates new GPU and CPU power limits at block s318. At block s320, the new power limits are communicated to the CPU and GPU. After communicating the new power limits at block s320, process 300 goes to sleep and waits for a communication signal or timer to initiate process 300 at block s304.

[0049] The second thread (thread #2) handles communications. All interrupts and callbacks are sent to the second thread. The second thread wakes up the first thread as needed. At block s340, communications are initialized. At block s342, communications interruptions are handled. For example, a laptop computer may be plugged into an electrical outlet and operating under the constant limit of what can be delivered from the battery plus the charger. If the charger is unplugged, the PLD changes the limit to the battery's capacity alone. Another entity notifies the PLD that the charger is unplugged by sending a communication to the second thread, which is then received at block s342.

[0050] According to aspects of the present disclosure, a mobile device includes a power limit driver. The power limit driver may include a component for calculating a power budget threshold for a first computing device and a second computing device based on first power consumption data, second power consumption data, and a system power limit. In one configuration, the computing component may be a PLD 202, such as Figure 2In other aspects, the aforementioned components may be any structure or any material configured to perform the functions recited by the aforementioned components.

[0051] As indicated above, Figures 2 to 3 are provided as examples. Other examples can be compared with Figures 2 to 3 The examples described are different.

[0052] Figure 4 is a flow chart illustrating an example process 400, performed, for example, by a mobile device, in accordance with various aspects of the present disclosure. The example process 400 is an example of power control of a computing device based on system-level power measurements.

[0053] like Figure 4 As shown, in some aspects, process 400 may include receiving first power consumption data of a first computing device based on measurements of the first computing device (block 402). For example, the first computing device may be a system on a chip (SoC).

[0054] In some aspects, process 400 may include receiving second power consumption data of a second computing device based on measurements of the second computing device (block 404).For example, the second computing device may be a GPU.

[0055] In some aspects, process 400 may include receiving system power data to obtain a system power limit (block 406). For example, the system power data may include battery data and / or thermal data.

[0056] In some aspects, process 400 may include calculating power budget thresholds for the first computing device and the second computing device based on the first power consumption data, the second power consumption data, and a system power limit (block 408). For example, the system power limit may include: a total allowable system power for continuous system operation, a total allowable power for a duration of system operation, a total allowable system power for continuous SoC operation, and a total allowable power for a duration of SoC operation.

[0057] In some aspects, process 400 may include controlling the performance of the first computing device to operate within a power budget threshold (block 410).For example, the clock speed of the first computing device may be reduced.

[0058] In some aspects, process 400 may include controlling the performance of the second computing device to operate within a power budget threshold (block 412).For example, the clock speed of the second computing device may be reduced.

[0059] Figure 5 is a block diagram illustrating an exemplary wireless communication system 500 in which one aspect of the present disclosure may be advantageously employed. For purposes of illustration, Figure 5Three remote units 520, 530, and 550 and two base stations 540 are shown. It will be appreciated that a wireless communication system may have more remote units and base stations. Remote units 520, 530, and 550 include integrated circuit (IC) devices 525A, 525B, and 525C that include the disclosed power limiting drivers (PLDs). It will be appreciated that other devices may also include the disclosed PLDs, such as base stations, switchgear, and network equipment. Figure 5 Forward link signals 580 from base station 540 to remote units 520, 530, and 550, and reverse link signals 590 from remote units 520, 530, and 550 to base station 540 are shown.

[0060] exist Figure 5 , remote unit 520 is shown as a mobile phone, remote unit 530 is shown as a portable computer, and remote unit 550 is shown as a fixed location remote unit in a wireless local loop system. For example, the remote unit may be a mobile phone, a handheld personal communication system (PCS) unit, a portable data unit (such as a personal data assistant), a GPS-enabled device, a navigation device, a set-top box, a music player, a video player, an entertainment unit, a fixed location data unit (such as a meter reading device), or other devices that store or retrieve data or computer instructions, or a combination thereof. Although Figure 5 Remote units according to aspects of the present disclosure are illustrated, but the present disclosure is not limited to these exemplary illustrated units.Aspects of the present disclosure may be suitable for use in many devices including the disclosed PLD.

[0061] Figure 6 FIG2 is a block diagram illustrating a design workstation 600 for circuit, layout, and logic design of semiconductor components, such as the PLDs disclosed above. Design workstation 600 includes a hard disk 601 containing operating system software, supporting files, and design software (such as Cadence or OrCAD). Design workstation 600 also includes a display 602 to facilitate the design of a circuit 610 or semiconductor component 612 (such as a PLD). A storage medium 604 is provided for tangibly storing the design of circuit 610 or semiconductor component 612 (e.g., a PLD). The design of circuit 610 or semiconductor component 612 can be stored on storage medium 604 in a file format such as GDSII or GERBER. Storage medium 604 can be a CD-ROM, DVD, hard disk, flash memory, or other suitable device. Furthermore, design workstation 600 includes a drive 603 for receiving input from or writing output to storage medium 604.

[0062] The data recorded on storage medium 604 may specify a logic circuit configuration, pattern data for a photolithography mask, or mask pattern data for a serial write tool (such as electron beam lithography). The data may also include logic verification data, such as timing diagrams or network circuits associated with logic simulations. Providing data on storage medium 604 facilitates the design of circuit 610 or semiconductor component 612 by reducing the number of processes used to design a semiconductor wafer.

[0063] Example aspects

[0064] Aspect 1: A power control method, the method comprising: receiving first power consumption data of the first computing device based on measurements of the first computing device; receiving second power consumption data of the second computing device based on measurements of the second computing device; receiving system power data to obtain a system power limit; calculating a power budget threshold of the first computing device and the second computing device based on the first power consumption data, the second power consumption data and the system power limit; controlling the performance of the first computing device to operate within the power budget threshold; and controlling the performance of the second computing device to operate within the power budget threshold.

[0065] Aspect 2: The method according to aspect 1, wherein the system power data comprises at least one of the following: battery data and thermal data.

[0066] Aspect 3: The method of aspect 1 or 2, wherein the first computing device comprises a system on a chip (SoC) and the second computing device comprises a graphics processing unit (GPU).

[0067] Aspect 4: A method according to any of the preceding aspects, wherein the system power limit includes: the total allowable system power for continuous system operation, the total allowable power for the duration of system operation, the total allowable system power for continuous SoC operation, and the total allowable power for the duration of SoC operation.

[0068] Aspect 5: A method according to any one of the preceding aspects, wherein the measurement of the first computing device includes a digital power meter estimate of the dynamic power and leakage power of the first computing device, the measurement of the second computing device includes a digital power meter estimate of the dynamic power and leakage power of the second computing device, controlling the performance of the first computing device includes limiting the maximum average power of the first computing device, and controlling the performance of the second computing device includes limiting the maximum average power of the second computing device.

[0069] Aspect 6: An apparatus for power control, the apparatus comprising: at least one memory; and at least one processor, the at least one processor being coupled to the at least one memory, the at least one processor being configured to: receive first power consumption data of the first computing device based on measurements of the first computing device; receive second power consumption data of the second computing device based on measurements of the second computing device; receive system power data to obtain a system power limit; calculate a power budget threshold for the first computing device and the second computing device based on the first power consumption data, the second power consumption data, and the system power limit; control the performance of the first computing device to operate within the power budget threshold; and control the performance of the second computing device to operate within the power budget threshold.

[0070] Aspect 7: The apparatus of aspect 6, wherein the system power data comprises at least one of: battery data and thermal data.

[0071] Aspect 8: The apparatus of aspect 6 or 7, wherein the first computing device comprises a system on a chip (SoC) and the second computing device comprises a graphics processing unit (GPU).

[0072] Aspect 9: An apparatus according to any one of Aspects 6 to 8, wherein the system power limit includes: the total allowable system power for continuous system operation, the total allowable power for the duration of system operation, the total allowable system power for continuous SoC operation, and the total allowable power for the duration of SoC operation.

[0073] Aspect 10: An apparatus according to any one of Aspects 6 to 9, wherein the measurement of the first computing device includes a digital power meter estimate of the dynamic power and leakage power of the first computing device, the measurement of the second computing device includes a digital power meter estimate of the dynamic power and leakage power of the second computing device, controlling the performance of the first computing device includes limiting the maximum average power of the first computing device, and controlling the performance of the second computing device includes limiting the maximum average power of the second computing device.

[0074] Aspect 11: An apparatus for power control, the apparatus comprising: a component for receiving first power consumption data of the first computing device based on measurements of the first computing device; a component for receiving second power consumption data of the second computing device based on measurements of the second computing device; a component for receiving system power data to obtain a system power limit; a component for calculating a power budget threshold of the first computing device and the second computing device based on the first power consumption data, the second power consumption data and the system power limit; a component for controlling the performance of the first computing device to operate within the power budget threshold; and a component for controlling the performance of the second computing device to operate within the power budget threshold.

[0075] Aspect 12: The apparatus of aspect 11, wherein the system power data comprises at least one of: battery data and thermal data.

[0076] Aspect 13: The apparatus of aspect 11 or 12, wherein the first computing device comprises a system on a chip (SoC) and the second computing device comprises a graphics processing unit (GPU).

[0077] Aspect 14: An apparatus according to any one of Aspects 11 to 13, wherein the system power limit includes: a total allowable system power for continuous system operation, a total allowable power for a duration of system operation, a total allowable system power for continuous SoC operation, and a total allowable power for a duration of SoC operation.

[0078] Aspect 15: An apparatus according to any one of Aspects 11 to 14, wherein the measurement of the first computing device includes a digital power meter estimate of the dynamic power and leakage power of the first computing device, the measurement of the second computing device includes a digital power meter estimate of the dynamic power and leakage power of the second computing device, controlling the performance of the first computing device includes limiting the maximum average power of the first computing device, and controlling the performance of the second computing device includes limiting the maximum average power of the second computing device.

[0079] Aspect 16: A non-transitory computer-readable medium having program code recorded thereon, the program code being executed by a processor and comprising: program code for receiving first power consumption data of a first computing device based on measurements of a first computing device; program code for receiving second power consumption data of a second computing device based on measurements of a second computing device; program code for receiving system power data to obtain a system power limit; program code for calculating a power budget threshold for the first computing device and the second computing device based on the first power consumption data, the second power consumption data, and the system power limit; program code for controlling the performance of the first computing device to operate within the power budget threshold; and program code for controlling the performance of the second computing device to operate within the power budget threshold.

[0080] Aspect 17: The non-transitory computer-readable medium of aspect 16, wherein the system power data comprises at least one of: battery data and thermal data.

[0081] Aspect 18: The non-transitory computer-readable medium of aspect 16 or 17, wherein the first computing device comprises a system on a chip (SoC) and the second computing device comprises a graphics processing unit (GPU).

[0082] Aspect 19: A non-transitory computer-readable medium according to any one of Aspects 16 to 18, wherein the system power limit includes: the total allowable system power for continuous system operation, the total allowable power for the duration of system operation, the total allowable system power for continuous SoC operation, and the total allowable power for the duration of SoC operation.

[0083] Aspect 20: A non-transitory computer-readable medium according to any one of Aspects 16 to 19, wherein the measurements of the first computing device include digital power meter estimates of the dynamic power and leakage power of the first computing device, the measurements of the second computing device include digital power meter estimates of the dynamic power and leakage power of the second computing device, controlling the performance of the first computing device includes limiting the maximum average power to the first computing device, and controlling the performance of the second computing device includes limiting the maximum average power to the second computing device.

[0084] For firmware and / or software implementations, the methodologies may be implemented with modules (e.g., procedures, functions, etc.) that perform the described functionality. Machine-readable media tangibly embodying instructions may be used to implement the described methodologies. For example, software code may be stored in memory and executed by a processor unit. The memory may be implemented within the processor unit or external to the processor unit. As used, the term "memory" refers to various types of long-term, short-term, volatile, non-volatile, or other memory, and is not limited to a particular type of memory or amount of memory or the type of medium on which the memory is stored.

[0085] If implemented in firmware and / or software, the functions may be stored as one or more instructions or code on a computer-readable medium. Examples include computer-readable media encoded with a data structure and computer-readable media encoded with a computer program. Computer-readable media include physical computer storage media. Storage media can be available media that can be accessed by a computer. By way of example and not limitation, such computer-readable media may include random access memory (RAM), read-only memory (ROM), electrically erasable read-only memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disc storage, magnetic disk storage or other magnetic storage devices, or other media that can be used to store the desired program code in the form of instructions or data structures and that can be accessed by a computer. Disk and optical disc, as used, include: compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk, and Blu-ray ® Optical disks, where magnetic disks typically reproduce data magnetically, while optical disks reproduce data using lasers. Combinations of the above should also be included within the scope of computer-readable media.

[0086] In addition to being stored on a computer-readable medium, instructions and / or data may also be provided as signals on a transmission medium included in a communication device. For example, the communication device may include a transceiver that carries signals indicating instructions and data. These instructions and data are configured to cause one or more processors to implement the functionality outlined in the claims.

[0087] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and modifications can be made without departing from the technology of the present disclosure as defined in the appended claims. For example, relative terms such as "above" and "below" are used with respect to a substrate or electronic device. Of course, if the substrate or electronic device is inverted, above becomes below, and vice versa. In addition, if it is sideways oriented, above and below may refer to the sides of the substrate or electronic device. In addition, the scope of the present disclosure is not intended to be limited to the specific configurations of the processes, machines, manufactures, material compositions, components, methods and steps described in the specification. As a person of ordinary skill in the art will readily understand from the present disclosure, processes, machines, manufactures, material compositions, components, methods or steps that currently exist or will be developed in accordance with the present disclosure that perform substantially the same functions as the corresponding configurations described or achieve substantially the same results as the corresponding configurations described herein can be utilized. Therefore, the appended claims are intended to include such processes, machines, manufactures, material compositions, components, methods or steps within their scope.

[0088] It will be further understood by those skilled in the art that the various illustrative logic blocks, modules, circuits, and algorithmic steps described in conjunction with the present disclosure may be implemented as electronic hardware, computer software, or a combination of the two. In order to clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been generally described above in terms of their functionality. Whether such functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in different ways for each specific application, but such specific implementation decisions should not be interpreted as resulting in a departure from the scope of the present disclosure.

[0089] The various illustrative logical blocks, modules, and circuits described in connection with this disclosure may be implemented or performed using a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described. While a general-purpose processor may be a microprocessor, in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

[0090] The steps or algorithms of the methods described in conjunction with the present disclosure may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. The software module may be located in RAM, flash memory, ROM, erasable programmable read-only memory (EPROM), EEPROM, registers, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor so that the processor can read information from and write information to the storage medium. In an alternative embodiment, the storage medium may be integral to the processor. The processor and storage medium may reside in an ASIC. The ASIC may reside in a user terminal. In an alternative embodiment, the processor and storage medium may reside in the user terminal as discrete components.

[0091] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be apparent to those skilled in the art, and the general principles defined may be applied to other variations without departing from the spirit or scope of the disclosure. Therefore, the disclosure is not intended to be limited to the examples and designs described, but is to be accorded the widest scope consistent with the principles and novel features disclosed.

Claims

1. A power control method, the method comprising: receiving first power consumption data of a first computing device based on a measurement of the first computing device; receiving second power consumption data of the second computing device based on a measurement of the second computing device; receiving system power data to obtain a system power limit; calculating a power budget threshold for the first computing device and the second computing device based on the first power consumption data, the second power consumption data, and the system power limit; controlling performance of the first computing device to operate within the power budget threshold; as well as Performance of the second computing device is controlled to operate within the power budget threshold. 2 . The method of claim 1 , wherein the system power data comprises at least one of: battery data and thermal data. 3 . The method of claim 1 , wherein the first computing device comprises a system on a chip (SoC) and the second computing device comprises a graphics processing unit (GPU).

4. The method of claim 3, wherein the system power limitation comprises: Total allowable system power for continuous system operation, total allowable power for a duration of system operation, total allowable system power for continuous SoC operation, and total allowable power for a duration of SoC operation.

5. The method of claim 1 , wherein the measurements of the first computing device include digital power meter estimates of dynamic power and leakage power of the first computing device, the measurements of the second computing device include digital power meter estimates of dynamic power and leakage power of the second computing device, controlling the performance of the first computing device includes limiting to a maximum average power of the first computing device, and controlling the performance of the second computing device includes limiting to a maximum average power of the second computing device.

6. A device for power control, the device comprising: at least one memory; and at least one processor coupled to the at least one memory, the at least one processor configured to: receiving first power consumption data of a first computing device based on a measurement of the first computing device; receiving second power consumption data of the second computing device based on a measurement of the second computing device; receiving system power data to obtain a system power limit; calculating a power budget threshold for the first computing device and the second computing device based on the first power consumption data, the second power consumption data, and the system power limit; controlling performance of the first computing device to operate within the power budget threshold; as well as Performance of the second computing device is controlled to operate within the power budget threshold. The apparatus of claim 6 , wherein the system power data comprises at least one of: battery data and thermal data. 8 . The apparatus of claim 6 , wherein the first computing device comprises a system on a chip (SoC) and the second computing device comprises a graphics processing unit (GPU).

9. The apparatus of claim 8, wherein the system power limitation comprises: Total allowable system power for continuous system operation, total allowable power for a duration of system operation, total allowable system power for continuous SoC operation, and total allowable power for a duration of SoC operation.

10. The apparatus of claim 6 , wherein the measurements of the first computing device include digital power meter estimates of dynamic power and leakage power of the first computing device, the measurements of the second computing device include digital power meter estimates of dynamic power and leakage power of the second computing device, controlling the performance of the first computing device includes limiting to a maximum average power of the first computing device, and controlling the performance of the second computing device includes limiting to a maximum average power of the second computing device.

11. A device for power control, the device comprising: means for receiving first power consumption data of a first computing device based on measurements of the first computing device; means for receiving second power consumption data of a second computing device based on measurements of the second computing device; means for receiving system power data to obtain a system power limit; means for calculating a power budget threshold for the first computing device and the second computing device based on the first power consumption data, the second power consumption data, and the system power limit; means for controlling performance of the first computing device to operate within the power budget threshold; and Means for controlling performance of the second computing device to operate within the power budget threshold. 12 . The apparatus of claim 11 , wherein the system power data comprises at least one of: battery data and thermal data.

13. The apparatus of claim 11, wherein the first computing device comprises a system on a chip (SoC) and the second computing device comprises a graphics processing unit (GPU).

14. The apparatus of claim 13, wherein the system power limitation comprises: Total allowable system power for continuous system operation, total allowable power for a duration of system operation, total allowable system power for continuous SoC operation, and total allowable power for a duration of SoC operation.

15. The apparatus of claim 11 , wherein the measurements of the first computing device comprise digital power meter estimates of dynamic power and leakage power of the first computing device, the measurements of the second computing device comprise digital power meter estimates of dynamic power and leakage power of the second computing device, controlling the performance of the first computing device comprises limiting to a maximum average power of the first computing device, and controlling the performance of the second computing device comprises limiting to a maximum average power of the second computing device.

16. A non-transitory computer-readable medium having program code recorded thereon, the program code being executed by a processor and comprising: program code for receiving first power consumption data of a first computing device based on measurements of the first computing device; program code for receiving second power consumption data of a second computing device based on measurements of the second computing device; program code for receiving system power data to obtain a system power limit; program code for calculating power budget thresholds for the first computing device and the second computing device based on the first power consumption data, the second power consumption data, and the system power limit; program code for controlling performance of the first computing device to operate within the power budget threshold; and Program code for controlling performance of the second computing device to operate within the power budget threshold. 17 . The non-transitory computer readable medium of claim 16 , wherein the system power data comprises at least one of: battery data and thermal data.

18. The non-transitory computer-readable medium of claim 16, wherein the first computing device comprises a system on a chip (SoC) and the second computing device comprises a graphics processing unit (GPU).

19. The non-transitory computer readable medium of claim 18, wherein the system power limit comprises: Total allowable system power for continuous system operation, total allowable power for a duration of system operation, total allowable system power for continuous SoC operation, and total allowable power for a duration of SoC operation.

20. The non-transitory computer-readable medium of claim 16, wherein the measurements of the first computing device include digital power meter estimates of dynamic power and leakage power of the first computing device, the measurements of the second computing device include digital power meter estimates of dynamic power and leakage power of the second computing device, controlling the performance of the first computing device includes limiting to a maximum average power of the first computing device, and controlling the performance of the second computing device includes limiting to a maximum average power of the second computing device.

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