Mitigating saddle deformation of substrates using film deposition and edge ion implantation

Abstract

The disclosed systems and techniques relate to correcting out-of-plane deformation (OPD) of a substrate. The technique includes obtaining a profile of the out-of-plane deformation of the substrate using optical inspection data; and identifying one or more parameters characterizing a saddle stress of the substrate using the obtained profile. The technique further includes calculating one or more characteristics of a stress compensation layer (SCL) for the substrate using the identified one or more parameters; and causing the SCL to be deposited on the substrate. The technique further includes causing a stress mitigation beam to be applied to a plurality of edge regions of the SCL, wherein a setting of the stress mitigation beam is determined using the identified one or more parameters.

Description

Technical Field

[0001] This disclosure relates to semiconductor fabrication, including the fabrication of wafers. Background Art

[0002] Modern semiconductor devices (such as processing circuits, memory devices, photodetectors, solar cells, light-emitting semiconductor devices, etc.) are typically manufactured on silicon wafers (or other suitable substrates). The wafer may undergo many processing operations, such as physical vapor deposition, chemical vapor deposition, etching, photomasking, polishing and / or various other operations. In order to continuously reduce the cost of semiconductor devices, multilayer stacks of chips, insulating films, patterned and / or doped semiconductor films and / or other features are typically deposited on a single wafer, thereby producing high aspect ratio devices such as those used in three-dimensional flash memory devices and other applications. The deposition, patterning, etching, polishing, etc. of the multilayer structure stack typically results in significant stress being applied to the underlying wafer. This stress can cause both out-of-plane and in-plane distortion of the features supported by the wafer. These distortions can cause misalignment of the deposited features and can significantly reduce the quality of the manufactured device. Summary of the Invention

[0003] In one embodiment, disclosed is a method for correcting out-of-plane deformation of a substrate, the method comprising: obtaining a profile of the out-of-plane deformation of the substrate using optical inspection data. The method further comprises: using the obtained profile to identify one or more parameters characterizing saddle stress of the substrate. The method further comprises: calculating one or more properties of a stress-compensating layer (SCL) for the substrate using the identified one or more parameters. The method further comprises: depositing the SCL on the substrate; and applying a stress mitigation beam to a plurality of edge regions of the SCL, wherein settings of the stress mitigation beam are determined using the identified one or more parameters.

[0004] In another embodiment, disclosed is a system comprising a memory and a processing device communicatively coupled to the memory, the processing device configured to: obtain a profile of out-of-plane deformation of a substrate using optical inspection data. The processing device is further configured to: use the obtained profile to identify one or more parameters characterizing saddle stress of the substrate. The processing device is further configured to: calculate one or more properties of a stress-compensating layer (SCL) for the substrate using the identified one or more parameters. The processing device is further configured to: apply a stress mitigation beam to a plurality of edge regions of the SCL, wherein settings of the stress mitigation beam are determined using the identified one or more parameters.

[0005] In another embodiment, disclosed is a semiconductor manufacturing system comprising one or more processing chambers for processing a substrate and a computing device. The computing device is configured to: obtain a profile of the out-of-plane deformation of the substrate using optical inspection data; and identify one or more parameters characterizing saddle stress of the substrate using the obtained profile. The computing device is further configured to: calculate one or more properties of a stress compensating layer (SCL) for the substrate using the identified one or more parameters; deposit the SCL on the substrate; and apply a stress mitigation beam to multiple edge regions of the SCL, wherein settings of the stress mitigation beam are determined using the identified one or more parameters.

[0006] In yet another embodiment, disclosed is a non-transitory computer-readable memory having instructions stored thereon that, when executed by a processing device, cause the processing device to perform operations comprising: identifying one or more parameters characterizing saddle stress of the substrate using the obtained profile. The operations further comprise: calculating one or more properties of a stress-compensating layer (SCL) for the substrate using the identified one or more parameters. The operations further comprise: applying a stress mitigation beam to a plurality of edge regions of the SCL, wherein settings for the stress mitigation beam are determined using the identified one or more parameters, and wherein settings for the ion implantation are determined using the identified one or more parameters. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present disclosure can be understood more fully from the detailed description given below and the accompanying drawings of various embodiments of the present disclosure.

[0008] Figures 1A to 1E A process for stress correction of a backside deposited film using additional ion implantation is schematically illustrated according to at least one embodiment.

[0009] Figure 2 An example Zernike polynomial decomposition of an actual deformation of a wafer (upper left) in arbitrary units is shown to decompose it into a parabolic bow deformation (upper right), a saddle deformation (lower left), and a residual deformation (lower right), in accordance with at least one embodiment.

[0010] Figure 3 An example wafer is shown using a Figures 1A to 1E Stress and deformation relief of the disclosed process.

[0011] Figure 4 An example profile of a Gaussian ion beam that may be used for stress and deformation mitigation in a wafer is shown in accordance with at least one embodiment.

[0012] Figure 5 An example silicon wafer having a silicon nitride film deposited thereon and having a saddle-shaped deformation is shown in accordance with at least one embodiment.

[0013] Figure 6 is a flow chart illustrating an example process for mitigating saddle shape deformation of a wafer in accordance with at least one embodiment.

[0014] Figure 7A Saddle stress is shown for an example wafer according to at least one embodiment.

[0015] Figure 7B Schematically illustrating the selection of a target stress compensation film based on the amplitude of the saddle portion of wafer stress according to at least one embodiment.

[0016] Figure 7C FIG. 5 illustrates stress present in a wafer after a stress compensating film is deposited on the wafer in accordance with at least one embodiment.

[0017] Figure 7D Wafer stress relief due to edge ion implantation into the stress compensating film is shown.

[0018] Figures 8A to 8D Example ion implantations that may be used for ion implantation performed to mitigate saddle wafer deformation are shown in accordance with at least one embodiment. Figure 8A A curved implantation is shown in accordance with at least one embodiment, wherein a uniform ion implantation dose is applied within a certain equal-width edge region of a stress-compensating film. Figure 8B A meniscus edge implant is shown in accordance with at least one embodiment, wherein a uniform ion implant dose is applied within an edge region of varying (azimuthal) thickness. Figure 8C A gradient edge implantation in accordance with at least one embodiment is shown, wherein a non-uniform ion implantation dose is applied within the edge region. Figure 8D Custom shape ion implantation in accordance with at least one embodiment is shown.

[0019] Figures 9A to 9C Some examples of implant assist features that may be used to mitigate residual stress in accordance with at least one embodiment are shown.

[0020] FIG. 10A to FIG. 10B Schematically illustrates an example wafer pair according to at least one embodiment. Figure 9A and Figure 9C The dose graph shows the response.

[0021] Figure 11A An ion implantation system capable of performing ion implantation into a stress compensating layer according to at least one embodiment is schematically illustrated.

[0022] Figure 11B According to at least one embodiment, Figure 11A The ion implantation system delivers ions to the wafer at any incident angle.

[0023] Figure 12 Depicted is a block diagram of an example computer system capable of supporting operations of the present disclosure in accordance with at least one embodiment. DETAILED DESCRIPTION

[0024] The prior art includes a variety of approaches to addressing wafer deformation. For example, a deformed (warped) wafer, with various films and features deposited on one side (herein referred to as the front, top, or primary side), can be coated on the other side (herein referred to as the backside or bottom) with a film that applies compressive or tensile stress to the wafer. Such backside-deposited deformation-correcting films (herein also referred to as stress-compensating layers) typically apply a uniform (or global) stress across the entire wafer and are unable to compensate for localized stress modulation and / or anisotropic stress. Additional correction can be achieved by implanting ions into the stress-compensating layer (e.g., bombarding the stress-compensating layer with an ion beam) to adjust the stress in the stress-compensating layer, thereby further mitigating deformation in the underlying wafer.

[0025] As used herein, "wafer" refers to any substrate or material surface formed on a substrate on which film processing is performed during the manufacturing process. For example, depending on the application, wafer surfaces on which processing may be performed include materials such as silicon, silicon oxide, silicon nitride, strained silicon, silicon on insulator, carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other material (e.g., metals, metal nitrides, metal alloys, and other conductive materials). Wafers include, but are not limited to, semiconductor wafers. In some cases, wafers may include plastic substrates. Wafers may be exposed to pretreatment processes to polish, etch, reduce, oxidize, hydroxylate, anneal, UV cure, electron beam cure, and / or bake the substrate surface. In addition to performing film processing directly on the surface of the wafer itself, any of the disclosed film processing steps may also be performed on an underlying layer formed on the wafer, as disclosed in more detail below, and the term "wafer surface" is intended to include such underlying layers as indicated by the context. Thus, for example, if a film / layer or portion of a film / layer has already been deposited onto the wafer surface, the exposed surface of the newly deposited film / layer becomes the wafer surface. In some embodiments, the thickness of the wafer is in the range of 0.25 mm to 1.5 mm, or in the range of 0.5 mm to 1.25 mm, or in the range of 0.75 mm to 1.0 mm, or thicker. In some embodiments, the diameter of the wafer is about 10 cm, 20 cm, 30 cm or more.

[0026] Stress compensation layers deposited by ion implantation are used to correct uniform and isotropic stress (σxx ≈σ yy ) can be quite efficient. On the other hand, the stress (σ) that varies with position x,y on the wafer can be mitigated. jk (x,y)), anisotropic stress (σ xx ≠σ yy ) or both is a more challenging problem. Some feature patterns may cause compressive stress along one direction (e.g. σ xx <0), while tensile stress (σ yy >0), resulting in saddle-shaped wafers, such as Figure 5 Such saddle-shaped features may appear, for example, in material stacks with directional patterning (e.g., word line patterning in flash memory devices). Correcting such anisotropic saddle-shaped deformations in wafers remains a difficult task.

[0027] Aspects and embodiments of the present disclosure address these and other challenges of modern semiconductor manufacturing technology by providing systems and techniques that can mitigate non-uniform and / or anisotropic stress and deformation in wafers. In some embodiments, a method for mitigating saddle deformation may include: identifying the principal axis (direction) and magnitude of the saddle deformation, e.g., σ jk ∝cos(2φ+α); and identifying properties of a stress-compensating film (layer) that can cause stress in the wafer to have a defined sign (e.g., whether the stress is positive or negative across the entire region of the wafer). This transforms the deformation of the wafer from a saddle-like deformation to a cylindrical deformation. The method can further include depositing a film with the identified properties and then relieving high-stress regions of the wafer by implanting ions into the edges of these high-stress regions of the film. Residual higher-order (waviness) deformations can then be addressed by further implanting ions into regions of the film.

[0028] In one embodiment, the vertical profile z=h(r,φ) of the wafer deformation can be measured using optical metrology techniques. For example, optical interferometry can be used to obtain an interference pattern of the profile h(r,φ). The wafer profile h(r,φ) can then be represented by a plurality of parameters that qualitatively and quantitatively characterize the geometry of the wafer deformation. In some embodiments, the wafer profile can be represented using a set of Zernike (or a similar set of) polynomials,

[0029]

[0030] where r is the radial coordinate and φ is the polar coordinate in the (average) plane of the wafer. The successive coefficients A1, A2, A3, A4, ... represent the weights of specific geometrical features (element deformations) of the wafer as described by the corresponding Zernike polynomials Z1(r,φ), Z2(r,φ), Z3(r,φ), Z4(r,φ), ... (The Noll indexing scheme for the Zernike polynomials is used in this paper.) The first three coefficients are less important, since they describe a uniform displacement of the wafer (coefficient A1, associated with the polynomial Z1(r,φ) = 1), a deformation-free x-tilt equivalent to a rotation about the y-axis (coefficient A2, associated with the polynomial Z2(r,φ) = 2rcosφ), and a deformation-free x-tilt equivalent to a rotation about the x-axis (coefficient A3, associated with the polynomial Z3(r,φ) = 2rsinφ), which can be eliminated by realigning the coordinate axes. The fourth coefficient A4 is associated with The fifth coefficient A5 and the sixth coefficient A6 are related to and The polynomials are associated and characterize saddle-type deformations. The A5 coefficient characterizes saddle shapes that bend upward (A5>0) or downward (A5<0) along the diagonal y=x and downward (A5>0) or upward (A5<0) along the diagonal y=-x. The A6 coefficient characterizes saddle shapes that bend upward (A6>0) or downward (A6<0) along the x-axis and downward (A6>0) or upward (A6<0) along the y-axis. Higher coefficients A7, A8, etc. characterize that the wafer deformation h(r,φ) changes increasingly rapidly along the radial direction, along the azimuthal direction, or both, and together represent the residual deformation. Figure 2 An example Zernike polynomial decomposition 200 of an actual deformation h(r,φ) of a wafer (upper left) in arbitrary units is shown to decompose the deformation into a parabolic bow deformation A4Z4(r,φ) (upper right), a saddle deformation A5Z5(r,φ)+A6A6(r,φ) (lower left), and a residual deformation h res (r,φ)(lower right).

[0031] In some embodiments, the thickness d of the stress-compensating film may be selected based on the value of the parabola bow coefficient A4. Figures 1A to 1E A process for stress correction of a backside deposited film using additional ion implantation is schematically illustrated according to at least one embodiment. Figure 1A The wafer 102 is depicted with deformations, which may include parabolic bow deformation (with negative coefficient A4 < 0) and other deformations, such as saddle deformation and residual deformation (both are shown in Figure 1 for simplicity and ease of review). Figures 1A to 1E(not shown in the figures). Wafer 102 has a front side 104 and a back side 106. Any number of features (e.g., deposited and / or etched patterns), chips, photomasks, and / or any other structures may be deposited on or etched in front side 104. In some embodiments, back side 106 may be free of deposited / etched features / structures. In some embodiments, back side 106 may also have one or more deposited / etched features / structures. Figure 1B The schematic diagram shows the deposition of a stress-compensating layer on the backside of wafer 102. In some embodiments, stress-compensating layer 108 can include one or more films of different materials. The thickness of individual films can be in the range of 10 to 200 nanometers, or in the range of 20 to 180 nanometers, or in the range of 30 to 160 nanometers, or in the range of 40 to 140 nanometers, or greater. The total thickness of the stress-compensating layer can be up to several micrometers or even thicker. In some embodiments, stress-compensating layer 108 is deposited at a temperature in the range of 100° C. to 500° C., or higher.

[0032] The material (type) of the stress compensating layer 108 may be selected based on the sign of the coefficient A4. For example, for negative bow, A4 < 0, and the stress compensating layer 108 may be selected to have a tensile stress (e.g., Figures 1A to 1E For a silicon wafer, this film may be a silicon nitride (Si3N4) film. Conversely, for a positive bow, A4>0, and the stress compensation layer 108 may be selected to have a tensile stress ( Figures 1A to 1E (not shown). The stress-compensating layer 108 can be deposited using any suitable deposition technique, including physical vapor deposition (e.g., sputtering), chemical vapor deposition (e.g., plasma-assisted deposition), epitaxy, lift-off, etc. The deposition can be performed at room temperature or at a temperature different from room temperature (e.g., high temperature). In some embodiments, the thickness d of the stress-compensating layer 108 can be selected to overcorrect the deformation to a certain extent, for example, Figure 1C As shown, the negative parabolic bow becomes a positive parabolic bow. Thickness-dependent parabolic bow correction A corr (d) Change the wafer deformation from h(r,φ) to h corr (r,φ).

[0033] h corr (r,φ)=h(r,φ)+A corr (d)·Z4(r,φ)

[0034] The overcorrection is selected in conjunction with the implant species, energy, and dose to ensure maximum benefit from stress compensation. The overcorrection allows the combined structure of the wafer 102 and the stress compensating layer 108 to be susceptible to further control of stress (and thus to wafer deformation). corr Further control of (r,φ). Figure 1D As shown, an ion beam implanter 110 can generate an ion beam 112 that impacts the stress-compensating layer 108 and deposits ions therein. The ion beam 112 can carry silicon ions, phosphorus ions, argon ions, neon ions, xenon ions, krypton ions, and the like. In some embodiments, the energy and type of ions in the ion beam 112 can be selected to confine the implanted ions to the volume of the stress-compensating layer 108 and prevent the ions from reaching the wafer 102. Ions retained in the stress-compensating layer 108 can generate substitutional defects therein. Furthermore, the ions can also leave traces of vacancy defects along their propagation paths in the stress-compensating layer 108. Substitutional defects and / or vacancies modify (e.g., reduce) the stress in the stress-compensating layer 108 and can reduce the degree of stress overcorrection caused by film deposition. This results in a flattened combination of the wafer 102 and the stress-compensating layer 108.

[0035] While the stress mitigating beam used to modify the stress in the stress-compensating layer 108 is referred to as an ion beam (e.g., ion beam 112) for purposes of detail, throughout this disclosure, the stress mitigating beam may include other species (e.g., electrons), electromagnetic waves (e.g., ultraviolet light, visible light, infrared light, etc.), and / or suitable combinations thereof. The stress mitigating beam impacts the stress-compensating layer 108 and modifies the bonding network of the stress-compensating layer 108. For example, a low-energy stress mitigating beam may interact with surface atoms of the stress-compensating layer 108, for example, removing some of the surface atoms, thereby effectively etching the surface region of the stress-compensating layer 108. The effectiveness of this etching can be controlled by selecting the ion species / radicals / ambient gas. In another example, a high-energy stress mitigating beam may deposit ions within the stress-compensating layer 108. The ions and / or photons may disrupt bonds in the bonding network (or lattice) of the stress-compensating layer 108, thereby forming vacancies therein, which may further induce annealing due to localized heating, UV curing, and / or other effects.

[0036] In some embodiments, simulations (performed in more detail below) may be used to calculate the deformation h based on the corrections. corr The local value of (r, φ) determines the number of ions deposited per small area of ​​the wafer ΔA = ΔxΔy ΔN i The corrected deformation may include saddle deformation, residual deformation, and a parabolic bow-shaped deformation portion A that has been overcorrected by the deposition of the stress compensation layer 108. corr (d) + A4. The desired local density of ions ΔN can be delivered by controlling the scanning speed v of the ion beam 112. i / ΔxΔy. In some embodiments, the profile of the ion beam 112 can be approximated by a Gaussian function, for example, ion flux j(ρ)=j0exp(-x 2 / a 2 -y2 / b 2 ), where x and y are Cartesian coordinates, j0 is the maximum ion flux at the beam center, and a and b are the characteristic spread of the beam along the x and y axes, respectively. Correspondingly, a point at a distance y relative to the beam center path receives an ion dose comprising the following number of ions:

[0037]

[0038] Correspondingly, by reducing the scanning speed v, the number of ions received by various regions of the stress-compensating layer 108 can be increased, and vice versa. In addition, the ion beam 112 can be scanned multiple times with different offsets y, so that various points of the stress-compensating layer 108 are scanned by different factors. For example, after n passes through the ion beam implanter 110 (each at a different distance y relative to the center of the ion beam 112), the ion beam implanter 110 may be fed with a plurality of ions at different distances y from the center of the ion beam 112. k At the corresponding speed v k For area ΔxΔy), the total ion dose received by this area will be

[0039]

[0040] like Figure 1E As shown, the implanted layer 114 formed as part of the stress compensating layer 108 significantly reduces deformation of the wafer 102, particularly the saddle and residual portions thereof.

[0041] Figure 3 An example wafer is shown using a Figures 1A to 1E The stress and deformation of the disclosed process are reduced by 300. Figure 3 As depicted, a 30 cm silicon wafer 102 having a maximum negative deformation of -75.0 μm is first overcorrected to a maximum deformation of +83.5 μm using a silicon nitride tensile stress-compensating layer 108. The stress in the stress-compensating layer 108 is then reduced by forming an implanted layer 114 using an ion beam, resulting in a final maximum deformation of +15.4 μm. Figure 4 An example profile 400 of a Gaussian ion beam 112 that may be used for stress and deformation mitigation in a wafer is shown in accordance with at least one embodiment.

[0042] Figure 1 to Figure 3 The techniques shown for strain and deformation mitigation can also be applied to wafers with complex deformations, where the stress tensor components σ xx and σ yy have different signs, resulting in a saddle-shaped deformation of the wafer. Figure 5An example wafer 500 (e.g., a silicon wafer with a silicon nitride film deposited thereon) having saddle-shaped deformation is shown in accordance with at least one embodiment. As seen in the cross-sectional xz view 502, the stress component σ in the wafer (top layer) xx may be lower than the stress component σ in the film (bottom layer) deposited on the back side of the wafer xx In contrast, as shown in the cross-sectional yz view 504, the stress component σ in the wafer yy may be higher than the stress component σ in the membrane yy In some embodiments, the stress state in the wafer can be represented by a position-dependent stress tensor, which can be approximated as:

[0043]

[0044] This structure of the stress tensor is usually a good approximation because the wafer is generally in pure bending and is independent of the shear stresses represented by the off-diagonal terms in the stress tensor. Correcting for the saddle shape requires special care in the dose map calculation and optimization to ensure that no additional residual terms are introduced into the wafer.

[0045] Figure 6 6 is a flow chart illustrating an example process 600 for mitigating saddle deformation of a wafer according to at least one embodiment. Process 600 can be performed using a semiconductor manufacturing system that includes one or more processing chambers, such as a deposition chamber, a plasma chamber, an etch chamber, a polishing chamber, a film removal chamber, a beam irradiation chamber, an optical inspection chamber, and the like. The processing chambers can be coupled to one or more transfer chambers that can be equipped with robots to handle wafers, such as to move wafers into and out of the processing chambers. The transfer chambers can further be coupled to load-lock chambers (front-end interfaces) that can be coupled to one or more front-opening unified pods (FUPs) that hold bare wafers, processed wafers, partially processed wafers, and the like. The operations performed by the semiconductor manufacturing system (including any, some, or all of the operations of process 600) can be performed in response to instructions issued by a suitable computing device having processing logic and memory for storing instructions.

[0046] At block 610, process 600 includes measuring a shape of a wafer, such as a displacement of a surface (e.g., a top surface) of the wafer as a function of some in-plane coordinates (e.g., polar coordinates z=h(r,φ), Cartesian coordinates z=h(x,y), or any other suitable coordinates). At block 620, process 600 includes decomposing the determined shape via a set of suitable polynomials (e.g., Zernike polynomials) and obtaining a set of polynomial expansion coefficients, {A j} = (A1, A2, A3) A4, A5, A6, A7, ..., each coefficient in the set of coefficients characterizes the degree of presence of a specific element geometry in the wafer deformation.

[0047] At block 630, the coefficients {A j The stress tensor σ is determined by the deformation represented by jk The saddle part of the stress tensor is the part proportional to cos(2φ+α), where the phase α defines the orientation of the saddle shape relative to the coordinate axes. Without loss of generality, for simplicity, we will assume that α=0 (this can be done by simply rotating the coordinate system).

[0048] Based on {A j}, process 600 may include determining the amplitude σ0 of the hoop stress σ(R,φ)=σ0cos(2φ) of the wafer at the wafer edge r=R. This determination may be made based on elastic properties such as Young's modulus, Poisson's ratio, etc. of the wafer. Figure 7A The saddle stress σ0cos(2φ) of an example wafer according to at least one embodiment is shown. Figure 6 At block 640, the amplitude of the saddle portion of the stress, σ0, can be used to identify the properties (e.g., material and thickness) of the target stress-compensating film to be deposited on the wafer. The film can be selected so that the stress tensor of the new wafer plus film structure has a certain sign (e.g., σ(R,φ) < 0). This has the advantage that ion implantation can reduce the amount of stress in the film, whereas reversing the sign of tension in the film using ions can be difficult. Figure 7B Schematically illustrates the selection of a target stress compensation film based on a determined amplitude σ0 according to at least one embodiment. In some embodiments, the thickness of the film can be selected (calculated, simulated, etc.) to induce a uniform (parabolic) deformation in the wafer corresponding to a uniform (or approximately uniform) stress -σ0. Figure 6 At block 650 , process 600 may include depositing a film of a selected material and thickness on the wafer. Figure 7C FIG. 4 shows the stress existing in a wafer after a stress compensation film is deposited on the wafer according to at least one embodiment. Figure 7C As shown, a uniform downward displacement σ0 of the membrane results in the wafer having low stress locations (e.g., approach angles φ=0 and φ=π in this example) and high stress locations (e.g., approach angles φ=π / 2 and φ=3π / 2 in this example).

[0049] A film is deposited thereon and has Figure 7CThe stressed wafer shown has a cylindrical type deformation that can be characterized by the following combination of Z4 and Z6 (and / or Z5 for other choices of coordinate system, and the corresponding phase and α), referred to herein as the cylindrical polynomial Z cyl , that is, the displacement (until uniform) is equal to:

[0050]

[0051] The first term Z6 corresponds to the stress of the wafer itself (see Figure 7A ), the second item corresponds to the uniform stress induced by a properly chosen membrane (see Figure 7B ).

[0052] exist Figure 6 At block 660, a dose for edge ion implantation may be calculated, for example based on the amplitude σ0 determined at block 640. Edge ion implantation performed into the stress compensating film relieves stress in the film, thereby relieving stress in the wafer, as shown in FIG. Figure 7D More specifically, edge ion implantation significantly reduces the magnitude of hoop stress.

[0053] σ(R,φ)=-2σ0cos 2 φ→-2σ res cos 2 φ,σ res <<σ0

[0054] With small residual hoop stress σ res .

[0055] Figures 8A to 8D Example ion implantations that may be used for ion implantation performed to mitigate saddle wafer deformation are shown in accordance with at least one embodiment. Figure 8A An arc implant 802 is shown, in accordance with at least one embodiment, wherein a uniform ion implant dose is applied within a specific uniform width edge region of a stress-compensating film. For example, a constant ion density n0 (defined, for example, as the ion flux delivered by the ion beam multiplied by the beam exposure time) may be deposited within a segment of width d and angle φ0:

[0056] n(r,φ)=n0Θ(Rr)Θ(r+dR)Θ(sin(φ0 / 2)-|sinφ|)

[0057] where Θ() is the Heaviside step function. In some embodiments, the angle φ0 may be equal to or about 90°. In some embodiments, the angle φ0 may be less than 90° (e.g., 60°, 45°, 30°, etc.) or greater than 90° (e.g., 100°, 110°, 120°, etc.). In some embodiments, the width of the edge implant may be within d≈1 - 10 mm. In some embodiments, the width of the edge implant may be less than 1 mm or greater than 10 mm. In some embodiments, the width of the edge implant may be equal to or less than 10% of the diameter of the wafer or some other fraction of the diameter (e.g., 5%, 20%, etc.).

[0058] Figure 8B A semi - circular edge implant 804 is shown, where a uniform ion implantation dose is applied within an edge region having a thickness d(φ) that varies (with angle φ), e.g.,

[0059] n(r,φ) = n0Θ(R - r)Θ(r + d(φ) - R)

[0060] The thickness d(φ) may have a maximum value at φ = ±π / 2 and may vanish along the lines φ0 = ±45° and = ±135° lines (or some other lines). In some embodiments, the inner boundary of the semi - circular implant 804 may be parallel to Figure 8B the horizontal axis in (e.g., the dashed boundary 805 indicated by the dashed line), e.g.,

[0061] n(r,φ) = n0Θ(R - r)Θ(r|sinφ|+d - R)

[0062] Figure 8C A gradient edge implant 806 according to at least one embodiment is shown, where a non - uniform ion implantation dose is applied within the edge region. In some embodiments, the ion implantation density may vary linearly (or according to some non - linear dependence) with the radial distance r within the implantation region, e.g.,

[0063]

[0064] where R - d < r < R and sin(φ0 / 2) < |sinφ| (otherwise zero). In this example, the ion implantation density varies (e.g., increases) from n1 at r = R - d to n2 at r = R. In some embodiments, the ion implantation density may vary with the vertical distance (y = sinφ) from the center of the wafer, e.g.,

[0065]

[0066] In some embodiments, a non-uniform (non-uniform with azimuthal angle φ) ion implantation dose may be applied to the film, for example, as a piecewise linear function of φ,

[0067]

[0068] In some embodiments, a smoothly varying (smoothly varying with azimuthal angle φ) ion implantation dose may be applied non-uniformly to the film, for example, a piecewise linear function,

[0069]

[0070] Ion implantation doses that follow many other functions may be used, such as functions that vary smoothly with both radial distance and azimuthal angle.

[0071] Figure 8D A custom shaped ion implantation according to at least one embodiment is shown. For example, a custom shaped implantation may include combining Figures 8A to 8C Any of the implants mentioned (or similar implants). In one non-limiting example, the custom-shaped implants can include a meniscus implant 808 and one or more longitudinal implants (e.g., implant 810). Meniscus implant 808 and longitudinal implant 810 can have different ion implant densities, for example, meniscus implant 808 can have a higher ion implant density than longitudinal implant 810. Longitudinal implant 810 can be used to prevent (or reduce) the formation of ripples and / or other bulk deformations that may be caused by edge implants.

[0072] exist Figure 6 At block 670, use Figures 8A to 8D Ion implantation is performed at one of the ion implantation doses shown (or any other similar dose), for example as described below in conjunction with Figures 11A to 11B As disclosed. After the ions are implanted into the film, the process 600 can continue to make new measurements of the shape of the wafer at box 680 to evaluate the post-implantation residual stresses that are still present in the wafer. For a variety of reasons, the wafer after implantation may still show a certain amount of stress and deformation. Specifically, edge implantation can reduce the stress around the periphery of the wafer (hoop stress), but a certain amount of residual stress (also referred to as higher-order stress in this article) may still exist in the body of the wafer, resulting in changes in the wafer profile (waviness). In addition, the thickness of the stress-compensating film typically has an uneven radial profile near the edge, for example, gradually decreasing near the edge of the wafer, for example, from about 300 nanometers at about 7-10 mm from the edge to about 150 nanometers just on the edge (as an illustrative example). This radial non-uniformity may further increase the amount of waviness.

[0073] Back to Figure 6To reduce waviness and other residual deformations and stresses in the wafer, the process 600 may select one of the additional implant assist features at block 690 . Figures 9A to 9C Some examples of implant assist features that may be used to mitigate residual stress in accordance with at least one embodiment are shown. Figure 9A An example "oval" dose map 900 is schematically shown, where lighter areas 904 indicate areas of the wafer 902 that receive ions (or receive a higher ion dose), and darker areas 906 of the wafer 902 do not receive ions (or receive a lower ion dose). Figure 9B An example "hourglass shaped" dose graph 910 is schematically shown. Figure 9C An example "butterfly-shaped" dose graph 920 is schematically shown.

[0074] Can be Figure 6 The various implant assist features 910-930 (and many other features) are included in the selection process performed at block 690. In one example, non-limiting embodiment, each implant assist feature may be encoded (and stored in computer memory) as a mask M. j (x, y), the mask identifies the area to receive the ion implantation (index j enumerates the various masks that have been defined). In some embodiments, the mask M j (x,y) can be binary, for example, M if the point (x,y) belongs to one of the bright regions 904 intended to receive ions. j (x,y)=1, and M if the point (x,y) belongs to one of the dark regions 906 that is not intended to receive ions j (x, y) = 0. The residual stress σ measured in the wafer at step 680 (or inferred from the measurement of the residual deformation of the wafer) can be calculated by calculating a set of overlap factors (or any other suitable similarity values) that represent the similarity between the residual stress and the mask of the corresponding implant assist feature. res (x,y) is compared with the available mask (the negative sign is used in case the residual stress is negative, e.g. Figure 7D shown),

[0075] O j =-∫∫dx dy σ res (x,y)M j (x,y)

[0076] where the integral (or the corresponding discrete two-dimensional sum) extends over the area of ​​the circle. One can choose the one with the highest overlap O j (or one of the highest overlaps) of the implant assist feature to apply a stress compensation film on the wafer. The ion beam density can then be based on σ res The amplitude of (x,y) is selected (for example, to make the ion beam density and σres (x, y) are proportional), calculated using Monte Carlo simulation or other suitable techniques. In some embodiments, the mask M j (x,y) can be a continuous function of x,y.

[0077] At block 695, selected implant assist features may be applied to the stress compensation film, for example, as described below in conjunction with Figures 11A to 11B As disclosed by Figure 6 As indicated by the dashed arrows in , blocks 680 - 695 of process 600 may be iteratively repeated until the stress or deformation of the wafer is reduced to below a target tolerance.

[0078] Figure 10A Schematically illustrates an example wafer's response 1000 to an "oval" dose map 900 that may be used for Figure 6 Response 1000 is calculated for an undeformed reference wafer on which a reference film is deposited. Wafer deformation after ion implantation is shown in a two-dimensional (2D) thermal map 1002 and a three-dimensional (3D) map 1004. 2D thermal maps 1006, 1008 and 3D maps 1008, 1010 illustrate the decomposition of wafer deformation into a secondary component (2D maps 1006 and 1008) and a residual component (2D maps 1010 and 1012), the secondary component including parabolic deformation and saddle deformation. Figure 10B Schematically illustrates an example wafer's response 1001 to a "butterfly" dose map 920 that may be used to generate a dose pattern in accordance with at least one embodiment. Figure 6 600 of technology.

[0079] Figure 11AAn ion implantation system 1100 is schematically illustrated that can perform ion implantation into a stress-compensating layer according to at least one embodiment. The ion implantation system 1100 can be or include the ion beam implanter 110 of FIG. 1 . Although, for the sake of detail, the stress mitigation beam used to modify the stress in the stress-compensating layer 108 is referred to as an ion beam (e.g., ion beam 112), in some embodiments, the stress mitigation beam can include particles of other substances (e.g., electrons), electromagnetic waves (e.g., ultraviolet light, visible light, infrared light, etc.), and / or suitable combinations thereof. The ion implantation system 1100 can include an ion source 1102 for generating an ion beam 1104. The ion source 1102 can include a chamber (e.g., a plasma chamber) for generating ions. The ion source 1102 can be powered by a power supply 1106 and can include an extraction electrode assembly (not shown). The ion implantation system 1100 can include a mass spectrometer 1108 and a collimating and focusing column 1110. The collimating and focusing column 1110 can direct the ion beam 112 toward the wafer 102. The wafer 102 can be supported by a support table 1112. In some embodiments, the support table 1112 and wafer 102 can remain stationary while components of the ion implantation system 1100 are repositioned relative to the wafer 102 while the ion beam 112 is scanning across the wafer 102. In some embodiments, the ion implantation system 1100 can be stationary while the support table 1112 repositions the wafer 102. The ion beam 112 can be scanned in multiple directions, such as along the x-axis and along the y-axis according to any suitable predetermined pattern, such as back and forth along the x-axis, in a spiral pattern, etc. In various embodiments, the ion beam 112 can be scanned at a frequency of several hertz, tens of hertz, hundreds of hertz, several kilohertz, or higher.

[0080] The operation of the ion implantation system 1100 can be controlled by a controller 1114, which can include any suitable computing device, microcontroller or any other processing device having a processor (e.g., a central processing unit (CPU), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.) and a memory device (e.g., a random access memory (RAM), a read-only memory (ROM), flash memory, etc.) or any combination of the above. The controller 1114 can control the operation of the power supply 1106, the support table 1112 and / or various other components and modules of the ion implantation system 1100. The controller 1114 can include an ion beam simulation module 1116 that is capable of performing simulations to determine a target intensity of the ion beam 112 to be used to mitigate various wafer deformations. In some embodiments, the support table 1112 can apply a tilt to the wafer 102 (e.g., in one or two spatial directions) to change the angle of incidence of the ion beam 112 relative to the wafer 102. In some embodiments, the controller 1114 can tilt the ion implantation system 1100 relative to the wafer 102 instead of tilting the wafer 102. In some embodiments, for example, as Figure 11B As shown, the support stage 1112 can apply a tilt to the wafer 102 (e.g., in one or two spatial directions) to change the angle of incidence of the ion beam 112 relative to the wafer 102. In some embodiments, the controller 1114 can tilt the ion implantation system 1100 relative to the wafer 102 rather than tilting the wafer 102.

[0081] Figure 12 Described is a block diagram of an example computer system 1200 that can support the operation of the present disclosure according to at least one embodiment. In various illustrative examples, the example computer system 1200 can be or include the controller 1114 of Figure 11. The example computer system 1200 can be connected to other computer systems in a LAN, an internal network, an external network and / or the Internet. The computer system 1200 can operate as a server in a client-server network environment. The computer system 1200 can be a personal computer (PC), a set-top box (STB), a server, a network router, a switch or a bridge, or any device that can execute a set of instructions (sequentially or otherwise) that specify the actions to be taken by the device. Further, although only a single example computer system is described, the term "computer" should also be considered to include a collection of any computers that execute a set (or multiple sets) of instructions to perform any one or more methods discussed herein, either individually or collectively.

[0082] The example computer system 1200 may include a processing device 1202 (also referred to as a processor or CPU), a main memory 1204 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous dynamic random access memory (SDRAM)), etc.), a static memory 1206 (e.g., flash memory, static random access memory (SRAM), etc.), and a secondary memory (e.g., a data storage device 1218), which may communicate with each other via a bus 1230.

[0083] The processing device 1202 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, or the like. The processing device 1202 may include processing logic 1226. The processing device 1202 may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, a processor implementing other instruction sets, or a processor implementing a combination of instruction sets. The processing device 1202 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. According to one or more aspects of the present disclosure, the processing device 1202 may be configured to execute instructions for implementing the example process 600 for mitigating saddle deformation of a wafer.

[0084] The example computer system 1200 may further include a network interface device 1208, which may be communicatively coupled to a network 1220. The example computer system 1200 may further include a video display 1210 (e.g., a liquid crystal display (LCD), a touch screen, or a cathode ray tube (CRT)), an alphanumeric input device 1212 (e.g., a keyboard), a cursor control device 1214 (e.g., a mouse), and an acoustic signal generating device 1216 (e.g., a speaker).

[0085] Data storage device 1218 may include a computer-readable storage medium (or more specifically, a non-transitory computer-readable storage medium) 1224 on which is stored one or more sets of executable instructions 1222. Executable instructions 1222 may include executable instructions for implementing example process 600 for mitigating saddle deformation of a wafer, according to one or more aspects of the present disclosure.

[0086] The executable instructions 1222 may also reside, completely or at least partially, within the main memory 1204 and / or within the processing device 1202 during execution of the instructions by the example computer system 1200, the main memory 1204 and the processing device 1202 also constituting computer-readable storage media. The executable instructions 1222 may further be transmitted or received over a network via the network interface device 1208.

[0087] Although Figure 12 Although computer-readable storage medium 1224 is shown as a single medium, the term "computer-readable storage medium" should also be considered to include a single medium or multiple media (such as a centralized or distributed database and / or associated caches and servers) that store one or more sets of operating instructions. The term "computer-readable storage medium" should also be considered to include any medium that can store or encode a set of instructions for execution by a machine, causing the machine to perform any one or more of the methods described herein. Thus, the term "computer-readable storage medium" should be considered to include (but not be limited to) solid-state memories and optical and magnetic media.

[0088] Some portions of the foregoing detailed description are presented in the form of algorithms and symbolic representations of operations performed on data bits within a computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate their work to other persons skilled in the art. Here, and generally speaking, an algorithm is considered to be a self-consistent sequence of steps leading to a desired result. These steps are those that require physical manipulation of physical quantities. Typically, although not necessarily, these quantities take the form of electrical or magnetic signals that can be stored, transferred, combined, compared, and otherwise manipulated. It turns out that it is sometimes convenient, primarily for common reasons, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, etc.

[0089] It should be remembered, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise, it will be understood from the following discussion that discussions throughout the description utilizing terms such as "identify," "determine," "store," "adjust," "result in," "return," "compare," "create," "stop," "load," "copy," "throwing," "replace," "execute," etc., refer to actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage, transmission, or display devices.

[0090] Examples of the present disclosure also relate to an apparatus for performing the methods described herein. This apparatus may be specially constructed for the desired purpose, or it may be a general-purpose computer system selectively programmed by a computer program stored in the computer system. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk (including optical disks, CD-ROMs, and magneto-optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic disk storage media, optical storage media, flash memory devices, other types of machine-accessible storage media, or any type of medium suitable for storing electronic instructions, each of which is coupled to a computer system bus.

[0091] The methods and displays proposed herein have no inherent relevance to any particular computer or other device. Various general-purpose systems can be used together with the programs taught herein, or it may prove convenient to construct a more specialized device to perform the required method steps. The structures required for various of these systems will appear in the elaboration described below. In addition, the scope of this disclosure is not limited to any specific programming language. It will be understood that various programming languages ​​can be used to implement the teachings of this disclosure.

[0092] It is to be understood that the above description is intended to be illustrative and not restrictive. Many other examples of embodiments will be apparent to those skilled in the art upon reading and understanding the above description. Although this disclosure describes specific examples, it will be appreciated that the systems and methods of the present disclosure are not limited to the examples described herein, but may be practiced with modification within the scope of the appended claims. Accordingly, the specification and drawings should be viewed in an illustrative and not restrictive sense. The scope of the present disclosure should, therefore, be determined with reference to the appended claims and the full scope of equivalents to which such claims are entitled.

Claims

1. A method for correcting out-of-plane deformation of a substrate, the method comprising: obtaining a profile of the out-of-plane deformation of the substrate using optical inspection data; identifying one or more parameters characterizing saddle stress of the substrate using the obtained profile; calculating one or more properties of a stress compensating layer (SCL) for the substrate using the identified one or more parameters; depositing the SCL on the substrate; and Applying a stress mitigation beam to a plurality of edge regions of the SCL is performed, wherein settings of the stress mitigation beam are determined using the identified one or more parameters. 2 . The method of claim 1 , wherein the one or more characteristics of the SCL are calculated so that the stress in the substrate has the same sign throughout the entire area of ​​the substrate. 3 . The method of claim 1 , wherein a width of each of the plurality of edge regions of the SCL is equal to or less than 30% of a diameter of the substrate. 4 . The method of claim 1 , wherein the stress mitigation beam applies a spatially uniform ion dose to the plurality of edge regions of the SCL. 5 . The method of claim 1 , wherein the stress mitigation beam applies a radially varying ion dose to the plurality of edge regions of the substrate. The method of claim 1 , wherein the stress mitigation beam applies an azimuthally varying ion dose to the plurality of edge regions of the SCL.

7. The method of claim 1 , wherein the one or more characteristics of the SCL include one or more of the following: the SCL material, or The thickness of the SCL.

8. The method of claim 1 , wherein the setting of the stress mitigation beam comprises one or more of: the particle type of the stress relief beam, the energy of the particles of the stress mitigating beam, or An angle of incidence of the particles of the stress mitigation beam on the SCL.

9. The method of claim 1, further comprising: obtaining an updated profile of the out-of-plane deformation of the substrate in response to applying the stress mitigating beam to the plurality of edge regions of the SCL; identifying residual stresses in the substrate based on the updated profile; selecting a target stress mitigation beam pattern from a plurality of stored stress mitigation beam patterns based on the residual stress; and Additional stress mitigation beams are applied to regions of the SCL identified by the target stress mitigation beam pattern.

10. The method of claim 9, wherein selecting the stress mitigation beam pattern comprises: A similarity of the residual stress in the substrate to each stored stress mitigation beam pattern of at least a subset of the plurality of stored stress mitigation beam patterns is calculated.

11. The method of claim 1 , wherein the substrate comprises a front side and a back side, wherein the front side comprises one or more fabricated features, and wherein the SCL is deposited on the back side of the substrate.

12. A system comprising: Memory; and a processing device, communicatively coupled to the memory, the processing device being configured to: obtaining a profile of the out-of-plane deformation of the substrate using optical inspection data; identifying one or more parameters characterizing saddle stress of the substrate using the obtained profile; calculating one or more properties of a stress compensating layer (SCL) for the substrate using the identified one or more parameters; depositing the SCL on the substrate; and Applying a stress mitigation beam to a plurality of edge regions of the SCL is performed, wherein settings of the stress mitigation beam are determined using the identified one or more parameters.

13. The system of claim 12, wherein the one or more characteristics of the SCL are calculated so that stress in the substrate has the same sign throughout the entire area of ​​the substrate.

14. The system of claim 12, wherein a width of each of the plurality of edge regions of the SCL is equal to or less than 30% of a diameter of the substrate.

15. The system of claim 12, wherein the stress mitigation beam applies at least one of: applying a spatially uniform ion dose to the plurality of edge regions of the SCL, applying radially varying ion doses to the plurality of edge regions of the substrate, or An azimuthally varying ion dose is applied to the plurality of edge regions of the SCL.

16. The system of claim 12, wherein the one or more characteristics of the SCL include one or more of the following: the SCL material, or The thickness of the SCL.

17. The system of claim 12, wherein the settings of the stress mitigation beam include one or more of: the particle type of the stress relief beam, the energy of the particles of the stress mitigating beam, or An angle of incidence of the particles of the stress mitigation beam on the SCL.

18. The system of claim 12, wherein the processing device is further configured to: obtaining an updated profile of the out-of-plane deformation of the substrate in response to applying the stress mitigating beam to the plurality of edge regions of the SCL; identifying residual stresses in the substrate based on the updated profile; selecting a target stress mitigation beam pattern from a plurality of stored stress mitigation beam patterns based on the residual stress; and Additional stress mitigation beams are applied to regions of the SCL identified by the target stress mitigation beam pattern.

19. The system of claim 18, wherein to select the stress mitigation beam pattern, the processing device is configured to calculate a similarity of the residual stress in the substrate to each stored stress mitigation beam pattern in at least a subset of the plurality of stored stress mitigation beam patterns.

20. A semiconductor manufacturing system, comprising: one or more processing chambers for processing substrates; and A computing device for: obtaining a profile of out-of-plane deformation of the substrate using optical inspection data; identifying one or more parameters characterizing saddle stress of the substrate using the obtained profile; calculating one or more properties of a stress compensating layer (SCL) for the substrate using the identified one or more parameters; depositing the SCL on the substrate; and Applying a stress mitigation beam to a plurality of edge regions of the SCL is performed, wherein settings of the stress mitigation beam are determined using the identified one or more parameters.

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