Pump controller for multiple charge pump units

Abstract

In one example, a system includes: a plurality of charge pump units connected in parallel to receive an input voltage and generate an output voltage greater than the input voltage; and a pump controller to provide a pump signal to a first charge pump unit of the plurality of charge pump units and to provide a sequentially delayed version of the pump signal to other charge pump units of the plurality of charge pump units.

Description

[0001] Priority Declaration

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 442,807, filed on February 2, 2023, entitled “Charge Pump Comprising Latch-Based Self-Oscillating Voltage Regulator,” and U.S. Patent Application No. 18 / 135,395, filed on April 17, 2023, entitled “Pumping Controller For A Plurality Of Charge Pump Units.” Technical Field

[0003] A pump controller for providing a pump signal to a plurality of charge pump units is disclosed. Background Art

[0004] Charge pumps are commonly used in semiconductor devices to generate voltages greater than the available supply voltage, which is often denoted as VDD. For example, charge pumps are used in flash memory systems to generate voltages greater than VDD for programming, erasing, or reading operations.

[0005] Prior art designs include multiple charge pump units operating in parallel. One limitation of these prior art designs is that, because each charge pump unit begins its charging and discharging operations simultaneously based on a common pumping signal, a power surge occurs at the beginning of each charging cycle, which can damage circuits sensitive to current or voltage surges. Another disadvantage of prior art designs is that, even when the charge pump reaches the desired voltage level, the charging operation will sometimes continue for a period of time before stopping, causing the output to become higher than the desired level.

[0006] What is needed is an improved charge pump design and control system. Summary of the Invention

[0007] A pump controller for a plurality of charge pumps is disclosed. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 A voltage regulator comprising a pump controller and a plurality of charge pump cells is depicted.

[0009] Figure 2 Describes the use Figure 1 Timing diagram of the voltage regulator.

[0010] Figure 3 and Figure 4 Depicts Figure 1 Method of operating a voltage regulator Detailed implementation

[0011] Figure 1 A system including a voltage regulator 100 is depicted. The voltage regulator 100 includes charge pump units 102-1, 102-2, 102-3, and 102-4. The charge pump units 102-1, 102-2, 102-3, and 102-4 are connected in parallel and each receive an input voltage VDD and generate an output voltage VD25 greater than the input voltage. In this example, four charge pump units are connected in parallel to provide the output voltage VD25 so as to be able to supply power to an attached load without a voltage drop.

[0012] The voltage regulator 100 further includes a pump controller 101. The pump controller 101 includes a voltage divider which includes a first resistor 103 and a second resistor 104, and the voltage divider generates a divided voltage V proportional to the output voltage VD25 at node 113 S . The comparator 106 receives the divided voltage V on its first non-inverting input S , and receives a reference voltage VREF on its second inverting input and compares them. When V S >VREF, the output VDET of the comparator 106 is high, and when V S <VREF, the output of the comparator 106 is low. The capacitor 105 transfers the ripple from VD25 to V S to accelerate the comparator 106.

[0013] The latch 107 is a gated D-latch with a reset signal and operates according to the following truth table:

[0014] R D LAT Q 1 0 / 1 0 / 1 0 0 0 / 1 0 D 0 0 / 1 1 Q

[0015] The signal RESET is provided on the reset port R of the latch 107 by other logic components or controllers not shown. The latch enable port LAT of the latch 107 receives the signal VDET from the comparator 106. The data port D of the latch 107 receives a signal from the inverter 112, which will be described in more detail below. As shown in the above truth table, when the RESET signal on the reset port R is asserted, the output Q is 0 regardless of the values received by the data port D and the latch enable port LAT. When the RESET signal on the reset port R is not asserted and the signal received by the latch enable port LAT is asserted (this will be when V S>When it occurs at VREF, indicating that VD25 has reached or exceeded the desired voltage, the output Q will hold its level regardless of the value subsequently received at the data port D. When the RESET signal on the R port is not asserted and the signal received by the latch enable port LAT is not asserted (this will occur when V S <When it occurs at <VREF, indicating that VD25 is less than the desired voltage and additional pumping is desirable), the output Q will be whatever value is received at the data port D at that time.

[0016] The output Q is the signal PMP CLK, which is provided as a pumping signal to the input sections of the charge pump unit 102-1 and the delay circuit 108. The delay circuit 108 passes the received signal PMP CLK, but generates the signal PMP CLK’ at the output section of the delay circuit 108 with an increased delay.

[0017] PMP CLK’ is provided as a pumping signal to the input sections of the charge pump unit 102-2 and the delay circuit 109. The delay circuit 109 passes the received signal PMP CLK’, but generates the signal PMP CLK” at the output section of the delay circuit 109 with an increased delay.

[0018] PMP CLK” is provided as a pumping signal to the input sections of the charge pump unit 102-3 and the delay circuit 110. The delay circuit 110 passes the received signal PMP CLK”, but generates the signal PMP CLK”’ at the output section of the delay circuit 110 with an increased delay.

[0019] PMP CLK”’ is provided as a pumping signal to the input sections of the charge pump unit 102-4 and the delay circuit 111. The delay circuit 111 passes the received signal PMP CLK”’, but generates the signal PMP CLK”” at the output section of the delay circuit 111 with an increased delay. In this example, the charge pump unit 102-4 is the last pump unit among the plurality of pump units 102.

[0020] The inverter 112 receives the signal PMP CLK”” and generates the inverse of PMP CLK””, which is subsequently provided as the data signal at the data port D of the latch 107.

[0021] The end result is that when RESET is low and VDET is low, the pump controller generates an oscillating signal (PMP CLK), as well as sequentially delayed versions of the oscillating signal (PMP CLK′, PMP CLK″, PMP CLK′″, and PMP CLK″”). When VDET goes high, PMP CLK stabilizes at its existing value, and the oscillation of the oscillating signal (PMP CLK) and the sequentially delayed versions of the oscillating signal (PMP CLK′, PMP CLK″, PMP CLK′″, and PMP CLK″”) ceases.

[0022] Therefore, it can be understood that the voltage regulator 100 includes: a plurality of charge pump units 102, which are used to receive an input voltage (VDD) and generate an output voltage (VD25) greater than the input voltage; and a pump controller 101, which is used to provide a pump signal (PMPCLK) to a first pump unit (e.g., pump unit 102-1) among the plurality of pump units, and provide corresponding sequentially delayed versions of the pump signal (PMP CLK', PMP CLK", and PMP CLK'") to other pump units (e.g., pump units 102-2, 102-3, and 102-4) among the plurality of pump units.

[0023] Although the voltage regulator 100 includes four pump cells 102 in this example, it should be understood that the voltage regulator 100 may alternatively include fewer than four pump cells 102 or more than four pump cells 102 .

[0024] Figure 2 A timing diagram 200 of the voltage regulator 100 is depicted, and the signals PMP CLK, VD25, and VDET are shown. Unlike some prior art systems, the output voltage VD25 does not undergo an additional charging cycle that causes the output voltage to become higher than the desired voltage (as opposed to the dashed line shown for VD25, which indicates how VD25 may experience an additional voltage boost in some prior art systems). This is because VDET is used as the LAT input of the latch 107. That is, when VDET goes high, the output PMP CLK of the latch 107 will remain in its current state and will stop oscillating (as opposed to the dashed line shown for PMP CLK, which indicates how PMP CLK may behave in some prior art systems).

[0025] Figure 3 Depicts Figure 1 and Figure 2A method 300 of operating the voltage regulator 100 is provided. The method 300 includes: receiving an input voltage (301) by a plurality of charge pump units connected in parallel; providing a pumping signal (302) to a first pump unit of the plurality of charge pump units; providing sequentially delayed versions of the pumping signal to other charge pump units of the plurality of charge pump units (303); and (304) generating an output voltage greater than the input voltage by the plurality of charge pump units.

[0026] Figure 4 Method 400 is depicted. Method 400 is an example of performing the method of method 300 of providing a pumping signal (302) to a first charge pumping cell of a plurality of charge pumping cells and providing sequentially delayed versions (303) of the pumping signal to other charge pumping cells of the plurality of charge pumping cells. Method 400 includes: comparing a voltage proportional to an output voltage with a reference voltage to generate a comparator output (401); receiving the comparator output as a latch enable signal (402) by a gated D latch having a reset port; receiving a data signal on a data port and a reset signal on a reset port by the gated D latch (403); generating a pump signal as an output (404) by the gated D latch; generating sequentially delayed versions of the pump signal by corresponding delay circuits (405); receiving an input by an inverter, the input including a delayed version of the pump signal provided to a last pump unit in other pump units in a plurality of pump units (406); generating an output by the inverter (407); and providing the output of the inverter as a data signal to the latch (408).

[0027] It should be noted that, as used herein, the terms "over" and "on" include both "directly on" (without intervening materials, elements, or spaces therebetween) and "indirectly on" (with intervening materials, elements, or spaces therebetween). For example, forming an element "over a substrate" may include forming the element directly on the substrate without intervening materials / elements therebetween, as well as forming the element indirectly on the substrate with one or more intervening materials / elements therebetween.

Claims

1. A system, comprising: a plurality of charge pump units connected in parallel to receive an input voltage and generate an output voltage greater than the input voltage; and A pump controller is configured to provide a pump signal to a first charge pump unit of the plurality of charge pump units and to provide sequentially delayed versions of the pump signal to other charge pump units of the plurality of charge pump units.

2. The system of claim 1 , wherein the pump controller comprises: a voltage divider for receiving the output voltage and generating a lower voltage at a node, the voltage divider comprising a first resistor coupled to a second resistor at the node, wherein the first resistor receives the output voltage; and A capacitor is coupled between the output voltage and the node.

3. The system of claim 2, wherein the pump controller comprises: A comparator includes a first input coupled to the node, a second input coupled to a reference voltage, and an output.

4. The system of claim 3, wherein the pump controller comprises: A latch is configured to generate a latch output in response to an output from the comparator received on a latch enable port, a data signal received on a data port, and a reset signal received on a reset port. 5 . The system of claim 4 , wherein the latch output is provided as the pump signal to a first pump cell among a plurality of pump cells.

6. The system of claim 5, wherein the pump controller comprises: A delay circuit is provided for generating the sequentially delayed versions of the pump signal.

7. The system of claim 6, wherein the pump controller comprises: an inverter configured to receive as input the delayed version of the pump signal provided to a last pump unit among the other pump units in the plurality of pump units and generate an output; The output of the inverter is provided to the latch as the data signal.

8. A method comprising: receiving an input voltage from a plurality of charge pump units connected in parallel; providing a pumping signal to a first pump unit of the plurality of charge pump units; providing sequentially delayed versions of the pump signal to other charge pump cells of the plurality of charge pump cells; as well as An output voltage greater than the input voltage is generated by the plurality of charge pump units.

9. The method according to claim 8, comprising: A voltage proportional to the output voltage is compared to a reference voltage to generate a comparator output.

10. The method according to claim 9, comprising: receiving the comparator output at a latch enable port by a gated D latch having a reset port; The latch receives a data signal on the data port and a reset signal on the reset port; as well as The pump signal is generated as an output by the latch.

11. The method according to claim 10, comprising: The sequentially delayed versions of the pump signal are generated by respective delay circuits.

12. The method according to claim 11, comprising: receiving an input by an inverter, the input comprising the delayed version of the pump signal provided to a last pump cell among the other pump cells in the plurality of pump cells; as well as An output is generated by the inverter.

13. The method according to claim 12, comprising: The output of the inverter is provided to the latch as the data signal.

14. A system comprising: A voltage regulator is configured to generate a pumping signal for a first pump unit of a plurality of pump units connected in parallel and to generate sequentially delayed versions of the pumping signal for other pump units of the plurality of pump units.

15. The system according to claim 14, comprising: a voltage divider for receiving output voltages from the plurality of pump cells and generating a voltage proportional to the output voltages at a node, the voltage divider comprising a first resistor coupled to a second resistor at the node, and wherein the first resistor receives the output voltage; and A capacitor includes a first plate receiving the output voltage and a second plate coupled to the node.

16. The system according to claim 15, comprising: A comparator includes a first input coupled to the node, a second input coupled to a reference voltage, and an output.

17. The system according to claim 16, comprising: A latch is configured to generate a latch output in response to an output from the comparator received on a latch enable port, a data signal received on a data port, and a reset signal received on a reset port.

18. The system of claim 17, wherein the latch output is provided as the pump signal.

19. The system according to claim 18, comprising: A delay circuit is provided for generating the sequentially delayed versions of the pump signal.

20. The system of claim 19, comprising: An inverter is configured to receive as an input a final version of the sequentially delayed versions of the pump signal and to generate an output that is provided to the latch as the data signal.

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