Dynamic current absorption circuit for ultrasonic transmitting and receiving chip

Abstract

The invention provides a dynamic current absorption circuit for an ultrasonic transmitting and receiving chip. The dynamic current absorption circuit comprises a transmitting circuit, a diode D1, a diode D2, a receiving driving circuit, a high-voltage NMOS (N-channel Metal Oxide Semiconductor) tube NH1, a low-voltage NMOS tube NL1, a low-voltage NMOS tube NL2, a transducer Z and a dynamic current absorption circuit, the output of the transmitting circuit is connected with the anode of the diode D1 and the cathode of the diode D2; the cathode of the diode D1, the anode of the diode D2, the drain electrode of the high-voltage NMOS tube NH1, the output of the dynamic current absorption circuit and the transducer Z are connected to an HVOUT end; and the dynamic current absorption circuit generates a narrow pulse signal through the logic control circuit to control the switching tube to form a low-resistance path so as to absorb the dynamic current in the switching process of the transmitting state and the receiving state, and the dynamic current absorption circuit recovers to a high-resistance state after the switching is finished. By adding the dynamic current absorption circuit, a low-resistance path is formed at the switching moment, dynamic current is absorbed and prevented from being conducted to the transducer, interference signals are effectively restrained, and the imaging quality is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of ultrasonic imaging technology in ultrasonic medical equipment, and in particular to a dynamic current absorption circuit for an ultrasonic transmitting and receiving chip. Background Art

[0002] In ultrasound medical equipment, ultrasound imaging primarily utilizes the transducer's piezoelectric effect to convert high-frequency, high-voltage electrical signals into ultrasonic signals, which are transmitted into the human body for detection. The transducer also converts the received acoustic signals into smaller-amplitude electrical signals for processing and analysis, ultimately forming an ultrasound image. The chips used in ultrasound systems can be broadly categorized by function: transmitter chips, receiver chips, analog front-end (AFE) chips, and digital signal processors (DSP). The transmitter chip generates high-voltage, high-frequency voltage signals (+-20V to +-100V) and transmits them to the transducer. The receiver chip receives the transducer's echo signal (in the uV to mV range). The AFE chip amplifies, filters, and performs analog-to-digital conversion on the echo signal. The digital signal processor processes and analyzes the data, ultimately generating the image. The transmitting chip and the receiving chip are usually integrated together to reduce costs. When the chip switches from transmitting mode to receiving mode, a dynamic current is generated and transmitted to the transducer to generate a spike voltage. As the transducer receiving sensitivity continues to increase in modern applications, this spike voltage can easily activate the transducer and generate an interfered echo signal, thereby affecting the imaging quality.

[0003] The output structure of traditional transmitting and receiving chips is as follows: Figure 1 As shown, the operating principle is as follows: When the chip is in the transmitting state, the transmitting circuit 11 generates a high-voltage, high-frequency voltage signal, which is transmitted through diode 12 to the transducer 15 at the HVOUT end (15 is the transducer equivalent circuit). At this time, the receiving driver circuit 13 turns off the high-voltage NMOS transistor NH1 and the low-voltage NMOS transistor NL1, and turns on the low-voltage NMOS transistor NL2, preventing the transmitted signal from being transmitted to the LVOUT end and achieving high isolation (LVOUT is the echo signal receiving end). When the chip is in the receiving state, the output of the transmitting circuit I1 is GND. The receiving driver circuit turns on the high-voltage NMOS transistor NH1 and the low-voltage NMOS transistor NL1, and turns off the low-voltage NMOS transistor NL2. The transducer transmits the echo signal through the high-voltage NMOS transistor NH1 and the low-voltage NMOS transistor NL1 to the LVOUT end. Because the received signal is very weak (mV level), diodes D1 and D2 isolate the echo signal at the HVOUT end from the transmitting circuit. During the switching process of transmitting and receiving, that is, in the process of driving the switch tube to turn on or off, there is a dynamic current. This current flowing into the transducer will generate an additional spike voltage signal to activate the transducer and generate an interfered echo signal.

[0004] When traditional transmitter and receiver chips switch between states, dynamic current flows directly into the transducer, generating additional spike voltage signals that activate the transducer and generate interference signals. This is a significant flaw in existing technology and limits the performance of ultrasound imaging systems. Summary of the Invention

[0005] In view of the defects in the prior art, the object of the present invention is to provide a dynamic current absorption circuit for an ultrasonic transmitting and receiving chip.

[0006] According to the present invention, a dynamic current absorption circuit for an ultrasonic transmitting and receiving chip includes: a transmitting circuit, a diode D1, a diode D2, a receiving drive circuit, a high-voltage NMOS transistor NH1, a low-voltage NMOS transistor NL1, a low-voltage NMOS transistor NL2, a transducer Z, and a dynamic current absorption circuit;

[0007] The output of the transmitting circuit is connected to the anode of the diode D1 and the cathode of D2; the cathode of the diode D1, the anode of the diode D2, the drain of the high-voltage NMOS transistor NH1, the output of the dynamic current absorption circuit, and the transducer Z are connected to the HVOUT terminal; one output terminal of the receiving drive circuit is connected to the gate of the high-voltage NMOS transistor NH1; one output terminal of the receiving drive circuit is connected to the gate of the low-voltage NMOS transistor NL1; one output terminal of the receiving drive circuit is connected to the gate of the low-voltage NMOS transistor NL2; the source of the high-voltage NMOS transistor NH1, the drain of the low-voltage NMOS transistor NL2, and the drain of the low-voltage NMOS transistor NL1 are short-circuited; the source of the low-voltage NMOS transistor NL1 is connected to LVOUT; and the source of the low-voltage NMOS transistor NL2 is grounded;

[0008] During the switching process between the transmitting state and the receiving state, the dynamic current absorption circuit generates a narrow pulse signal through the logic control circuit to control the switch tube to form a low-resistance path to absorb the dynamic current, and returns to the high-resistance state after the switching is completed.

[0009] Preferably, the dynamic current absorption circuit includes a logic control circuit, at least two diodes, at least two resistors and at least three switching tubes, wherein the input end of the logic control circuit is connected to the receiving circuit enable signal, and the output end is respectively connected to the gate of each switching tube to control its on and off.

[0010] Preferably, the switching tubes include a high-voltage NMOS tube, a high-voltage PMOS tube and a low-voltage NMOS tube. When the enable signal changes, the logic control circuit generates a narrow pulse signal with a pulse width of 200ns-500ns, so that the three switching tubes are turned on at the same time to form a low-resistance path.

[0011] Preferably, the resistors are matched resistors of the same type and resistance value, the diodes are matched diodes of the same type and area parameters, the absolute values ​​of the voltages of the positive power supply and the negative power supply are equal, and the bias point is stable at zero potential.

[0012] Preferably, the selection of the resistance value of the resistor needs to take into account the dynamic power consumption of the chip.

[0013] Preferably, the low-voltage NMOS transistor reduces the equivalent impedance of the entire current absorption loop when turned on, and maintains a strong dynamic current absorption capability when the static bias current is small.

[0014] Preferably, the dynamic current absorption circuit includes a logic control circuit, a diode D3, a diode D4, a diode D5, a diode D6, a resistor R1, a resistor R2, a high-voltage NMOS transistor NH2, a high-voltage PMOS transistor PH1, and a low-voltage NMOS transistor NL3;

[0015] The input terminal SW of the logic control circuit is a receiving circuit enable signal; one output terminal of the logic control circuit is connected to the gate of the high-voltage NMOS transistor NH2, one output terminal of the logic control circuit is connected to the gate of the low-voltage NMOS transistor NL3, and one output terminal of the logic control circuit is connected to the gate of the high-voltage PMOS transistor PH1; the source of the high-voltage NMOS transistor NH2 is connected to the negative power supply VEE; the drain of the high-voltage NMOS transistor NH2 is connected to one end of the resistor R1; the cathode of the diode D3, the cathode of the diode D5, and the other end of the resistor R1 are short-circuited; the anode of the diode D3 and the cathode of the diode D4 are short-circuited and connected to the output terminal HVOUT; the anode of the diode D4 and the anode of the diode D6 are connected to one end of the resistor R2; the anode of the diode D5 and the cathode of the diode D6 are connected to the drain of the low-voltage NMOS transistor NL3; the source of the low-voltage NMOS transistor NL3 is connected to ground; the drain of the high-voltage PMOS transistor PH1 is connected to the resistor R2; and the source of the high-voltage PMOS transistor PH1 is connected to the positive power supply VCC.

[0016] Preferably, the logic control circuit includes a Schmitt trigger for performing shaping and anti-interference processing on the receiving circuit enable signal to generate a narrow pulse signal.

[0017] Preferably, the diode is a diode with a voltage drop of about 0.7V, and the switch tube is a high-voltage MOS tube.

[0018] Preferably, when the circuit is in a transmitting state, a high voltage is generated by the transmitting circuit, and a high-frequency voltage signal is conducted to the transducer at the HVOUT end through the diode D1 and the diode D2. At this time, the receiving drive circuit turns off the switching tubes high-voltage NMOS tube NH1 and low-voltage NMOS tube NL1, and turns on the switching tube low-voltage NMOS tube NL2, connecting the source of the high-voltage NMOS tube NH1 and the drain of the low-voltage NMOS tube NL1 to the ground potential;

[0019] When the circuit is in the receiving state, the transmitting circuit is grounded. At the same time, the receiving drive circuit turns on the high-voltage NMOS transistor NH1 and the low-voltage NMOS transistor NL1, and turns off the low-voltage NMOS transistor NL2. The signal is transmitted from the HVOUT terminal to the LVOUT terminal. Since the output voltage of the HVOUT terminal is only in the mV level in the receiving state, the diodes D1 and D2 are isolated from the transmitting circuit.

[0020] Compared with the prior art, the present invention has the following beneficial effects:

[0021] 1. The present invention adds a dynamic current absorption circuit to form a low-resistance path at the switching moment, actively absorbing the dynamic current and preventing it from being transmitted to the transducer, effectively suppressing interference signals and improving imaging quality. Experiments show that under equivalent transducer load, the output peak voltage can be reduced by more than 60%, significantly reducing the generation of interference signals.

[0022] 2. The dynamic current absorption circuit of the present invention accurately controls the conduction and shutdown of the switch tube through the logic control circuit, ensuring that the system always operates stably during the switching process between the transmitting and receiving states; thus, it avoids damage to the transducer or chip caused by dynamic current shock, reduces the equipment failure rate, and extends the service life;

[0023] 3. The dynamic current absorption circuit of the present invention intervenes only during the switching process and automatically returns to a high-impedance state after the switching is completed, without affecting the high-voltage signal output of the transmitting circuit and the weak signal processing of the receiving circuit; the circuit can be flexibly integrated into the existing chip architecture without major changes in the hardware design, has strong compatibility, and is easy to promote. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Other features, objects and advantages of the present invention will become more apparent upon reading the detailed description of non-limiting embodiments with reference to the following drawings:

[0025] Figure 1 This is a schematic diagram of a traditional transmitting and receiving chip;

[0026] Figure 2 It is a technical schematic diagram of the present invention;

[0027] Figure 3 This is a schematic diagram of a dynamic current absorption circuit;

[0028] Figure 4 This is a schematic diagram of the control signal waveform of the dynamic current absorption circuit;

[0029] Figure 5 This is a schematic diagram of the output end of a traditional transmitting and receiving circuit;

[0030] Figure 6 This is a schematic diagram of a dynamic current absorption circuit. DETAILED DESCRIPTION

[0031] The present invention will be described in detail below with reference to specific embodiments. The following examples will help those skilled in the art to further understand the present invention, but are not intended to limit the present invention in any form. It should be noted that, for those skilled in the art, several changes and improvements can be made without departing from the scope of the present invention. These all fall within the scope of protection of the present invention.

[0032] Example 1:

[0033] Reference Figure 2 and Figure 3 According to the present invention, a dynamic current absorption circuit for an ultrasonic transmitting and receiving chip includes: a transmitting circuit, a diode D1, a diode D2, a receiving drive circuit, a high-voltage NMOS transistor NH1, a low-voltage NMOS transistor NL1, a low-voltage NMOS transistor NL2, a transducer Z, and a dynamic current absorption circuit; the output of the transmitting circuit is connected to the anode of the diode D1 and the cathode of D2; the cathode of the diode D1, the anode of the diode D2, the drain of the high-voltage NMOS transistor NH1, the output of the dynamic current absorption circuit, and the transducer Z are connected to the HVOUT terminal; one output terminal of the receiving drive circuit is connected to the gate of the high-voltage NMOS transistor NH1 One output end of the receiving drive circuit is connected to the gate of the low-voltage NMOS transistor NL1; one output end of the receiving drive circuit is connected to the gate of the low-voltage NMOS transistor NL2; the source of the high-voltage NMOS transistor NH1, the drain of the low-voltage NMOS transistor NL2, and the drain of the low-voltage NMOS transistor NL1 are short-circuited; the source of the low-voltage NMOS transistor NL1 is connected to LVOUT; the source of the low-voltage NMOS transistor NL2 is grounded; during the switching process between the transmitting state and the receiving state, the dynamic current absorption circuit generates a narrow pulse signal through the logic control circuit to control the switch tube to form a low-resistance path to absorb the dynamic current, and returns to the high-resistance state after the switching is completed.

[0034] The dynamic current absorption circuit includes a logic control circuit, at least two diodes, at least two resistors, and at least three switching transistors. The logic control circuit's input is connected to a receiving circuit enable signal, and its output is connected to the gates of each switching transistor to control its on / off state. The switching transistors include a high-voltage NMOS transistor, a high-voltage PMOS transistor, and a low-voltage NMOS transistor. When the enable signal changes, the logic control circuit generates a narrow pulse signal with a pulse width of 200ns-500ns, causing the three switching transistors to conduct simultaneously to form a low-resistance path. The resistors are matched resistors of the same type and value, and the diodes are matched diodes of the same type and area parameters. The absolute values ​​of the positive and negative power supply voltages are equal, and the bias point is stabilized at zero potential. The resistor values ​​should be selected based on the chip's dynamic power consumption. When the low-voltage NMOS transistor is on, it reduces the equivalent impedance of the entire current absorption loop, maintaining dynamic current absorption capability under static bias current conditions.

[0035] The dynamic current absorption circuit includes a logic control circuit, a diode D3, a diode D4, a diode D5, a diode D6, a resistor R1, a resistor R2, a high-voltage NMOS transistor NH2, a high-voltage PMOS transistor PH1, and a low-voltage NMOS transistor NL3; an input end SW of the logic control circuit is a receiving circuit enable signal; an output end of the logic control circuit is connected to the gate of the high-voltage NMOS transistor NH2, an output end of the logic control circuit is connected to the gate of the low-voltage NMOS transistor NL3, and an output end of the logic control circuit is connected to the gate of the high-voltage PMOS transistor PH1; the source of the high-voltage NMOS transistor NH2 is connected to the negative power supply VEE; the high The drain of the low-voltage NMOS transistor NH2 is connected to one end of the resistor R1; the cathode of the diode D3, the cathode of the diode D5, and the other end of the resistor R1 are short-circuited; the anode of the diode D3 and the cathode of the diode D4 are short-circuited and connected to the output HVOUT end; the anode of the diode D4 and the anode of the diode D6 are connected to one end of the resistor R2; the anode of the diode D5 and the cathode of the diode D6 are connected to the drain of the low-voltage NMOS transistor NL3; the source of the low-voltage NMOS transistor NL3 is connected to ground; the drain of the high-voltage PMOS transistor PH1 is connected to the resistor R2; and the source of the high-voltage PMOS transistor PH1 is connected to the positive power supply VCC.

[0036] The logic control circuit includes a Schmitt trigger for shaping and anti-interference processing of the receiving circuit enable signal to generate a narrow pulse signal. The diode uses a diode with a voltage drop of 0.7V, and the switch tube uses a high-voltage MOS tube.

[0037] When the circuit is in the transmitting state, the transmitting circuit generates high voltage, and the high-frequency voltage signal is transmitted to the transducer at the HVOUT terminal through diodes D1 and D2. At this time, the receiving drive circuit turns off the high-voltage NMOS transistor NH1 and the low-voltage NMOS transistor NL1, and turns on the low-voltage NMOS transistor NL2, connecting the source of the high-voltage NMOS transistor NH1 and the drain of the low-voltage NMOS transistor NL1 to the ground potential. When the circuit is in the receiving state, the transmitting circuit is grounded, and the receiving drive circuit turns on the high-voltage NMOS transistor NH1 and the low-voltage NMOS transistor NL1, and turns off the low-voltage NMOS transistor NL2. The signal is transmitted from the HVOUT terminal to the LVOUT terminal. Since the output voltage of the HVOUT terminal is only in the millivolt level in the receiving state, diodes D1 and D2 are isolated from the transmitting circuit.

[0038] Example 2:

[0039] When an ultrasound system switches from transmitting to receiving, dynamic currents generated during the process of driving the switch on and off can easily activate the transducer and generate interference signals, affecting imaging quality. This invention adds a dynamic current absorption circuit to the transducer end. During the switching process, it creates a low-resistance path to absorb the dynamic current; after the switching is complete, it becomes a high-resistance path, which does not affect signal transmission or reception.

[0040] The transmitting and receiving chip 10 ( Figure 2 ) includes a transmitting circuit (11), diodes D1, D2 (12), a receiving drive circuit (13), a high-voltage NMOS transistor HN1, a low-voltage NMOS transistor NL1, a low-voltage NMOS transistor NL2 (14), a transducer Z (15), and a dynamic current absorption circuit (16). The output of the transmitting circuit is connected to the anode of the diode D1 and the cathode of D2; the cathode of the diode D1, the anode of the diode D2, the drain of the high-voltage NMOS transistor NH1, the output of the dynamic current absorption circuit, and the transducer Z are connected to the HVOUT terminal; one output terminal of the receiving drive circuit is connected to the gate of the high-voltage NMOS transistor NH1; one output terminal of the receiving drive circuit is connected to the gate of the low-voltage NMOS transistor NL1; one output terminal of the receiving drive circuit is connected to the gate of the low-voltage NMOS transistor NL2; the source of the high-voltage NMOS transistor NH1, the drain of the low-voltage NMOS transistor NL2, and the drain of the low-voltage NMOS transistor NL1 are short-circuited; the source of the low-voltage NMOS transistor NL1 is connected to LVOUT; and the source of the low-voltage NMOS transistor NL2 is grounded.

[0041] The dynamic current absorption circuit 16 ( Figure 3) includes a logic control circuit, diodes D3, D4, D5, D6, resistors R1, R2, a high-voltage NMOS transistor NH2, a high-voltage PMOS transistor PH1, and a low-voltage NMOS transistor NL3. The input terminal SW of the logic control circuit is a receiving circuit enable signal; one output terminal of the logic control circuit is connected to the gate of the high-voltage NMOS transistor NH2, one output terminal of the logic control circuit is connected to the gate of the low-voltage NMOS transistor NL3, and one output terminal of the logic control circuit is connected to the gate of the high-voltage PMOS transistor PH1; the source of the high-voltage NMOS transistor NH2 is connected to the negative power supply VEE; the drain of the high-voltage NMOS transistor NH2 is connected to one end of the resistor R1; the cathode of the diode D3, the cathode of the diode D5, and the other end of the resistor R1 are short-circuited; the anode of the diode D3 and the cathode of the diode D4 are short-circuited and connected to the output terminal HVOUT; the anode of the diode D4 and the anode of the diode D6 are connected to one end of the resistor R2; the anode of the diode D5 and the cathode of the diode D6 are connected to the drain of the low-voltage NMOS transistor NL3; the source of the low-voltage NMOS transistor NL3 is connected to ground; the drain of the high-voltage PMOS transistor PH1 is connected to the resistor R2; and the source of the high-voltage PMOS transistor PH1 is connected to the positive power supply VCC.

[0042] The operating principle of the transmitter-receiver chip is as follows: When the chip is in the transmitting state, the transmitting circuit generates a high-voltage, high-frequency voltage signal that is conducted through diodes D1 and D2 to the transducer at the HVOUT terminal. At this time, the receiving driver circuit turns off the high-voltage NMOS transistor NH1 and the low-voltage NMOS transistor NL1, and turns on the low-voltage NMOS transistor NL2. The source of the high-voltage NMOS transistor NH1 and the drain of the low-voltage NMOS transistor NL1 are connected to ground. This structure improves the isolation between the HVOUT terminal and the LVOUT terminal, minimizing the impact of the transmitting state on the receiving terminal. When the chip is in the receiving state, the transmitting circuit is grounded, and the receiving driver circuit turns on the high-voltage NMOS transistor NH1 and the low-voltage NMOS transistor NL1, while turning off the low-voltage NMOS transistor NL2. The signal is transmitted from the HVOUT terminal to the LVOUT terminal. Since the output voltage at the HVOUT terminal is only in the millivolt range in the receiving state, diodes D1 and D2 isolate it from the transmitting circuit and do not affect the output voltage.

[0043] The dynamic current absorption circuit is the core of the present invention. Its main function is to absorb dynamic current during the chip's switching between transmit and receive states, thereby reducing the impact on the transducer. Its working principle is as follows: the SW signal is a state enable signal. When SW is high, the chip is in the transmit state, and when SW is low, the chip is in the receive state. When the SW state changes, the logic control circuit causes the high-voltage NMOS transistor NH2_G, the high-voltage PMOS transistor PH1_G, and the low-voltage NMOS transistor NL3_G to generate a narrow pulse signal (such as Figure 4As shown in the figure, the narrow pulse signal turns on the switch tubes high-voltage NMOS tube NH2, high-voltage PMOS tube PH1, and low-voltage NMOS tube NL3, forming a low-resistance path to absorb most of the dynamic current. The duration of the narrow pulse is generally between 200ns and 500ns.

[0044] The positive power supply VCC and the negative power supply VEE must have the same absolute value, resistors R1 and R2 must be of the same type and value, and the diodes must be of the same type and area. This ensures that the HVOUT terminal is biased at ground potential to prevent additional offset voltage generated by the dynamic current sink circuit itself. The resistance values ​​of resistors R1 and R2 must be chosen to balance current sinking capability and dynamic power consumption. Smaller values ​​will generate a larger bias current when the switch is turned on, increasing chip power consumption. Larger values ​​will reduce power consumption but weaken the current sinking capability. The function of the low-voltage NMOS transistor NL3 is to reduce the equivalent impedance of the entire circuit without changing the bias current, thereby improving current sinking capability.

[0045] The following example illustrates its function. To simplify the analysis, we use a 200 ohm resistor and a 50pF capacitor as the equivalent transducer. Assuming there is no dynamic current absorption circuit and there is a 1mA peak dynamic current during chip switching, the peak voltage at the HVOUT terminal is 200mV (e.g. Figure 5 shown).

[0046] Assume a dynamic current sink circuit such as Figure 6 As shown, select VCC = 5V; VEE = -5V; resistors R1 = R2 = 1K, and the voltage drop of diodes D3 and D4 is 0.7V; ignore the on-resistance of the high-voltage NMOS transistor NH2 and the high-voltage PMOS transistor PH1, and calculate the bias current of the circuit I = [(VCC + VEE) - 1.4] / (R1 + R2) = 4.3mA; the voltage at the HVOUT terminal can be calculated as follows:

[0047] (HVOUT-0.7-VEE) / R1+HVOUT / 200=1mA+(VCC-0.7V-HVOUT) / R2;

[0048] HVOUT≈143mV.

[0049] This structure has little effect in reducing the peak voltage at the HVOUT terminal when biased at 4.3mA.

[0050] This patented dynamic current sink circuit can reduce the peak voltage at HVOUT to less than 10mV without changing the bias current. The specific characteristics depend on the device characteristics provided by the FAB, including the diode area and the on-resistance of the low-voltage NMOS transistor NL3. This parameter can be adjusted based on customer needs and chip cost.

[0051] Dynamic current absorption technology is used in the transmitter and receiver chips to effectively reduce the peak voltage at the output, preventing abnormal activation of the transducer that could affect imaging quality. The dynamic current absorption circuit employed in this patent can improve dynamic current absorption capabilities at lower bias currents without affecting the chip's normal transmit and receive functions.

[0052] Transducer: A device that converts electrical signals into ultrasonic signals using the piezoelectric effect;

[0053] MOS tube: Metal oxide semiconductor field effect tube, which uses gate voltage to control channel current;

[0054] Diode: A two-terminal device with forward conduction and reverse blocking characteristics.

[0055] Those skilled in the art may understand this embodiment as a more specific description of Embodiment 1.

[0056] Those skilled in the art will appreciate that, in addition to implementing the system and its various devices, modules, and units provided by the present invention in purely computer-readable program code, it is entirely possible to implement the same functions of the system and its various devices, modules, and units provided by the present invention in the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers, and embedded microcontrollers by logically programming the method steps. Therefore, the system and its various devices, modules, and units provided by the present invention can be considered a hardware component, and the devices, modules, and units included therein for implementing various functions can also be considered as structures within the hardware component; the devices, modules, and units for implementing various functions can also be considered as both software modules implementing the method and structures within the hardware component.

[0057] The above describes specific embodiments of the present invention. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art may make various changes or modifications within the scope of the claims, which do not affect the essence of the present invention. The embodiments of this application and the features in the embodiments may be combined with each other in any manner unless there is a conflict.

Claims

1. A dynamic current absorption circuit for an ultrasonic transmitter and receiver chip, characterized in that: include: Transmitting circuit, diode D1, diode D2, receiving drive circuit, high-voltage NMOS transistor NH1, low-voltage NMOS transistor NL1, low-voltage NMOS transistor NL2, transducer Z, dynamic current absorption circuit; The output of the transmitting circuit is connected to the anode of the diode D1 and the cathode of D2; the cathode of the diode D1, the anode of the diode D2, the drain of the high-voltage NMOS transistor NH1, the output of the dynamic current absorption circuit, and the transducer Z are connected to the HVOUT terminal; one output terminal of the receiving drive circuit is connected to the gate of the high-voltage NMOS transistor NH1; one output terminal of the receiving drive circuit is connected to the gate of the low-voltage NMOS transistor NL1; one output terminal of the receiving drive circuit is connected to the gate of the low-voltage NMOS transistor NL2; the source of the high-voltage NMOS transistor NH1, the drain of the low-voltage NMOS transistor NL2, and the drain of the low-voltage NMOS transistor NL1 are short-circuited; the source of the low-voltage NMOS transistor NL1 is connected to LVOUT; and the source of the low-voltage NMOS transistor NL2 is grounded; During the switching process between the transmitting state and the receiving state, the dynamic current absorption circuit generates a narrow pulse signal through the logic control circuit to control the switch tube to form a low-resistance path to absorb the dynamic current, and returns to the high-resistance state after the switching is completed.

2. The dynamic current absorption circuit for an ultrasonic transmitting and receiving chip according to claim 1, characterized in that: The dynamic current absorption circuit includes a logic control circuit, at least two diodes, at least two resistors and at least three switching tubes, wherein the input end of the logic control circuit is connected to the receiving circuit enable signal, and the output end is respectively connected to the gate of each switching tube to control its on and off.

3. The dynamic current absorption circuit for an ultrasonic transmitting and receiving chip according to claim 2, characterized in that: The switch tubes include a high-voltage NMOS tube, a high-voltage PMOS tube and a low-voltage NMOS tube. When the enable signal changes, the logic control circuit generates a narrow pulse signal with a pulse width of 200ns-500ns, so that the three switch tubes are turned on at the same time to form a low-resistance path.

4. The dynamic current absorption circuit for an ultrasonic transmitting and receiving chip according to claim 2, characterized in that: The resistors are matching resistors of the same type and resistance value, the diodes are matching diodes of the same type and area parameters, the absolute values ​​of the voltages of the positive power supply and the negative power supply are equal, and the bias point is stable at zero potential.

5. The dynamic current absorption circuit for an ultrasonic transmitting and receiving chip according to claim 4, characterized in that: The selection of the resistance value of the resistor needs to take into account the dynamic power consumption of the chip.

6. The dynamic current absorption circuit for an ultrasonic transmitting and receiving chip according to claim 3, characterized in that: The low-voltage NMOS tube reduces the equivalent impedance of the entire current absorption loop when it is turned on, and maintains the dynamic current absorption capability under the condition of static bias current.

7. The dynamic current absorption circuit for an ultrasonic transmitting and receiving chip according to claim 1, characterized in that: The dynamic current absorption circuit includes a logic control circuit, a diode D3, a diode D4, a diode D5, a diode D6, a resistor R1, a resistor R2, a high-voltage NMOS transistor NH2, a high-voltage PMOS transistor PH1, and a low-voltage NMOS transistor NL3; The input terminal SW of the logic control circuit is a receiving circuit enable signal; one output terminal of the logic control circuit is connected to the gate of the high-voltage NMOS transistor NH2, one output terminal of the logic control circuit is connected to the gate of the low-voltage NMOS transistor NL3, and one output terminal of the logic control circuit is connected to the gate of the high-voltage PMOS transistor PH1; the source of the high-voltage NMOS transistor NH2 is connected to the negative power supply VEE; the drain of the high-voltage NMOS transistor NH2 is connected to one end of the resistor R1; the cathode of the diode D3, the cathode of the diode D5, and the other end of the resistor R1 are short-circuited; the anode of the diode D3 and the cathode of the diode D4 are short-circuited and connected to the output terminal HVOUT; the anode of the diode D4 and the anode of the diode D6 are connected to one end of the resistor R2; the anode of the diode D5 and the cathode of the diode D6 are connected to the drain of the low-voltage NMOS transistor NL3; the source of the low-voltage NMOS transistor NL3 is connected to ground; the drain of the high-voltage PMOS transistor PH1 is connected to the resistor R2; and the source of the high-voltage PMOS transistor PH1 is connected to the positive power supply VCC.

8. The dynamic current absorption circuit for an ultrasonic transmitting and receiving chip according to claim 7, characterized in that: The logic control circuit includes a Schmitt trigger, which is used to perform shaping and anti-interference processing on the receiving circuit enable signal to generate a narrow pulse signal.

9. The dynamic current absorption circuit for an ultrasonic transmitting and receiving chip according to claim 1, characterized in that: The diode is a Schottky diode, and the switch tube is a high-voltage MOS tube.

10. The dynamic current absorption circuit for an ultrasonic transmitting and receiving chip according to claim 1, characterized in that: When the circuit is in the transmitting state, the transmitting circuit generates high voltage, and the high-frequency voltage signal is transmitted to the transducer at the HVOUT end through diodes D1 and D2. At this time, the receiving drive circuit turns off the high-voltage NMOS transistor NH1 and the low-voltage NMOS transistor NL1, and turns on the low-voltage NMOS transistor NL2, connecting the source of the high-voltage NMOS transistor NH1 and the drain of the low-voltage NMOS transistor NL1 to the ground potential. When the circuit is in the receiving state, the transmitting circuit is grounded. At the same time, the receiving drive circuit turns on the high-voltage NMOS transistor NH1 and the low-voltage NMOS transistor NL1, and turns off the low-voltage NMOS transistor NL2. The signal is transmitted from the HVOUT terminal to the LVOUT terminal. Since the output voltage of the HVOUT terminal is only in the mV level in the receiving state, the diodes D1 and D2 are isolated from the transmitting circuit.

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