Processing method for MEMS device and wafer level packaging method

Abstract

The invention provides a processing method for an MEMS (Micro Electro Mechanical System) device and a wafer level packaging method. The method comprises the following steps: step 1, bonding a borosilicate glass sheet on a silicon substrate; 2, the glass layer obtained in the step 1 is thinned, so that the thickness of the glass layer meets the design requirement, and the thickness range is 3-20 microns; step 3, carrying out boss processing on the glass layer, and manufacturing anchor points; 4, metalizing the surface of the glass layer to manufacture a required lead; step 5, bonding another silicon wafer on the surface of the glass layer, and controlling the thickness of the silicon wafer to the required thickness of the sensitive structure layer in a thinning manner to form a silicon sensitive structure layer; and step 6, processing the silicon sensitive structure layer, and manufacturing a mass block, a beam and a comb tooth structure. According to the scheme, the parasitic capacitance between the lead and the silicon substrate layer can be greatly reduced, the process compatibility is good, and only the silicon substrate layer processing process of the all-silicon process needs to be adjusted.

Description

Technical Field

[0001] The present invention relates to the field of inertial measurement technology, and in particular to a processing method for MEMS devices and a wafer-level packaging method. Background Art

[0002] Inertial MEMS devices are manufactured using MEMS methods and are capable of measuring inertial physical quantities such as the angular velocity and acceleration of an object. They offer advantages such as small size, low cost, and low power consumption, and are widely used in defense, inertial navigation, industrial control, and other fields. Inertial MEMS devices primarily include MEMS gyroscopes and MEMS accelerometers.

[0003] The core of inertial MEMS devices is typically a silicon sensitive structure, fabricated using processes such as photolithography and etching. Typical fabrication methods include SOG (silicon-on-glass) and all-silicon processes. The all-silicon process, with its primary structure made entirely of silicon, offers excellent thermal compatibility, reducing process stress and ultimately achieving higher device performance.

[0004] However, this solution has an obvious problem. The structure needs to prepare leads to lead out the structural electrical signals. Since it is an all-silicon solution, the leads must be prepared on the silicon substrate and separated by an insulating layer in the middle. The insulating layer is usually made of silicon oxide material, and the structural thickness generally does not exceed 2um. Parasitic capacitance will inevitably form between the leads and the silicon substrate. Due to the small capacitor gap and the large dielectric constant of the silicon oxide material, the parasitic capacitance is very large (typical value 100pF), which is usually far greater than the sensitive working capacitance (typical value 10pF), which may reduce the sensitive accuracy and thus reduce the device performance. Summary of the Invention

[0005] The present invention aims to solve at least one of the technical problems existing in the prior art or related art.

[0006] To this end, the present invention provides a method for processing MEMS devices and a wafer-level packaging method. This method uses borosilicate glass as the insulating layer material in a typical all-silicon process. Compared to insulating layer materials such as silicon oxide and silicon nitride, this method can achieve a thicker insulating layer, thereby reducing parasitic capacitance. Because its thermal expansion coefficient is closer to that of silicon, it does not significantly increase stress, thereby improving device precision.

[0007] The technical solutions of the present invention are as follows:

[0008] According to one aspect, a method for manufacturing a MEMS device is provided, the method comprising:

[0009] Step 1: bonding a borosilicate glass sheet onto a silicon substrate;

[0010] Step 2: Thinning the glass layer obtained in step 1 to make the glass layer thickness meet the design requirements, with a thickness range of 3-20 μm;

[0011] Step 3: Process the glass layer into bosses to create anchor points;

[0012] Step 4: Metallize the surface of the glass layer to make the required leads;

[0013] Step 5: Bond another silicon wafer to the surface of the glass layer, and then thin the silicon wafer to the required thickness of the sensitive structure layer to form a silicon sensitive structure layer;

[0014] Step 6: Process the silicon sensitive structural layer to produce a mass block, beam and comb structure.

[0015] Furthermore, in step one, an anodic bonding process or a direct bonding process is used to bond a borosilicate glass sheet onto a silicon substrate.

[0016] Furthermore, in step 2, the surface roughness of the glass is reduced by a polishing process after thinning.

[0017] Furthermore, the processing technology used in step 3 is wet etching or dry etching, the mask is photoresist or metal, and / or, the bonding process in step 5 includes eutectic bonding process, anodic bonding or thermal compression bonding; and / or, in step 6, dry etching technology is used to process the silicon sensitive structural layer.

[0018] Furthermore, the lead in step 4 includes a single layer of lead or multiple layers of lead, wherein, in the case of multiple layers of lead, the multiple layers of lead are realized by alternate deposition or plating.

[0019] Furthermore, the silicon wafer in step 5 can be replaced by an SOI wafer, and the sensitive structure layer of the required thickness can be obtained by removing the substrate layer and the insulating layer of the SOI wafer.

[0020] According to another aspect, a method for wafer-level packaging of a MEMS device is provided, the method comprising:

[0021] Step 1: bonding a borosilicate glass sheet onto a silicon substrate;

[0022] Step 2: Thinning the glass layer obtained in step 1 to make the glass layer thickness meet the design requirements, with a thickness range of 3-20 μm;

[0023] Step 3: Process the glass layer into bosses to create anchor points;

[0024] Step 4: Metallize the surface of the glass layer to make the required leads to obtain structure 1;

[0025] Step 5: depositing a mask on another silicon wafer;

[0026] Step 6: Patterning the mask;

[0027] Step 7: Processing the silicon boss based on the patterned mask to realize silicon capping layer processing;

[0028] Step 8: Bonding a silicon wafer to the surface of the structure obtained in step 7, and then thinning the silicon wafer to the desired thickness of the sensitive structure layer to form a silicon sensitive structure layer;

[0029] Step 9: Process the silicon sensitive structural layer to produce a mass block, a beam, and a comb structure to obtain structure 2;

[0030] Step 10: Bonding structure 1 and structure 2 together, wherein the silicon sensitive structure layer of structure 2 is bonded to the surface of the glass layer processed with leads of structure 1.

[0031] Furthermore, the method further includes machining pads on the surface of the structure obtained in step 4, and after completing step 10, removing part of the silicon capping layer structure to expose the pads in structure 1.

[0032] Furthermore, the lead in step 4 includes at least two layers of leads, one of which is used as a sealing ring, and the multi-layer lead is achieved by alternate deposition or plating.

[0033] Furthermore, in the method, between step 7 and step 8, the mask may be removed first, and then a layer of silicon oxide may be grown on the surface of the structure through a thermal oxidation process.

[0034] The above technical solution uses borosilicate glass as the insulating layer material in a typical all-silicon process solution. Based on this, a processing method for the borosilicate glass insulating layer is designed. This greatly reduces the parasitic capacitance between the leads and the silicon substrate layer (the thickness of which can far exceed 2 microns). At the same time, because the thermal expansion coefficient of borosilicate glass is close to that of silicon, it does not cause significant stress increase. The process of this invention has good compatibility and only requires adjustments to the silicon substrate processing technology of the all-silicon process. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The accompanying drawings are included to provide a further understanding of the embodiments of the present invention, constitute a part of the specification, illustrate the embodiments of the present invention, and together with the description, explain the principles of the present invention. Obviously, the drawings described below are only some embodiments of the present invention, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0036] Figure 1 This is a cross-sectional diagram of a typical all-silicon process solution.

[0037] 1 is a silicon sensitive structural layer; 11 is a structural pattern; 2 is a silicon substrate layer; 21 is a boss; 22 is an insulating layer; and 23 is a lead.

[0038] Figure 2 It is a schematic cross-sectional view of the process scheme of the present invention.

[0039] 1 is a silicon sensitive structural layer; 11 is a structural pattern; 2 is a silicon substrate layer; 21 is a boss; 23 is a lead; and 24 is a borosilicate glass layer.

[0040] Figure 3 It is a process flow chart proposed by the present invention.

[0041] 1 is a silicon sensitive structural layer; 11 is a structural pattern; 2 is a silicon substrate layer; 21 is a boss; 23 is a lead; and 24 is a borosilicate glass layer.

[0042] Figure 4 It is a cross-sectional schematic diagram of another process scheme proposed by the present invention.

[0043] 1 is a silicon sensitive structural layer; 11 is a structural pattern; 2 is a silicon substrate layer; 21 is a boss; 23 is a lead; 24 is a borosilicate glass layer; 3 is a silicon capping layer; 31 is a boss; and 32 is a mask.

[0044] Figure 5 It is another process flow chart proposed by the present invention. DETAILED DESCRIPTION

[0045] It should be noted that, in the absence of conflict, the embodiments in this application and the features in the embodiments can be combined with each other. The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. The following description of at least one exemplary embodiment is actually only illustrative and is in no way intended to limit the present invention and its application or use. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0046] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, they indicate the presence of features, steps, operations, devices, components and / or combinations thereof.

[0047] Unless otherwise specifically stated, the relative arrangement of the parts and steps, the numerical expressions and the numerical values ​​set forth in these embodiments do not limit the scope of the present invention. At the same time, it should be understood that, for ease of description, the sizes of the various parts shown in the drawings are not drawn according to the actual proportional relationship. The techniques, methods and equipment known to those of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, the techniques, methods and equipment should be considered as part of the authorization specification. In all examples shown and discussed here, any specific values ​​should be interpreted as being merely exemplary and not as limiting. Therefore, other examples of the exemplary embodiments may have different values. It should be noted that similar numbers and letters represent similar items in the following figures, and therefore, once an item is defined in one figure, it does not need to be further discussed in subsequent figures.

[0048] like Figure 1 As shown in the figure, a typical all-silicon process solution includes two silicon structures: a silicon sensitive structure layer and a silicon substrate layer. The silicon sensitive structure layer contains the mass, beams, electrodes, and other structures required for the operation of the MEMS device. The silicon substrate layer is mainly used to support the silicon sensitive structure. Leads are also fabricated on it to lead out the sensitive structure electrodes. The silicon substrate layer is machined with bosses as anchor points for the sensitive structure. Because leads need to be machined on the silicon substrate layer, an insulating layer must first be machined on the silicon substrate layer to ensure insulation between the leads and the silicon substrate. The material of this insulating layer is generally silicon oxide, prepared by a deposition process or oxidation process. Inevitably, parasitic capacitance is formed between the leads and the silicon substrate. Due to process conditions and process stress, the thickness of this insulating layer generally does not exceed 2 microns, resulting in a large parasitic capacitance, which has a significant impact on the MEMS device.

[0049] In the embodiment of the present invention, the insulating layer in a typical all-silicon process solution is replaced with a borosilicate glass material, and on this basis, a processing method for the insulating layer based on the borosilicate glass material is designed.

[0050] like Figure 2-3 In one embodiment of the present invention, a method for processing a MEMS device is provided, the method comprising:

[0051] Step 1: bonding a borosilicate glass layer 24 on a silicon substrate layer 2;

[0052] In this step, the bonding process is usually an anodic bonding process, but other bonding processes such as direct bonding process can also be used.

[0053] Step 2: Thinning the borosilicate glass layer 24 of the bonding wafer to ensure that the thickness of the borosilicate glass layer 24 meets the design requirements, with a thickness range of 3-20 μm;

[0054] In this step, preferably, the surface roughness of the borosilicate glass layer 24 can be reduced by a polishing process after thinning;

[0055] Step 3: Processing the boss 21 on the borosilicate glass layer 24 to make an anchor point;

[0056] In this step, the processing technology is generally wet etching or dry etching, and the mask can be photoresist, metal, etc.

[0057] Step 4: Metallize the surface of the borosilicate glass layer 24 to produce the required leads 23;

[0058] This step realizes the processing of silicon substrate layer 2;

[0059] Step 5: Bond another silicon wafer to the surface of the borosilicate glass layer 24 with leads, and then thin the silicon wafer to the desired thickness of the sensitive structure layer to form a silicon sensitive structure layer 1;

[0060] Step 6: Process the silicon sensitive structure layer 1 to make structures such as mass blocks, beams and comb teeth.

[0061] This step generally adopts dry etching technology, and the structural pattern 11 is shown in FIG. Figure 3 .

[0062] By adopting this solution, the thickness of the insulating layer can be much greater than 2 microns, greatly reducing parasitic capacitance. At the same time, because the thermal expansion coefficient of borosilicate glass is close to that of silicon, it will not cause a significant increase in stress.

[0063] In addition, the borosilicate glass sheet in the solution can be replaced by other glass materials with a thermal expansion coefficient close to that of silicon material.

[0064] Furthermore, the lead 23 in step 4 is not limited to a single layer of lead, and multiple layers of lead can be realized by alternate deposition or plating.

[0065] According to an embodiment of the present invention, the silicon wafer in step 5 can be replaced by an SOI wafer, and the sensitive structure layer 1 of the required thickness is obtained by removing the substrate layer and the insulating layer of the SOI wafer.

[0066] According to an embodiment of the present invention, the bonding process in step 5 is not limited to the eutectic bonding process, and anodic bonding or thermal compression bonding may also be used.

[0067] Therefore, the embodiment of the present invention uses borosilicate glass as the insulating layer material in a typical all-silicon process solution, and designs a processing method based on this borosilicate glass insulating layer, thereby greatly reducing the parasitic capacitance between the lead and the silicon substrate layer (its thickness can far exceed 2 microns). At the same time, because the thermal expansion coefficient of borosilicate glass is close to that of silicon, it will not cause a significant increase in stress. The embodiment of the present invention has good process compatibility and only needs to adjust the silicon substrate layer processing technology of the all-silicon process.

[0068] The technical solution adopted in the above embodiment can also be applied to the wafer level packaging solution, such as Figure 4 This solution comprises a three-layer structure: a silicon capping layer 3, a silicon sensitive structure layer 1, and a silicon substrate layer 2. Compared to the previous solution, the silicon capping layer 3 is added. Because the silicon sensitive structure layer 1 is placed between the other two layers, it provides better protection. This solution also enables wafer-level vacuum packaging or hermetic sealing, making it particularly suitable for MEMS devices such as microelectromechanical gyroscopes, microaccelerometers, and pressure sensors.

[0069] The corresponding process scheme is similar to the above scheme, such as Figure 5 , which includes the following steps:

[0070] Step 1: Bonding a borosilicate glass layer 24 onto a silicon substrate layer 2. The bonding process is typically an anodic bonding process, but other bonding processes such as direct bonding may also be used.

[0071] Step 2: Thinning the borosilicate glass layer 24 of the bonding wafer to achieve a thickness that meets the design requirements, with a thickness range of 3-20 μm. After thinning, the surface roughness of the borosilicate glass layer 24 can be reduced through a polishing process.

[0072] Step 3: Processing the boss 21 on the borosilicate glass layer 24 to produce an anchor point. The processing technology is generally wet etching or dry etching, and the mask can be photoresist or metal;

[0073] Step 4: Metallize the surface of the borosilicate glass layer 24 to produce the required leads 23. This step completes the processing of the silicon substrate layer 2.

[0074] So far, steps 1-4 are consistent with the previous embodiment, and structure 1 is obtained;

[0075] Step 5: Depositing a mask 32 on another silicon wafer, the material of which is generally silicon oxide;

[0076] Step 6: Patterning the mask 32;

[0077] Step 7: Processing the silicon boss 31 by wet etching or dry etching, etc. This step realizes the processing of the silicon capping layer 3.

[0078] Step 8: Bond the third silicon wafer to the side with the boss 31 processed in step 7 by direct bonding, and then thin the silicon wafer to the required thickness of the sensitive structure layer to form the silicon sensitive structure layer 1;

[0079] Step 9: Process the silicon sensitive structure layer 1 to make structures such as mass blocks, beams and comb teeth. Dry etching technology is generally used. The structure diagram is shown in Figure 5 ;

[0080] At this point, steps 5-9 result in structure 2;

[0081] Step 10: Bonding the silicon sensitive structure layer 1 of structure 2 to the borosilicate glass layer 24 with wires processed thereon of structure 1.

[0082] Step 11: Remove part of the silicon capping layer 3 to expose the pad in structure 1.

[0083] In the above embodiment, the lead 23 in step 4 of the solution is not limited to a single layer of lead, and multiple layers of lead can be achieved by alternate deposition or coating. In particular, for wafer-level vacuum packaging or hermetic packaging, at least two layers of lead are required, one of which is used as a sealing ring.

[0084] In the above embodiment, after step 7, the mask 32 can be removed first, and then a layer of silicon oxide can be grown on the surface of the structure by a process such as thermal oxidation. In this way, there is also silicon oxide at the bottom of the structure, which can protect the bottom of the structure from damage in step 9.

[0085] In the above embodiment, the third silicon wafer in step 8 can be replaced by an SOI wafer, and the sensitive structure layer 1 of the required thickness can be obtained by removing the substrate layer and the insulating layer of the SOI wafer.

[0086] According to an embodiment of the present invention, the bonding process in step 10 is not limited to the eutectic bonding process, and anodic bonding, thermal compression bonding, etc. may also be used.

[0087] In addition, the technical solution of the present invention is applicable to other process solutions using silicon as the substrate layer, and is therefore not limited to the above two process solutions.

[0088] Features described and / or illustrated above for one embodiment may be used in the same or similar manner in one or more other embodiments, and / or combined with or used in place of features in other embodiments.

[0089] It should be emphasized that the term "include / comprises" when used herein refers to the presence of features, integers, steps or components, but does not exclude the presence or addition of one or more other features, integers, steps, components or combinations thereof.

[0090] The above methods of the present invention can be implemented by hardware, or by a combination of hardware and software. The present invention relates to a computer-readable program that, when executed by a logic component, enables the logic component to implement the apparatus or components described above, or to implement the various methods or steps described above. The present invention also relates to a storage medium for storing the above program, such as a hard disk, magnetic disk, optical disk, DVD, flash memory, etc.

[0091] The many features and advantages of these embodiments are apparent from this detailed description, and thus, the appended claims are intended to cover all such features and advantages of these embodiments that fall within the true spirit and scope thereof. Furthermore, since numerous modifications and changes will readily occur to those skilled in the art, it is not intended that the embodiments of the invention be limited to the exact construction and operation illustrated and described, but rather that all suitable modifications and equivalents be covered within the scope thereof.

[0092] Parts of the present invention that are not described in detail are well known to those skilled in the art.

Claims

1. A method for processing a MEMS device, characterized in that: The processing method comprises: Step 1: bonding a borosilicate glass sheet onto a silicon substrate; Step 2: Thinning the glass layer obtained in step 1 to make the glass layer thickness meet the design requirements, with a thickness range of 3-20 μm; Step 3: Process the glass layer into bosses to create anchor points; Step 4: Metallize the surface of the glass layer to make the required leads; Step 5: Bond another silicon wafer to the surface of the glass layer, and then thin the silicon wafer to the required thickness of the sensitive structure layer to form a silicon sensitive structure layer; Step 6: Process the silicon sensitive structural layer to produce a mass block, beam and comb structure.

2. A processing method for MEMS devices according to claim 1, characterized in that: In step 1, a borosilicate glass sheet is bonded on a silicon substrate using an anodic bonding process or a direct bonding process.

3. A method for processing a MEMS device according to claim 1, characterized in that: In step 2, the surface roughness of the glass is reduced by a polishing process after thinning.

4. A method for processing a MEMS device according to any one of claims 1 to 3, characterized in that: The processing technology used in step 3 is wet etching or dry etching, the mask is photoresist or metal, and / or, the bonding process in step 5 includes eutectic bonding process, anodic bonding or thermal compression bonding; and / or, in step 6, dry etching technology is used to process the silicon sensitive structural layer.

5. A method for processing a MEMS device according to any one of claims 1 to 4, characterized in that: The lead in step 4 includes a single layer of lead or multiple layers of lead. In the case of multiple layers of lead, the multiple layers of lead are realized by alternate deposition or plating.

6. A method for processing a MEMS device according to claim 1, characterized in that: The silicon wafer in step 5 can be replaced by an SOI wafer, and the sensitive structure layer of the required thickness can be obtained by removing the substrate layer and the insulating layer of the SOI wafer.

7. A method for wafer-level packaging of MEMS devices, characterized in that: The method comprises: Step 1: bonding a borosilicate glass sheet onto a silicon substrate; Step 2: Thinning the glass layer obtained in step 1 to make the glass layer thickness meet the design requirements, with a thickness range of 3-20 μm; Step 3: Process the glass layer into bosses to create anchor points; Step 4: Metallize the surface of the glass layer to make the required leads to obtain structure 1; Step 5: depositing a mask on another silicon wafer; Step 6: Patterning the mask; Step 7: Processing the silicon boss based on the patterned mask to realize silicon capping layer processing; Step 8: Bonding a silicon wafer to the surface of the structure obtained in step 7, and then thinning the silicon wafer to the desired thickness of the sensitive structure layer to form a silicon sensitive structure layer; Step 9: Process the silicon sensitive structural layer to produce a mass block, a beam, and a comb structure to obtain structure 2; Step 10: Bonding structure 1 and structure 2 together, wherein the silicon sensitive structure layer of structure 2 is bonded to the surface of the glass layer processed with leads of structure 1.

8. The wafer-level packaging method for MEMS devices according to claim 7, characterized in that: The method further includes machining pads on the surface of the structure obtained in step 4, and after completing step 10, removing part of the silicon capping layer structure to expose the pads in structure 1.

9. The wafer-level packaging method for MEMS devices according to claim 7, wherein: The leads in step 4 include at least two layers of leads, one of which is used as a sealing ring, and the multi-layer leads are achieved by alternate deposition or plating.

10. The wafer-level packaging method for MEMS devices according to claim 7, characterized in that: In the method, between step 7 and step 8, the mask may be removed first, and then a layer of silicon oxide may be grown on the surface of the structure through a thermal oxidation process.

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