Multi-channel TDLAS data real-time processing system based on FPGA

Abstract

The invention discloses a multichannel TDLAS data real-time processing system based on an FPGA, and the system comprises the steps: generating a superposed signal needed by a laser through the FPGA, and outputting the superposed signal to a laser driver through a DAC; after the two lasers emit light, the two lasers are divided into N light paths through the optical fiber beam combiner and the optical fiber beam splitter; after the laser passes through an area to be detected, the photoelectric detector converts a light intensity signal of each light path into an electric signal, and then the electric signal is converted into a digital signal through the ADC and is input into the FPGA; after the FPGA receives the ADC sampling signal, extracting a first harmonic signal and a second harmonic signal of each light path through an internal multi-channel double-phase lock-in amplifier; and finally, the FPGA transmits the harmonic signal of each light path to an MATLAB of an upper computer for data processing and real-time display by using a UDP protocol, and temperature and concentration solution and real-time display can be directly carried out through the obtained harmonic signal and the extracted peak signal. The device can be used for measuring the combustion temperature, and has high precision and good linearity and stability.

Description

Technical Field

[0001] The present invention relates to the fields of combustion diagnosis and laser spectroscopy, and in particular to a multi-channel TDLAS data real-time processing system based on FPGA. Background Art

[0002] Currently, non-contact temperature measurement technology has been widely researched and applied. In particular, technology based on tunable diode laser absorption spectroscopy (TDLAS) utilizes the spectral absorption characteristics of laser light interacting with gas molecules to invert temperature information. This allows real-time, multi-point, and multi-parameter measurement of combustion flow fields without disturbing the flow field being measured. In 2015, Chighine et al. proposed an FPGA-based digital TDLAS system to measure CO2 absorption characteristics and extract WMS-1f and 2f. In 2018, Xu Lijun proposed a real-time temperature measurement system based on an FPGA and tunable diode laser absorption spectroscopy. The FPGA implements a real-time quadrature demodulator to extract 2f and 1f frequency signals and calculate the WMS-2f / 1f signal on-chip. Research on TDLAS processing systems has been conducted, but the complexity of these systems makes it difficult to meet the requirements for long-term real-time extraction and observation of WMS-2f / 1f signals, and also hinders long-term data storage. Summary of the Invention

[0003] The purpose of this application is to propose a multi-channel TDLAS data real-time processing system based on FPGA to address the above-mentioned technical problems. The system can process and store TDLAS data signals in real time for a long time, and the frequency division multiplexing method in the multi-channel dual-phase lock-in amplifier reduces the system complexity. The system can be used for combustion temperature measurement and has high precision, good linearity and stability, and can provide effective data support for real-time monitoring and optimization of the combustion process.

[0004] The technical solutions of the present invention are as follows:

[0005] A multi-channel TDLAS data real-time processing system based on FPGA includes: M laser drivers, M DFB lasers with different wavelengths, N collimating lenses, N photodetectors, an FPGA and a host computer installed with MATLAB; the FPGA includes N ADC modules, N multi-channel dual-phase lock-in amplifiers, N multi-channel peak extraction modules, M DAC modules, a UDP module and M superposition signal generators; each superposition signal generator generates a modulation signal matching the corresponding laser and outputs it to the corresponding laser driver through the DAC module, and the output of each laser driver is connected to the corresponding DFB laser to drive the DFB laser to emit laser light; after the DFB laser emits light, it is connected to the 1X optical fiber combiner through the M X1 optical fiber combiner. An N-fiber beam splitter divides M laser beams into N optical paths. After the laser passes through the test area, a photodetector converts the light intensity signal of the corresponding optical path into an electrical signal. This signal is then converted and output to a multi-channel dual-phase lock-in amplifier via the corresponding ADC module. Each multi-channel dual-phase lock-in amplifier extracts the first harmonic signal, second harmonic signal, second harmonic X component, and second harmonic Y component of the corresponding optical path. The multi-channel peak extraction module then extracts the peak signals of the second harmonic signal, second harmonic X component, and second harmonic Y component. The FPGA transmits the extracted harmonic and peak signals of each optical path to the host computer's MATLAB through the UDP module for data processing and real-time display. MATLAB also uses the harmonic and peak signals to calculate temperature and gas concentration and displays them in real time. M and N are both greater than or equal to 1.

[0006] Preferably, each multi-channel dual-phase lock-in amplifier includes M dual-phase lock-in amplifiers, which are used to respectively extract the first harmonic signal, the second harmonic signal, the second harmonic X component and the second harmonic Y component of the modulation signals of M different frequencies; each dual-phase lock-in amplifier includes a plurality of multipliers, a low-pass filter and a square root module; a pre-stored modulation signal is used as a first reference signal to perform sine operation and cosine operation respectively, and then the sine operation results and the cosine operation results are respectively calculated with the input signal through the multiplier, and the multiplication results of the two are respectively processed through the low-pass filter, and the signals filtered by the two low-pass filters are calculated through the multiplier and then square root processed through the square root module to obtain the first harmonic signal; A pre-stored modulated signal is multiplied by 2 and used as a second reference signal for performing sine and cosine operations respectively. The sine and cosine operation results are then respectively operated on with the input signal through a multiplier, and the multiplication results of the two are respectively processed through low-pass filters; the signals filtered by the two low-pass filters are operated through a multiplier and then subjected to square root processing through a square root module to obtain a second harmonic signal; the signal filtered by one of the low-pass filters is input into the multiplier for operation and then subjected to square root processing through the square root module to obtain a second harmonic X component; the signal filtered by the other low-pass filter is input into the multiplier for operation and then subjected to square root processing through the square root module to obtain a second harmonic Y component.

[0007] Preferably, the low-pass filter adopts an FIR filter, and the order can be configured through MATLAB.

[0008] Preferably, the superposition signal generator includes a sine wave signal generator for generating a high-frequency sine wave modulation signal, a sine wave signal generator for generating a low-frequency triangular wave scanning signal, and an adder; the frequency, assignment and bias of the sine wave signal generator and the sine wave signal generator can be configured through MATLAB to adapt to DFB lasers of different wavelengths; the adder superimposes the high-frequency sine wave modulation signal and the low-frequency triangular wave scanning signal to generate a composite modulation signal.

[0009] Preferably, the FPGA also includes a signal preprocessing module arranged between the ADC module and the multi-channel dual-phase lock-in amplifier. The photodetector converts the light intensity signal of the corresponding optical path into an electrical signal, which is converted by the corresponding ADC module and then input into the signal preprocessing module. The signal preprocessing module processes the signal and then outputs it to the multi-channel dual-phase lock-in amplifier.

[0010] Preferably, the signal preprocessing module includes a filtering module, a data buffer FIFO, a subtractor, a mean calculation module and a multiplier; the input signal is processed by the filtering module which integrates the median and mean filtering functions and is then sent to the FIFO and the mean calculation module at the same time. The mean calculation module calculates the average value. After the average value calculation is completed, the data processed by the filtering module is read from the FIFO, and the subtractor is used to subtract the result of the mean calculation from these data to achieve a debiasing operation; when the amount of data read from the FIFO reaches a preset number of data, the reading process will stop, and then the debiasing part will prepare to start the next round of operation.

[0011] Preferably, the processing process of the multi-channel peak extraction module includes:

[0012] Setting a threshold between the second harmonic signals;

[0013] The portion greater than the threshold is judged as the peak interval;

[0014] Extract the peak value of the corresponding peak interval from each peak interval;

[0015] The peak values ​​of all peak intervals are compared and the two largest peak values ​​are extracted.

[0016] Preferably, the UDP module includes a UDP sending module and a UDP receiving module; the UDP sending module includes a data buffer FIFO, a frame generation module, a RAM, an IP header detection, a UDP header detection, a CRC32 calculation module and an output double data rate module ODDR; the UDP receiving module includes an input double data rate module IDDR, a frame filtering module, a CRC32 de-checking module and a data buffer FIFO.

[0017] Preferably, the FPGA further includes a configuration interface, and the host computer sends configuration commands to the configuration interface via the UDP protocol.

[0018] Preferably, the ADC module adopts the ADS8363S main chip.

[0019] Compared with the prior art, the present invention has the following beneficial effects:

[0020] (1) The present invention can simultaneously generate the required modulation signal and reference signal, and can simultaneously collect multi-channel original signals. By processing the signals of multiple channels inside the FPGA, the harmonic signals and peak signals required for TDLAS measurement are extracted. In addition, the complexity of the system is effectively reduced by adopting frequency division multiplexing technology. This design improves the efficiency of data processing and the scalability of the system.

[0021] (2) The present invention can be flexibly configured through different program designs without changing the hardware circuit, and can display multi-channel signals in real time through MATLAB based on the UDP protocol, which is suitable for different experimental scenarios. The hardware structure of the entire system is smaller while maintaining the multi-channel data processing performance, which is convenient for integration into the TDLAS system. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0023] Figure 1 Schematic diagram of the overall structure of the hardware part of the FPGA-based multi-channel TDLAS data real-time processing system of an embodiment of the present application;

[0024] Figure 2 A schematic diagram of the hardware structure of the FPGA according to an embodiment of the present application;

[0025] Figure 3 Schematic diagram of the overall structure of the software portion of the FPGA-based multi-channel TDLAS data real-time processing system according to an embodiment of the present application;

[0026] Figure 4 This is a timing diagram of a half-clock mode according to an embodiment of the present application;

[0027] Figure 5 This is a schematic diagram of the structure of a superposition signal generator module according to an embodiment of the present application;

[0028] Figure 6 Schematic diagram of the structure of the sine wave signal generator DDS1 according to an embodiment of the present application;

[0029] Figure 7 Schematic diagram of the structure of the sine wave signal generator DDS2 according to an embodiment of the present application;

[0030] Figure 8 This is a schematic structural diagram of a signal preprocessing module according to an embodiment of the present application;

[0031] Figure 9 This is a schematic structural diagram of a multi-channel dual-phase lock-in amplifier according to an embodiment of the present application;

[0032] Figure 10 A schematic structural diagram of an FIR filter according to an embodiment of the present application;

[0033] Figure 11A schematic diagram of a threshold method according to an embodiment of the present application;

[0034] Figure 12 This is a schematic diagram of the internal structure of the UDP sending module of an embodiment of the present application;

[0035] Figure 13 This is a schematic diagram of the internal structure of the UDP receiving module of an embodiment of the present application;

[0036] Figure 14 This is a schematic diagram of the configuration command frame structure of an embodiment of the present application;

[0037] Figure 15 A schematic diagram of the configuration process of an embodiment of the present application;

[0038] Figure 16 This is a schematic diagram of the MATLAB and FPGA periodic communication process in an embodiment of the present application. DETAILED DESCRIPTION

[0039] To make the objectives, technical solutions, and advantages of the present invention more apparent, the present invention will be further described in detail below with reference to the accompanying drawings. It is apparent that the embodiments described are only some, not all, of the present invention. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without creative effort are intended to fall within the scope of protection of the present invention.

[0040] The present invention discloses a multi-channel TDLAS data real-time processing system based on FPGA, comprising: M laser drivers, M DFB lasers of different wavelengths, N collimating mirrors, N photodetectors, an FPGA and a host computer installed with MATLAB; the FPGA comprises N ADC modules, N multi-channel dual-phase lock-in amplifiers, N multi-channel peak extraction modules, M DAC modules, a UDP module and M superposition signal generators; each superposition signal generator generates a modulation signal matching the corresponding laser and outputs it to the corresponding laser driver through the DAC module; the output of each laser driver is connected to the corresponding DFB laser to drive the DFB laser to emit laser light; after the DFB laser emits light, the light is combined with the 1X optical fiber combiner through the MX1 optical fiber combiner. An N-fiber beam splitter divides M laser beams into N optical paths. After the laser passes through the test area, a photodetector converts the light intensity signal of the corresponding optical path into an electrical signal. This signal is then converted and output to a multi-channel dual-phase lock-in amplifier via the corresponding ADC module. Each multi-channel dual-phase lock-in amplifier extracts the first harmonic signal, second harmonic signal, second harmonic X component, and second harmonic Y component of the corresponding optical path. The multi-channel peak extraction module then extracts the peak signals of the second harmonic signal, second harmonic X component, and second harmonic Y component. The FPGA transmits the extracted harmonic and peak signals of each optical path to the host computer's MATLAB through the UDP module for data processing and real-time display. MATLAB also uses the harmonic and peak signals to calculate temperature and gas concentration and displays them in real time. M and N are both greater than or equal to 1.

[0041] like Figure 1 As shown, in this embodiment, M is equal to 2, that is, two DFB lasers with different wavelengths are used as an example for description. Correspondingly, the number of the laser driver, DAC module, and superposition signal generator is 2.

[0042] like Figure 2 The figure shows a schematic diagram of the FPGA hardware structure of an embodiment. The FPGA allows for flexible expansion module changes based on varying sampling rate requirements and changes in ADC and DAC channels, without having to replace the entire FPGA board. Considering the system's Ethernet and storage requirements, the present invention adds an Ethernet PHY chip and a NAND flash chip to the FPGA board. Furthermore, the FPGA board also includes a reserved high-speed expansion interface that can be used to expand the number of ADC and DAC channels, or increase the number of Ethernet PHY chips, to support the parallel operation of multiple TDLAS processing systems.

[0043] In this embodiment, the MT29F16G08 series NAND Flash memory chip is used. Its key features include 16Gb storage capacity, an operating voltage range of 2.7V to 3.6V, and NAND Flash technology. NAND Flash is suitable for storing large amounts of spectral data, and a multi-chip NAND Flash design can be used to meet the needs of multi-channel spectral data storage.

[0044] In this embodiment, the Ethernet PHY chip uses a Gigabit Ethernet (1Gigabit Ethernet) PHY chip RTL8211E, which is mainly used to build a high-speed and reliable network connection.

[0045] In this embodiment, the FPGA board PCB is designed with a 6-layer board structure, where the top and bottom layers are mainly used to place components and connect the signal lines of each component. The second and fifth layers are complete ground planes, the third layer is a signal layer, and the fourth layer is a power supply layer. For BGA fan-out, the main considerations are the number of pins, layout, and spacing, as well as the space limitations of the PCB. When performing BGA fan-out, EMI / EMC (electromagnetic interference / electromagnetic compatibility) control issues are also considered, and measures are taken to reduce the impact of electromagnetic interference. The power supply system covers both analog and digital parts. Since the FPGA consumes a lot of current, it is also necessary to pay attention to the copper width, the current flow capacity of vias and traces. At the same time, the current input and output loop area should be minimized to reduce the intensity of high-order harmonic radiation. For the RGMII interface of the Ethernet PHY chip, the complete ground plane should be used as a reference to avoid over-division. At the same time, the chip should be close to the RJ45 network port with a transformer. Differential routing should be used between the two, and the reference ground (PGND) of the network port and the digital ground (DGND) should be connected through a ferrite bead.

[0046] In addition, the core components of the photodetector circuit of this embodiment include a photodiode and a signal amplification circuit. This embodiment uses a photodiode made of indium gallium arsenide (InGaAs) material. Photodiodes made of this material have fast response characteristics to light signals and can effectively convert weak light signals into strong electrical signals, achieving highly sensitive photodetection.

[0047] Specifically, a transimpedance amplifier (TA) is constructed using the ADA4817-1 op amp to amplify the photodiode output. The TIA's design takes into account the low voltage and high impedance characteristics of the photodiode's output signal. By appropriately setting the feedback resistor, it achieves signal amplification and conversion. The TIA's output is then filtered using an RC filter circuit. This RC filter effectively removes high-frequency noise and interference, retaining the desired signal components. The filter parameters are selected based on the desired cutoff frequency and filter order to ensure that the filtering effect meets the design requirements. Finally, a voltage follower circuit, constructed using the ADA4622-2 op amp, outputs the filtered signal.

[0048] Furthermore, to meet the needs of parallel processing of TDLAS multi-channel data and adapt to different experimental scenarios, each module in the system was customized and multiple parameter configuration interfaces were added. Finally, the host computer program was designed using MATLAB and connected to the FPGA.

[0049] like Figure 3 FIG. 1 is a schematic diagram showing the overall structure of the software portion of the FPGA-based multi-channel TDLAS data real-time processing system according to an embodiment of the present invention. The system mainly includes two parts: an FPGA program and a MATLAB program.

[0050] The FPGA program primarily includes a superposition signal generator, a DAC module, an ADC module, a signal preprocessing module, a multi-channel dual-phase lock-in amplifier, a multi-channel peak extraction module, and a UDP module. Two independent superposition signal generators generate superposition signals of varying amplitudes and offsets, which modulate two DFB lasers of different wavelengths through the DAC modules. After successfully receiving the photodetector's output signal, the ADC module transmits it to the signal preprocessing module for debiasing, filtering, and amplification. Subsequently, the multi-channel dual-phase lock-in amplifier accurately extracts the first and second harmonics, as well as the second harmonic X and Y components, of the two modulated signals. The multi-channel peak extraction module then extracts the peak values ​​of these harmonic components. Finally, the FPGA transmits the raw ADC signal, the optimized preprocessed signal, the multi-channel dual-phase lock-in amplifier output signal, and the peak extraction results to MATLAB via the UDP protocol for real-time display and temperature calculation. The FPGA also receives configuration information from MATLAB, ensuring the flexibility of the entire system.

[0051] It should be noted that in order to meet different experimental scenarios, the number of channels within the FPGA program can be set according to the number of photodetectors.

[0052] The implementation of each module of FPGA is described in detail below.

[0053] (1)ADC module

[0054] The ADC module uses the ADS8363S main chip. The chip integrates two successive approximation analog-to-digital converters (SAR ADCs) with 16-bit resolution and 1MSPS (million times per second) sampling rate. Before the analog-to-digital converter, it is an indispensable step to properly configure the internal registers of the integrated circuit. ADS8363S provides two configuration modes: half-speed clock mode and full-speed clock mode. In half-speed clock mode, the clock frequency can reach up to 20MHz, while in full-speed clock mode, the maximum frequency can reach 40MHz. Although the clock frequencies in the two modes are different, their sampling rates remain consistent. In this embodiment, the half-clock mode is used to configure the ADS8363S. The half-clock mode timing diagram is shown as follows. Figure 4 shown.

[0055] like Figure 4 As shown in the figure, triggered by the rising edge of the CONVST signal, the device undergoes an asynchronous transition from the sample state to the hold state. During this transition, the external CLOCK BUSY output pin goes high and remains in this state throughout the conversion cycle. At the falling edge of the following CLOCK cycle, the device selects the channel and initiates the next conversion cycle based on the C[1:0] bits in the CONFIG register. 00, 01, 10, and 11 correspond to SAR ADC channels 1, 2, 3, and 4, respectively. As the next cycle approaches, the SDOA and SDOB interfaces output the conversion results of the corresponding channels.

[0056] (2) Superposition signal generator module

[0057] In the research on combustion temperature measurement, considering the use of two lasers with different wavelengths and the significant differences in performance parameters of these two lasers, two independent superposition signal generation modules were designed. Each superposition signal generation module generates triangular wave and sine wave signals of specific frequencies to achieve independent control and drive of the two lasers. In this way, it can be ensured that each laser can provide laser output that precisely corresponds to the absorption characteristics of a specific gas. This design strategy not only optimizes the performance matching of the lasers, but also significantly improves the accuracy and reliability of combustion temperature measurements by precisely controlling the laser output. Accurate laser output is crucial for capturing gas absorption peaks, as these absorption peaks are key indicators for combustion temperature diagnosis.

[0058] The superposition signal generator module is mainly composed of a superposition signal generator and a digital-to-analog converter (DAC). The superposition signal generator consists of a sine wave signal generator (DDS1), a triangle wave signal generator (DDS2) and an adder. Figure 5 shown.

[0059] DDS1 generates a high-frequency sinusoidal modulation signal, and its external interface supports flexible adjustment of the sinusoidal frequency, amplitude, and offset. DDS2 is specifically designed to generate a low-frequency triangle wave sweep signal, and its external interface similarly allows adjustment of the triangle wave's frequency, amplitude, and offset. This design allows DDS1 and DDS2 to adapt to different DFB laser models, ensuring modulation and sweep accuracy and compatibility. An adder then superimposes the high-frequency sinusoidal modulation signal and the low-frequency triangle wave sweep signal to generate a composite signal, which is then transmitted to the DAC for output.

[0060] like Figure 6 As shown in Figure 1, the core architecture of the DDS1 consists of several key modules, including a phase accumulator, a phase modulator, a waveform data table read-only memory (ROM), and a divider. The phase accumulator generates a phase increment that controls the output frequency and synchronizes this accumulated value to a register for update on each rising edge of the clock signal, thereby maintaining the continuity and stability of the phase accumulation process. The phase modulator receives the output from the phase accumulator and applies a phase offset to it, achieving phase modulation of the signal. To ensure the adaptability of the DDS output signal, the waveform data table ROM pre-stores sine wave amplitude data that matches the DAC resolution. This ROM reads the corresponding voltage amplitude based on the phase code provided by the phase modulator and outputs the corresponding digital signal. To precisely control the amplitude and offset of the output signal, a divider and adder are connected in series after the waveform data table ROM. The divider adjusts the signal amplitude, while the adder sets the offset voltage, enabling fine signal control.

[0061] like Figure 7 As shown in Figure 1, DDS2 is structurally similar to DDS1, but with one significant difference: DDS2 uses a bit-width truncation module instead of the traditional ROM. This design has the advantage of not consuming FPGA memory resources. The bit-width truncation module works by truncation of the high-order bits of the phase modulator output signal.

[0062] (3) Multi-channel harmonic extraction module

[0063] The multi-channel harmonic extraction module includes a signal preprocessing module and a multi-channel dual-phase lock-in amplifier. The multi-channel harmonic extraction module is the core component of the TDLAS system responsible for processing multiple channel signals and extracting key harmonic information. The module first receives the signal from the ADC module and the reference signal generated by the superposition signal generator. After multiplication by the multiplier, the high-frequency noise is filtered out using a low-pass filter, retaining the low-frequency signal related to gas absorption. Subsequently, the multi-channel harmonic extraction module extracts the first harmonic signal, second harmonic signal, second harmonic X component and second harmonic Y component from the signal, and records the peak values ​​of these components through peak detection. These peak values ​​are key data for gas temperature and concentration inversion.

[0064] The design of the multi-channel harmonic extraction module ensures the ability to accurately extract harmonic signals from multiple channels, providing the foundation for real-time monitoring and analysis of the combustion process. By processing multiple signals in parallel, the TDLAS system is able to respond quickly and provide highly accurate measurement results. Further improvements to this module will help expand the application range and enhance the performance of the TDLAS system.

[0065] The signal preprocessing module integrates multiple functions such as debiasing, amplification, and noise reduction to address light intensity fluctuations caused by flame jumps when the laser passes through the flame combustion area. Such fluctuations will directly affect the stability of the output signal of the photodetector, thereby adversely affecting the final data processing results. The debiasing function can effectively eliminate the electrical signal offset caused by light intensity fluctuations, ensuring signal accuracy. In addition, according to different experimental requirements, the module can also appropriately amplify the signal to improve the accuracy and reliability of subsequent digital signal processing. Through the combined use of these functions, the signal preprocessing module significantly improves the quality of the output signal of the dual-phase lock-in amplifier.

[0066] The internal structure of the signal preprocessing module is as follows Figure 8 As shown in FIG, the structure mainly includes a filtering module, a data buffer (FIFO), a subtractor, a mean calculation module, and a multiplier, and is equipped with three adjustable parameters: filtering order, number of data, and amplification factor.

[0067] When a signal is input, it is first processed by the filtering module. The signal preprocessing module integrates median and mean filtering functions, and the filter order can be flexibly adjusted according to actual operating conditions to ensure that the collected data has ideal smoothness. The data is then fed into the FIFO and the mean calculation module simultaneously. The mean calculation module is responsible for calculating the average value of the same number of data as the data to provide information on the central trend of the data. Once the average calculation is completed, the system begins reading data from the FIFO and uses a subtractor to subtract the result of the mean calculation from these data to achieve a debiasing operation. When the amount of data read from the FIFO reaches the preset number of data, the reading process will stop, and the debiasing part will then prepare to begin the next round of operations. This design ensures flexibility in signal preprocessing and can adapt to different experimental conditions.

[0068] Multi-channel dual-phase lock-in amplifier needs to extract the R of environmental background and gas absorption signal 1f 、R 2f 、X 2f and Y 2f , namely the first harmonic signal, the second harmonic signal, the second harmonic X component and the second harmonic Y component. The main function of the multi-channel dual-phase lock-in amplifier is to extract the first harmonic signal, the second harmonic signal, the second harmonic X component and the second harmonic Y component of two different frequency modulation signals, such as Figure 9As shown. In this embodiment, each multi-channel dual-phase lock-in amplifier includes two dual-phase lock-in amplifiers. Each dual-phase lock-in amplifier includes a number of multipliers, low-pass filters and square root modules; the pre-stored modulation signal is used as the first reference signal to perform sine operation and cosine operation respectively, and then the sine operation results and cosine operation results are respectively calculated with the input signal through the multiplier, and the multiplication results of the two are respectively processed through the low-pass filter, and the signals filtered by the two low-pass filters are calculated through the multiplier and then processed by the square root module to obtain the first harmonic signal; the pre-stored modulation signal is multiplied by 2 and used as the second ... and cosine operation are respectively calculated. The sine and cosine calculation results are respectively multiplied with the input signal through a multiplier, and the multiplication results of the two are processed by low-pass filters. The signals filtered by the two low-pass filters are then multiplied and processed by a square root module to obtain the second harmonic signal. The signal filtered by one low-pass filter is input into the multiplier for calculation and then processed by a square root module to obtain the second harmonic X component. The signal filtered by the other low-pass filter is input into the multiplier for calculation and then processed by a square root module to obtain the second harmonic Y component. It should be noted that the reference signal uses the DDS portion of the signal superposition module. Since the reference signal used to extract the second harmonic is twice that of the first harmonic, the modulation frequency parameter needs to be multiplied by 2 when it is input into the reference signal of the second harmonic channel. To ensure that the multi-channel dual-phase lock-in amplifier module maintains the phase consistency of the extracted signals, both the X and Y components of the second harmonic are square rooted, thereby simplifying the signal processing process and improving the efficiency of subsequent peak extraction.

[0069] In this embodiment, an FIR filter is used to form a low-pass filter. On the FPGA platform, the application of a finite impulse response (FIR) filter shows significant advantages. Thanks to the efficient parallel processing capability of the FPGA, the various taps of the FIR filter can be calculated simultaneously, significantly improving the data processing speed, which is particularly suitable for the needs of high-speed and real-time processing. The programmable characteristics of the FPGA give the FIR filter extremely high flexibility, allowing the filter coefficients and order to be dynamically adjusted according to the specific application requirements. The design of the FIR filter does not include a feedback loop, thereby avoiding the system stability problem that may be caused by feedback. The resource optimization characteristics of the FPGA further enable the implementation of the FIR filter to be fine-tuned according to the hardware resources to achieve the optimal balance between performance and resource utilization.

[0070] In addition, the design process of FIR filters is relatively straightforward and simple, and the filter coefficients can be determined through methods such as window function method and frequency sampling method. The design flexibility of this filter enables it to adapt to various filtering requirements, such as low-pass, high-pass, band-pass and other types.

[0071] like Figure 10 Figure 2 shows a schematic diagram of the FIR filter structure. The properties of the Fourier transform indicate that the convolution of two signals in the time domain can be viewed as a multiplication operation in the frequency domain. According to the Fourier transform principle, the convolution of time-domain signals corresponds to the multiplication of frequency-domain signals. This property enables the convolution operation to selectively enhance or suppress the frequency components of a signal, thereby achieving the purpose of filtering.

[0072] To prevent inter-channel interference, you can increase the order of the FIR filter to narrow the filter passband. Therefore, in the MATLAB filter design tool, set the filter order to 800, the gen function to Chebyshev, the sidelobe attenuation to 100dB, the sampling rate to 1MHz, and the cutoff frequency to 1kHz. After setting these parameters, the filter design tool will generate the FIR filter tap coefficients as double-precision floating-point numbers. These double-precision floating-point numbers need to be converted to fixed-point numbers for output and saved as a COE file.

[0073] In the Xilinx Vivado integrated development environment, the FIR Compiler IP core is designed to implement FIR filters. Users can generate tap coefficients using the MATLAB filter design tool and import the generated COE file into the FIR Compiler IP core. The FIR Compiler IP core supports multi-channel data input, which means it can process data from multiple data sources simultaneously. In multi-channel mode, each channel has its own independent data stream but shares the same filter coefficients and configuration. By configuring the number of channels of the IP core, users can flexibly expand processing capabilities according to application requirements. Figure 9 For example, eight low-pass filters are used. Assigning independent coefficients and configurations to each filter would not only consume a large amount of FPGA internal memory resources but also increase design complexity. However, by using the FIR Compiler IP core's multi-channel data input mode, the design in this embodiment can efficiently share the same filter coefficients and configurations, significantly optimizing resource utilization and simplifying the design process.

[0074] In traditional FIR filter design, the input data sampling rate often matches the system clock frequency. When the sampling rate and clock frequency are equal, an n-order FIR filter design requires n+1 multiplication structures, consuming n+1 multiplier resources (i.e., DSP). However, the FIR Compiler IP core provides an oversampling mode that addresses this issue, allowing the input data frequency to exceed the FIR system clock frequency. By leveraging DSP time-division multiplexing, oversampling mode effectively reduces resource usage, achieving resource optimization and efficient utilization.

[0075] (4) Multi-channel peak extraction module

[0076] Because the output signals of a multi-channel dual-phase lock-in amplifier maintain consistent phase, only one signal peak from the second harmonic and its X and Y components needs to be extracted for each wavelength; the remaining signals can be represented by the values ​​at that peak. It is worth noting that the amplitudes of the X and Y components of the second harmonic vary significantly with changes in the input signal phase. However, the second harmonic output by the dual-phase lock-in amplifier has a unique characteristic: its amplitude does not change with changes in the input signal phase, making it the signal most suitable for accurate peak extraction. In this embodiment, the multi-channel peak extraction module uses two methods to identify and extract these peaks. The first method is to find the maximum value within a complete cycle of the triangular wave scanning signal. Specifically, a register with an initial value of 0 is continuously compared with the second harmonic signal. Whenever a signal value greater than the current value in the register is encountered, the register is updated with the new signal value. This process continues until the end of a complete cycle. However, this method has a significant drawback: the second harmonic actually has two peaks within a single triangular wave cycle. However, using this method, only one peak can be extracted per cycle, which reduces the time resolution of the detection. To solve this problem, a second method of setting the threshold is added to extract the peak value. First, a threshold between the second harmonic amplitude is set, such as Figure 11 shown.

[0077] The portion greater than the threshold is considered a peak interval. If the second harmonic noise is low, one cycle of the second harmonic will have six peak intervals. Then, using the first method, the peak values ​​P1, P2, P3, P4, P5, and P6 of these six peak intervals are extracted. Finally, these six peak values ​​are compared to determine the effective second harmonic peak values ​​P2 and P5.

[0078] (5)UDP module

[0079] The UDP module includes a UDP sending module, a UDP receiving module and a configuration module.

[0080] The UDP sending module mainly includes FIFO, frame generation module, RAM, IP header detection, UDP header detection, CRC32 calculation module, ODDR (Output Double Data Rate), such as Figure 12 As shown in the figure, data is first buffered in the FIFO. When the data buffered in the FIFO reaches the data length specified in the UDP frame structure, the frame generation module begins reading data from the FIFO. In the frame generation module, multiple registers are used to latch the Ethernet frame header, IP header, and UDP header of the UDP transmit frame. These values ​​can be modified based on usage. Once the UDP transmit frame is generated, it is stored in RAM and simultaneously input to the IP header detection module and the UDP header detection module.

[0081] The UDP receiving module mainly includes IDDR (Input Double Data Rate), frame filtering module, CRC32 decoding module, FIFO, such as Figure 13 shown.

[0082] First, UDP packets are received via the RGMII protocol via an external Ethernet PHY chip. The double-rate data is then converted to single-rate data using the IDDR primitive. During transmission, these packets are securely stored in a FIFO to ensure no data loss or reordering occurs during processing. Simultaneously, the data is passed to the frame filtering module and the CRC32 de-checking module. The frame filtering module filters UDP packets based on user-defined parameters such as the IP address, source port number, and destination port number. When the CRC32 de-checking module receives a UDP packet carrying a CRC value, it first extracts the packet's payload and the appended CRC value. The receiving FPGA then recalculates the payload's CRC value using the same CRC32 algorithm and polynomial as the transmitting end. If the frame filtering and CRC32 de-checking modules' calculations are correct, the user data in the UDP packet is output.

[0083] The design of the configuration module is as follows.

[0084] When designing modules such as the superposition signal generator, multi-channel dual-phase lock-in amplifier, and signal preprocessing, multiple configuration interfaces are reserved to facilitate dynamic modification of module parameters and working status. In order to simplify the parameter configuration process, this design uses the host computer to send configuration commands through the UDP protocol. The frame structure of the configuration command is as follows: Figure 14As shown in the figure, the frame structure consists of a configuration command frame header, an address, and a parameter value. The configuration command frame header contains eight 8-bit data bits that clearly distinguish the configuration command from other commands, effectively preventing FPGA misoperation. Within the FPGA, this design uses registers with different addresses to store each parameter value. The address information in the configuration command frame structure accurately matches the corresponding parameter. The last four 8-bit data bits of the configuration command frame structure form a 32-bit parameter value.

[0085] Before the FPGA program runs normally, it is necessary to configure the parameters. The configuration process is as follows: Figure 15 As shown. First, the host computer program defines the corresponding parameter values ​​in the FPGA as an array, where the address of each parameter value in the array must correspond to the address in the FPGA. After the parameter initialization is completed, the parameter value with address 0 is first sent to the FPGA via the UDP protocol. After receiving the configuration command, the FPGA begins to write the parameter value to the corresponding module. After the write is completed, the FPGA will read the parameter value and return it to the host computer via the UDP protocol. Subsequently, the host computer will compare the sent parameter value with the received value. If the two are the same, it means that the configuration is successful and the parameter value of the next address will be configured. If the two are different, it means that the parameter value needs to be reconfigured. Once the host computer program has sent the parameter value array and successfully compared with the data returned by the FPGA, the configuration process is completed and the TDLAS data reading operation can begin.

[0086] (6) MATLAB program

[0087] The MATLAB program's main functions include UDP reception and transmission, waveform display, and FPGA configuration. Once the FPGA is powered on, MATLAB transmits the necessary configuration information to the FPGA via the UDP protocol. The FPGA then flexibly adjusts the parameters of various modules based on this configuration information to accommodate diverse experimental scenarios. Once the FPGA is configured, MATLAB receives real-time signal data from the FPGA and displays it intuitively through the waveform display module. MATLAB also uses signal peak data extracted by the FPGA to calculate gas temperature.

[0088] The cyclic communication process between MATLAB and FPGA is as follows Figure 15As shown. MATLAB first initializes the configuration of the FPGA and then initiates a peak reading request. Given that the amount of data processed by TDLAS multi-channel data may exceed the communication bandwidth of both parties, it is crucial to take appropriate measures to ensure the integrity of the peak data transmitted to MATLAB. After receiving the request, the FPGA will perform data extraction and send the peak information. In addition, the transmission of gas absorption signals and their harmonic signals can also be customized through configuration information to adapt to different data transmission requirements. Through these steps, efficient and reliable data exchange is achieved, providing a solid data foundation for subsequent analysis. After the communication process is completed, you can choose to store the peak value and other data, or perform real-time temperature calculation. Choosing real-time temperature calculation will affect the transmission efficiency of the peak value and other data. Especially when the laser scanning frequency is high, peak value loss may occur.

[0089] The present invention can simultaneously generate the required modulation signal and reference signal, and can simultaneously collect multi-channel original signals, process the signals of multiple channels through the internal FPGA, extract the harmonic signals and peak signals required for TDLAS measurement, and effectively reduce the complexity of the system by adopting frequency division multiplexing (using a multi-channel dual-phase lock-in amplifier to divide the same beam signal into two signal ends for demultiplexing processing, each signal end processes a wavelength, and processes the relevant harmonic information of the two wavelength optical signals). This design improves the efficiency of data processing and the scalability of the system. At the same time, without changing the hardware circuit, it can be flexibly configured through different program designs, and real-time display of multi-channel signals can be performed through MATLAB through the UDP protocol, which is suitable for different experimental scenarios. The entire system has a smaller hardware structure volume while maintaining the multi-channel data processing performance, which is convenient for the integration of the TDLAS system.

[0090] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or make equivalent replacements for some or all of the technical features therein. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A multi-channel TDLAS data real-time processing system based on FPGA, characterized in that: include: M laser drivers, M DFB lasers with different wavelengths, N collimating lenses, N photodetectors, an FPGA and a host computer installed with MATLAB; the FPGA includes N ADC modules, N multi-channel dual-phase lock-in amplifiers, N multi-channel peak extraction modules, M DAC modules, a UDP module and M superposition signal generators; each superposition signal generator generates a modulation signal that matches the corresponding laser and outputs it to the corresponding laser driver through the DAC module, and the output of each laser driver is connected to the corresponding DFB laser to drive the DFB laser to emit laser light; after the DFB laser emits light, it is connected to the 1X optical fiber combiner through the MX 1 optical fiber combiner. An N-fiber beam splitter divides M laser beams into N optical paths. After the laser passes through the test area, a photodetector converts the light intensity signal of the corresponding optical path into an electrical signal. This signal is then converted and output to a multi-channel dual-phase lock-in amplifier via the corresponding ADC module. Each multi-channel dual-phase lock-in amplifier extracts the first harmonic signal, second harmonic signal, second harmonic X component, and second harmonic Y component of the corresponding optical path. The multi-channel peak extraction module then extracts the peak signals of the second harmonic signal, second harmonic X component, and second harmonic Y component. The FPGA transmits the extracted harmonic and peak signals of each optical path to the host computer's MATLAB through the UDP module for data processing and real-time display. MATLAB also uses the harmonic and peak signals to calculate temperature and gas concentration and displays them in real time. M and N are both greater than or equal to 1.

2. The FPGA-based multi-channel TDLAS data real-time processing system according to claim 1, characterized in that: Each multi-channel dual-phase lock-in amplifier includes M dual-phase lock-in amplifiers, which are used to respectively extract the first harmonic signal, the second harmonic signal, the second harmonic X component and the second harmonic Y component of the modulation signals of M different frequencies; each dual-phase lock-in amplifier includes a number of multipliers, a low-pass filter and a square root module; the pre-stored modulation signal is used as the first reference signal to perform sine operation and cosine operation respectively, and then the sine operation results and the cosine operation results are respectively calculated with the input signal through the multiplier, and the multiplication results of the two are respectively processed through the low-pass filter, and the signals filtered by the two low-pass filters are calculated through the multiplier and then processed by the square root module to obtain the first harmonic signal; the pre-stored modulation signal is used as the first reference signal to perform sine operation and cosine operation respectively, and then the sine operation results and the cosine operation results are respectively calculated with the input signal through the multiplier, and the multiplication results of the two are respectively processed through the low-pass filter, and the signals filtered by the two low-pass filters are calculated through the multiplier and then processed by the square root module to obtain the first harmonic signal; The stored modulated signal is multiplied by 2 and used as a second reference signal to perform sine and cosine operations respectively. The sine and cosine operation results are then respectively operated on with the input signal through a multiplier, and the multiplication results of the two are respectively processed through low-pass filters; the signals filtered by the two low-pass filters are operated through the multiplier and then subjected to square root processing through a square root module to obtain a second harmonic signal; the signal filtered by one of the low-pass filters is input into the multiplier for operation and then subjected to square root processing through the square root module to obtain a second harmonic X component; the signal filtered by the other low-pass filter is input into the multiplier for operation and then subjected to square root processing through the square root module to obtain a second harmonic Y component.

3. The FPGA-based multi-channel TDLAS data real-time processing system according to claim 1, characterized in that: The low-pass filter adopts an FIR filter, and the order can be configured through MATLAB.

4. The FPGA-based multi-channel TDLAS data real-time processing system according to claim 1, characterized in that: The superposition signal generator includes a sine wave signal generator for generating a high-frequency sine wave modulation signal, a sine wave signal generator for generating a low-frequency triangle wave scanning signal, and an adder; the frequency, assignment, and offset of the sine wave signal generator and the sine wave signal generator can be configured through MATLAB to adapt to DFB lasers of different wavelengths; the adder superimposes the high-frequency sine wave modulation signal and the low-frequency triangle wave scanning signal to generate a composite modulation signal.

5. The FPGA-based multi-channel TDLAS data real-time processing system according to claim 1, characterized in that: The FPGA also includes a signal preprocessing module arranged between the ADC module and the multi-channel dual-phase lock-in amplifier. The photodetector converts the light intensity signal of the corresponding optical path into an electrical signal, which is then converted by the corresponding ADC module and input into the signal preprocessing module. The signal preprocessing module processes the signal and then outputs it to the multi-channel dual-phase lock-in amplifier.

6. The FPGA-based multi-channel TDLAS data real-time processing system according to claim 5, characterized in that: The signal preprocessing module includes a filtering module, a data buffer FIFO, a subtractor, a mean calculation module and a multiplier. The input signal is processed by the filtering module that integrates median and mean filtering functions and then sent to the FIFO and the mean calculation module at the same time. The mean calculation module calculates the average value. After the average value calculation is completed, the data processed by the filtering module is read from the FIFO, and the subtractor is used to subtract the result of the mean calculation from the data to achieve a debiasing operation. When the amount of data read from the FIFO reaches a preset number of data, the reading process will stop, and then the debiasing part will prepare to start the next round of operation.

7. The FPGA-based multi-channel TDLAS data real-time processing system according to claim 1, characterized in that: The processing process of the multi-channel peak extraction module includes: Setting a threshold between the second harmonic signals; The portion greater than the threshold is judged as the peak interval; Extract the peak value of the corresponding peak interval from each peak interval; The peak values ​​of all peak intervals are compared and the two largest peak values ​​are extracted.

8. The FPGA-based multi-channel TDLAS data real-time processing system according to claim 1, characterized in that: The UDP module includes a UDP sending module and a UDP receiving module; the UDP sending module includes a data buffer FIFO, a frame generation module, a RAM, an IP header detection, a UDP header detection, a CRC32 calculation module and an output double data rate module ODDR; the UDP receiving module includes an input double data rate module IDDR, a frame filtering module, a CRC32 de-checking module and a data buffer FIFO.

9. The FPGA-based multi-channel TDLAS data real-time processing system according to claim 1, characterized in that: The FPGA further includes a configuration interface, and the host computer sends configuration commands to the configuration interface via the UDP protocol.

10. The FPGA-based multi-channel TDLAS data real-time processing system according to claim 1, characterized in that: The ADC module uses the ADS8363S main chip.

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