Method for determining thermal cycle test scheme of electronic device of nanometer time grating displacement sensor

Abstract

The invention discloses a method for determining a thermal cycle test scheme of an electronic device of a nanometer time grating displacement sensor, which aims at a specific nanometer time grating displacement sensor, considers the working temperature range of the electronic device of different nanometer time grating displacement sensors, and remarkably improves the accuracy of a test result. According to the method, a Coffin-Manson thermal fatigue life theory and a Miner linear cumulative damage theory are fused, and the effectiveness and acceptability of a thermal cycle test are scientifically analyzed, so that a reasonable and efficient test scheme is formulated. The method not only can evaluate whether various thermal cycle test schemes adopted by electronic devices of different nanometer time grating displacement sensors are reasonable and effective, but also can effectively avoid the problems of understress and overstress, prevents products from unnecessary damage while avoiding missing detection of faults, has stronger pertinence and rationality, and is suitable for popularization and application. And the application risk of an electronic device of the nanometer time grating displacement sensor in precise displacement measurement is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of nano-time grating, and in particular to a method for determining a thermal cycle test scheme for an electronic device of a nano-time grating displacement sensor. Background Art

[0002] Nanotime-grating technology is a high-precision displacement measurement technique that uses time to measure space. Due to its high precision, high reliability, and strong anti-interference capabilities, it is gradually becoming an ideal alternative to traditional optical measurement technologies. Its products include two categories: nanolinear time-grating and nanocircular time-grating. During the development of nanotime-grating displacement sensors, effective thermal cycling tests can help R&D personnel identify potential early failures of nanotime-grating displacement sensors, allowing targeted improvements to ensure their reliability and service life under normal operating conditions.

[0003] Currently, thermal cycling tests for nano-time-grating displacement sensors are primarily conducted in accordance with the relevant provisions of GB / T 2423.1-2008 and GB / T 2423.2-2008. However, these standards employ the same testing requirements for different electrical and electronic product components, failing to consider the operating characteristics of the electronic components of different nano-time-grating displacement sensors and lacking specificity. This "one-size-fits-all" testing approach frequently results in failures of the electronic components of nano-time-grating displacement sensors that pass thermal cycling tests within their designed lifecycles. Furthermore, existing thermal cycling tests overlook the dual risks associated with the rationality of test stress settings: overstressing may cause unnecessary damage to qualified components, weakening their inherent reliability; while understressing may fail to fully stimulate latent defects, leading to missed fault detection. Both of these situations seriously affect the test results' ability to accurately assess the product's actual reliability. Summary of the Invention

[0004] In view of the above-mentioned deficiencies in the prior art, the purpose of the present invention is to provide a method for determining a thermal cycling test scheme for electronic devices of a nano-time-grating displacement sensor, so as to solve the problems that the existing thermal cycling test standards do not take into account the working characteristics of electronic devices of different nano-time-grating sensors, lack of specificity, resulting in inaccurate test results, and the prior art does not take into account the rationality of the test stress setting, causing the product to suffer unnecessary damage under overstress, reducing reliability, or failing to fully stimulate potential defects under understress, resulting in missed fault detection.

[0005] In order to solve the above technical problems, the technical solution adopted by the present invention is as follows:

[0006] A method for determining a thermal cycle test scheme for an electronic device of a nanometer time-grating displacement sensor comprises the following steps:

[0007] S1. Determine the candidate thermal cycling test scheme;

[0008] S2. Based on the candidate solution, measure the maximum shell temperature T'1 of each electronic component of the nano-time-grating displacement sensor at the highest test temperature T1 and the minimum shell temperature T'2 of each electronic component of the nano-time-grating displacement sensor at the lowest test temperature T2, and calculate the corresponding temperature difference ΔT1 of each electronic component under the test conditions;

[0009] ΔT1=T'1-T'2

[0010] S3. Verification of the effectiveness of thermal cycling test:

[0011] S31, determining the effective area S1 of the solder joint corresponding to each early-stage faulty electronic component of the nanometer time-gate displacement sensor, and calculating the shear strain Δγ1 of the solder joint corresponding to each early-stage faulty electronic component under the thermal cycling test condition based on the ΔT1 of the corresponding electronic component in step S2;

[0012]

[0013] In the above formula, K D is the bending stiffness of the solder joint of the corresponding electronic device, in N / m; S1 is the effective area of ​​the solder joint of the corresponding electronic device, in mm 2 ; h is the height of the solder joint of the corresponding electronic device, unit is mm; ΔαLTc is the expansion of the corresponding electronic device under the thermal cycle test conditions, unit is mm; ΔαLTs is the expansion of the circuit board under the thermal cycle test conditions, unit is mm;

[0014] S32. Use the Coffin-Manson thermal fatigue model to calculate the thermal fatigue life N corresponding to each early failure electronic device. f1 ;

[0015]

[0016] In the above formula, Δγ1 is the solder joint shear strain of the electronic device corresponding to early failure under thermal cycle test conditions; ε' f is the fatigue ductility coefficient of the corresponding electronic device under the thermal cycling test conditions; c is the fatigue ductility index of the corresponding electronic device under the thermal cycling test conditions;

[0017] S33, when N f1 When the number of cycles N of the candidate thermal cycle test solution is less than the number of cycles N, the early-stage failure electronic device is determined to be an early-stage failure electronic device that can be screened out;

[0018] S34. Calculate the number of early-stage failure electronic devices that can be screened out and the total number of early-stage failure electronic devices, and calculate the thermal cycling test effectiveness E. When E = 100%, the early-stage failure electronic devices that can be screened out are improved to normal electronic devices, and then proceed to step S4. When E < 100%, increase the severity of the thermal cycling test conditions in step S1, and return to step S2.

[0019]

[0020] In the above formula, m is the number of electronic devices with early-stage failures that can be screened out, and M is the total number of electronic devices with early-stage failures;

[0021] S4. Based on the design requirements of electronic devices, determine the normal operating temperature range of electronic devices and measure the maximum normal operating temperature T 10 The maximum case temperature T' of each electronic device 10 and the minimum normal operating temperature T 20 The minimum case temperature T' of each electronic device under 20 , calculate the temperature difference ΔT2 corresponding to each electronic device under normal working conditions;

[0022] ΔT2=T' 10 -T' 20

[0023] S5. Thermal Cycling Test Damage Analysis:

[0024] S51, determining the effective area S2 of the solder joint corresponding to each normal electronic device of the nano-time-grating displacement sensor, and calculating the corresponding solder joint shear strain Δγ2 of each normal electronic device under the thermal cycle test condition based on the ΔT1 of the corresponding electronic device in step S2;

[0025]

[0026] S52. Use the Coffin-Manson thermal fatigue model to calculate the thermal fatigue life N of normal electronic devices under thermal cycle test conditions. f2 ;

[0027]

[0028] S53. Calculate the test damage rate D1 of normal electronic devices under thermal cycle test conditions;

[0029]

[0030] S6. Normal working damage analysis:

[0031] S61, calculating the corresponding solder point shear strain Δγ3 of each normal electronic device under normal working conditions based on the effective area S2 of the solder point corresponding to each normal electronic device of the nano-time grating displacement sensor and the ΔT2 of the corresponding electronic device in step S4;

[0032]

[0033] ΔαLTc' is the expansion of the corresponding electronic device under normal working conditions, unit is mm; ΔαLTs' is the expansion of the circuit board under normal working conditions, unit is mm;

[0034] S62. Use the Coffin-Manson thermal fatigue model to calculate the thermal fatigue life N of normal electronic devices under normal working conditions. f3 ;

[0035]

[0036] ε'f' is the fatigue ductility coefficient of the corresponding electronic device under normal working conditions; c' is the fatigue ductility index of the corresponding electronic device under normal working conditions;

[0037] S63. Calculate the test damage rate D2 of normal electronic devices under normal working conditions;

[0038]

[0039] In the above formula, N1 is the number of cycles under normal working conditions;

[0040] S7. Determination of test acceptability:

[0041] S71. Calculate the life cycle damage rate D;

[0042] D = D1 + D2;

[0043] S72. When D of all normal electronic devices is less than or equal to 1, execute step S8. When D of any normal electronic device is greater than 1, reduce the severity of the thermal cycle test conditions of step S1 and return to step S2.

[0044] S8. Output the final thermal cycle test plan.

[0045] Furthermore, in steps S31 and S51,

[0046]

[0047] In the above formula, L x L is the maximum spacing between solder joints or the span of solder joint array in the x direction of the corresponding electronic device, in mm; y The maximum spacing between solder joints or the span of solder joint array in the y direction of the corresponding electronic device, in mm;cx is the thermal expansion coefficient of the electronic device in the x direction, in ppm / ℃; cy is the thermal expansion coefficient of the electronic device in the y direction, in ppm / ℃; sx is the thermal expansion coefficient of the circuit board in the x direction, in ppm / ℃; sy is the thermal expansion coefficient of the circuit board in the y direction, in ppm / °C.

[0048] Furthermore, in step S61,

[0049]

[0050] Furthermore, in steps S32 and S52,

[0051]

[0052] In the above formula, Tm is the average temperature of the solder joint during the test cycle under thermal cycle test conditions, in °C; t D It is the maximum temperature immersion time, in min.

[0053] Further, in step S62,

[0054]

[0055] In the above formula, Tm' is the average temperature of the solder joint during the test cycle under normal working conditions, in °C.

[0056] Furthermore, increasing the severity of the thermal cycling test conditions in step S1 means increasing the temperature of the thermal cycling test and / or shortening the temperature change time of the thermal cycling test, and reducing the severity of the thermal cycling test conditions in step S1 means reducing the temperature of the thermal cycling test and / or extending the temperature change time of the thermal cycling test.

[0057] Furthermore, in step S34, the specific operation of improving the removable electronic devices to normal electronic devices is to increase the effective area and height of the solder joints of each removable electronic device so that the fatigue life N of each electronic device under the thermal cycle test conditions is f2 It is greater than the number of cycles N of the candidate solution for the thermal cycling test and is recorded as a normal electronic device.

[0058] Compared with the prior art, the present invention has the following beneficial effects:

[0059] The proposed method for determining thermal cycling test protocols for electronic components of nano-time-grating displacement sensors, tailored to specific nano-time-grating displacement sensors, considers the operating temperature ranges of the sensors' electronic components, significantly improving the accuracy of test results. Furthermore, by integrating the Coffin-Manson thermal fatigue life theory and Miner's linear cumulative damage theory, this method scientifically analyzes the effectiveness and acceptability of thermal cycling tests, thereby developing a rational and efficient test protocol. This method not only evaluates the rationality and effectiveness of various thermal cycling test protocols employed for the electronic components of different nano-time-grating displacement sensors, but also effectively mitigates understress and overstress issues, preventing missed faults and unnecessary damage to the product. This method is more targeted and rational, reducing the application risk of nano-time-grating displacement sensor electronic components in precision displacement measurement. Furthermore, the protocol itself is highly operational, significantly reducing testing costs and facilitating the rapid development of thermal cycling test protocols for the electronic components of nano-time-grating displacement sensors. This method significantly contributes to screening out potential early failures of components, reducing risks, improving product safety, and ensuring reliability and service life. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] Figure 1 The present invention is a flowchart of a method for determining a thermal cycle test solution for electronic devices of a nanometer time-grating displacement sensor. DETAILED DESCRIPTION

[0061] The specific embodiments of the present invention are described in further detail below with reference to the accompanying drawings.

[0062] See also Figure 1 The present invention provides a method for determining a thermal cycle test scheme for an electronic device of a nanometer time-grating displacement sensor, comprising the following steps:

[0063] S1. Determine the candidate thermal cycling test scheme;

[0064] S2. Based on the candidate solution, measure the maximum shell temperature T'1 of each electronic component of the nano-time-grating displacement sensor at the highest test temperature T1 and the minimum shell temperature T'2 of each electronic component of the nano-time-grating displacement sensor at the lowest test temperature T2, and calculate the corresponding temperature difference ΔT1 of each electronic component under the test conditions;

[0065] ΔT1=T'1-T'2

[0066] S3. Verification of the effectiveness of thermal cycling test:

[0067] S31, determining the effective area S1 of the solder joint corresponding to each early-stage faulty electronic component of the nanometer time-gate displacement sensor, and calculating the shear strain Δγ1 of the solder joint corresponding to each early-stage faulty electronic component under the thermal cycling test condition based on the ΔT1 of the corresponding electronic component in step S2;

[0068]

[0069] In the above formula, K D is the bending stiffness of the solder joint of the corresponding electronic device, in N / m; S1 is the effective area of ​​the solder joint of the corresponding electronic device, in mm 2 ; h is the height of the solder joint of the corresponding electronic device, unit is mm; ΔαLTc is the expansion of the corresponding electronic device under the thermal cycle test conditions, unit is mm; ΔαLTs is the expansion of the circuit board under the thermal cycle test conditions, unit is mm;

[0070] S32. Use the Coffin-Manson thermal fatigue model to calculate the thermal fatigue life N corresponding to each early failure electronic device. f1 ;

[0071]

[0072] In the above formula, Δγ1 is the solder joint shear strain of the electronic device corresponding to early failure under thermal cycle test conditions; ε' f is the fatigue ductility coefficient of the corresponding electronic device under the thermal cycling test conditions; c is the fatigue ductility index of the corresponding electronic device under the thermal cycling test conditions;

[0073] S33, when N f1 When the number of cycles N of the candidate thermal cycle test solution is less than the number of cycles N, the early-stage failure electronic device is determined to be an early-stage failure electronic device that can be screened out;

[0074] S34. Calculate the number of early-stage failure electronic devices that can be screened out and the total number of early-stage failure electronic devices, and calculate the thermal cycling test effectiveness E. When E = 100%, the early-stage failure electronic devices that can be screened out are improved to normal electronic devices, and then proceed to step S4. When E < 100%, increase the severity of the thermal cycling test conditions in step S1, and return to step S2.

[0075]

[0076] In the above formula, m is the number of electronic devices with early-stage failures that can be screened out, and M is the total number of electronic devices with early-stage failures;

[0077] S4. Based on the design requirements of electronic devices, determine the normal operating temperature range of electronic devices and measure the maximum normal operating temperature T 10 The maximum case temperature T' of each electronic device 10 and the minimum normal operating temperature T 20 The minimum case temperature T' of each electronic device under 20 , calculate the temperature difference ΔT2 corresponding to each electronic device under normal working conditions;

[0078] ΔT2=T' 10 -T' 20

[0079] S5. Thermal Cycling Test Damage Analysis:

[0080] S51, determining the effective area S2 of the solder joint corresponding to each normal electronic device of the nano-time-grating displacement sensor, and calculating the corresponding solder joint shear strain Δγ2 of each normal electronic device under the thermal cycle test condition based on the ΔT1 of the corresponding electronic device in step S2;

[0081]

[0082] S52. Use the Coffin-Manson thermal fatigue model to calculate the thermal fatigue life N of normal electronic devices under thermal cycle test conditions. f2 ;

[0083]

[0084] S53. Calculate the test damage rate D1 of normal electronic devices under thermal cycle test conditions;

[0085]

[0086] In the above formula, N is the number of cycles of the candidate thermal cycling test solution;

[0087] S6. Normal working damage analysis:

[0088] S61, calculating the corresponding solder point shear strain Δγ3 of each normal electronic device under normal working conditions based on the effective area S2 of the solder point corresponding to each normal electronic device of the nano-time grating displacement sensor and the ΔT2 of the corresponding electronic device in step S4;

[0089]

[0090] ΔαLTc' is the expansion of the corresponding electronic device under normal working conditions, unit is mm; ΔαLTs' is the expansion of the circuit board under normal working conditions, unit is mm;

[0091] S62. Use the Coffin-Manson thermal fatigue model to calculate the thermal fatigue life N of normal electronic devices under normal working conditions. f3 ;

[0092]

[0093] ε'f' is the fatigue ductility coefficient of the corresponding electronic device under normal working conditions; c' is the fatigue ductility index of the corresponding electronic device under normal working conditions;

[0094] S63. Calculate the test damage rate D2 of normal electronic devices under normal working conditions;

[0095]

[0096] In the above formula, N1 is the number of cycles under normal working conditions;

[0097] S7. Determination of test acceptability:

[0098] S71. Calculate the life cycle damage rate D;

[0099] D = D1 + D2;

[0100] S72. When D of all normal electronic devices is less than or equal to 1, execute step S8. When D of any normal electronic device is greater than 1, reduce the severity of the thermal cycle test conditions of step S1 and return to step S2.

[0101] S8. Output the final thermal cycle test plan.

[0102] In specific implementation, in steps S31 and S51,

[0103]

[0104] In the above formula, L x L is the maximum spacing between solder joints or the span of solder joint array in the x direction of the corresponding electronic device, in mm; y The maximum spacing between solder joints or the span of solder joint array in the y direction of the corresponding electronic device, in mm; cx is the thermal expansion coefficient of the electronic device in the x direction, in ppm / ℃; cy is the thermal expansion coefficient of the electronic device in the y direction, in ppm / ℃; sx is the thermal expansion coefficient of the circuit board in the x direction, in ppm / ℃; sy is the thermal expansion coefficient of the circuit board in the y direction, in ppm / °C.

[0105] During specific implementation, in step S61,

[0106]

[0107] In specific implementation, in steps S32 and S52,

[0108]

[0109] In the above formula, Tm is the average temperature of the solder joint during the test cycle under thermal cycle test conditions, in °C; t D It is the maximum temperature immersion time, in min.

[0110] During specific implementation, in step S62,

[0111]

[0112] In the above formula, Tm' is the average temperature of the solder joint during the test cycle under normal working conditions, in °C.

[0113] In specific implementation, increasing the severity of the thermal cycling test conditions in step S1 means increasing the temperature of the thermal cycling test and / or shortening the temperature change time of the thermal cycling test, and reducing the severity of the thermal cycling test conditions in step S1 means reducing the temperature of the thermal cycling test and / or extending the temperature change time of the thermal cycling test.

[0114] In the specific implementation, in step S34, the specific operation of improving the removable electronic devices to normal electronic devices is to increase the effective area and height of the solder joints of each removable electronic device so that the fatigue life N of each electronic device under the thermal cycle test conditions is f2 It is greater than the number of cycles N of the candidate solution for the thermal cycling test and is recorded as a normal electronic device.

[0115] In the present invention, the early-stage faulty electronic components refer to all electronic components in the nanometer time-grating displacement sensor that have failed during the early-stage fault period. The early-stage fault period refers to the stage when the product has just been put into use and has a high failure rate.

[0116] The present invention's thermal cycling test protocol is based on the fact that, when using a nanometer-scale displacement sensor, the sensor's electronic components may malfunction, necessitating improvements to ensure they meet user requirements. Considering that temperature is the primary factor affecting the lifespan of electronic components, the present invention incorporates a thermal cycling test. By analyzing the changes in various performance parameters of each electronic component during the thermal cycling test, the primary factors causing failure are identified, allowing for targeted improvements to ensure a functioning electronic component.

[0117] Principle: In the process of determining the thermal cycling test plan, first, all faulty devices need to be screened out at the test temperature to prove that the test plan is effective. If all faulty devices cannot be screened out, the test severity needs to be increased until all faulty devices are screened out. After screening, the changes in the performance parameters of each electronic device during the thermal cycling test are analyzed to find out the main factors causing the failure of the electronic device, and improvements are made to the factors to obtain normal electronic devices. However, in order to avoid unnecessary damage to the device due to excessively harsh thermal cycling test conditions, the thermal damage of the normal electronic devices obtained after the improvement needs to be analyzed. If the full life cycle damage rate D of each normal electronic device is ≤1, the thermal cycling test is just appropriate. If the full life cycle damage rate D of any normal electronic device is >1, the test severity needs to be reduced and the test plan needs to be re-determined until a reasonable thermal cycling test plan is obtained.

[0118] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit the technical solutions. Those skilled in the art should understand that modifications or equivalent replacements of the technical solutions of the present invention that do not depart from the purpose and scope of the technical solutions of the present invention should be included in the scope of the claims of the present invention.

Claims

1. A method for determining a thermal cycle test scheme for an electronic device of a nanometer time-grating displacement sensor, characterized in that: The following steps are involved: S1. Determine the candidate thermal cycling test scheme; S2. Based on the candidate solution, measure the maximum shell temperature T'1 of each electronic component of the nano-time-grating displacement sensor at the highest test temperature T1 and the minimum shell temperature T'2 of each electronic component of the nano-time-grating displacement sensor at the lowest test temperature T2, and calculate the corresponding temperature difference ΔT1 of each electronic component under the test conditions; ΔT1=T'1-T'2 S3. Verification of the effectiveness of thermal cycling test: S31, determining the effective area S1 of the solder joint corresponding to each early-stage faulty electronic component of the nanometer time-gate displacement sensor, and calculating the shear strain Δγ1 of the solder joint corresponding to each early-stage faulty electronic component under the thermal cycling test condition based on the ΔT1 of the corresponding electronic component in step S2; In the above formula, K D is the bending stiffness of the solder joint of the corresponding electronic device, in N / m; S1 is the effective area of ​​the solder joint of the corresponding electronic device, in mm 2 ; h is the height of the solder joint of the corresponding electronic device, unit is mm; ΔαLTc is the expansion of the corresponding electronic device under the thermal cycle test conditions, unit is mm; ΔαLTs is the expansion of the circuit board under the thermal cycle test conditions, unit is mm; S32. Use the Coffin-Manson thermal fatigue model to calculate the thermal fatigue life N corresponding to each early failure electronic device. f1 ; In the above formula, Δγ1 is the solder joint shear strain of the electronic device corresponding to early failure under thermal cycle test conditions; ε' f is the fatigue ductility coefficient of the corresponding electronic device under the thermal cycling test conditions; c is the fatigue ductility index of the corresponding electronic device under the thermal cycling test conditions; S33, when N f1 When the number of cycles N of the candidate thermal cycle test solution is less than the number of cycles N, the early-stage failure electronic device is determined to be an early-stage failure electronic device that can be screened out; S34. Calculate the number of early-stage failure electronic devices that can be screened out and the total number of early-stage failure electronic devices, and calculate the thermal cycling test effectiveness E. When E = 100%, the early-stage failure electronic devices that can be screened out are improved to normal electronic devices, and then proceed to step S4. When E < 100%, increase the severity of the thermal cycling test conditions in step S1, and return to step S2. In the above formula, m is the number of electronic devices with early-stage failures that can be screened out, and M is the total number of electronic devices with early-stage failures; S4. Based on the design requirements of electronic devices, determine the normal operating temperature range of electronic devices and measure the maximum normal operating temperature T 10 The maximum case temperature T' of each electronic device 10 and the minimum normal operating temperature T 20 The minimum case temperature T' of each electronic device under 20 , calculate the temperature difference ΔT2 corresponding to each electronic device under normal working conditions; ΔT2=T' 10 -T' 20 S5. Thermal Cycling Test Damage Analysis: S51, determining the effective area S2 of the solder joint corresponding to each normal electronic device of the nano-time-grating displacement sensor, and calculating the corresponding solder joint shear strain Δγ2 of each normal electronic device under the thermal cycle test condition based on the ΔT1 of the corresponding electronic device in step S2; S52. Use the Coffin-Manson thermal fatigue model to calculate the thermal fatigue life N of normal electronic devices under thermal cycle test conditions. f2 ; S53. Calculate the test damage rate D1 of normal electronic devices under thermal cycle test conditions; S6. Normal working damage analysis: S61, calculating the corresponding solder point shear strain Δγ3 of each normal electronic device under normal working conditions based on the effective area S2 of the solder point corresponding to each normal electronic device of the nano-time grating displacement sensor and the ΔT2 of the corresponding electronic device in step S4; ΔαLTc' is the expansion of the corresponding electronic device under normal working conditions, unit is mm; ΔαLTs' is the expansion of the circuit board under normal working conditions, unit is mm; S62. Use the Coffin-Manson thermal fatigue model to calculate the thermal fatigue life N of normal electronic devices under normal working conditions. f3 ; ε'f' is the fatigue ductility coefficient of the corresponding electronic device under normal working conditions; c' is the fatigue ductility index of the corresponding electronic device under normal working conditions; S63. Calculate the test damage rate D2 of normal electronic devices under normal working conditions; In the above formula, N1 is the number of cycles under normal working conditions; S7. Determination of test acceptability: S71. Calculate the life cycle damage rate D; D = D1 + D2; S72. When D of all normal electronic devices is less than or equal to 1, execute step S8. When D of any normal electronic device is greater than 1, reduce the severity of the thermal cycle test conditions of step S1 and return to step S2. S8. Output the final thermal cycle test plan.

2. The method for determining a thermal cycle test scheme for an electronic device of a nanometer time-grating displacement sensor according to claim 1, characterized in that: In the steps S31 and S51, In the above formula, L x L is the maximum spacing between solder joints or the span of solder joint array in the x direction of the corresponding electronic device, in mm; y The maximum spacing between solder joints or the span of solder joint array in the y direction of the corresponding electronic device, in mm; cx is the thermal expansion coefficient of the electronic device in the x direction, in ppm / ℃; cy is the thermal expansion coefficient of the electronic device in the y direction, in ppm / ℃; sx is the thermal expansion coefficient of the circuit board in the x direction, in ppm / ℃; sy is the thermal expansion coefficient of the circuit board in the y direction, in ppm / °C.

3. The method for determining a thermal cycle test scheme for an electronic device of a nanometer time-grating displacement sensor according to claim 1, characterized in that: In the step S61, 4. The method for determining a thermal cycle test plan for an electronic device of a nanometer time-grating displacement sensor according to claim 1, characterized in that: In the steps S32 and S52, In the above formula, Tm is the average temperature of the solder joint during the test cycle under thermal cycle test conditions, in °C; t D It is the maximum temperature immersion time, in min.

5. The method for determining a thermal cycle test plan for an electronic device of a nanometer time-grating displacement sensor according to claim 1, characterized in that: In the step S62, In the above formula, Tm' is the average temperature of the solder joint during the test cycle under normal working conditions, in °C.

6. The method for determining a thermal cycle test plan for an electronic device of a nanometer time-grating displacement sensor according to claim 1, characterized in that: Increasing the severity of the thermal cycling test conditions in step S1 is to increase the temperature of the thermal cycling test and / or shorten the temperature change time of the thermal cycling test, and decreasing the severity of the thermal cycling test conditions in step S1 is to decrease the temperature of the thermal cycling test and / or extend the temperature change time of the thermal cycling test.

7. The method for determining a thermal cycle test plan for an electronic device of a nanometer time-grating displacement sensor according to claim 1, characterized in that: In step S34, the specific operation of improving the removable electronic devices to normal electronic devices is to increase the effective area and height of the solder joints of each removable electronic device so that the fatigue life N of each electronic device under the thermal cycle test conditions is f2 It is greater than the number of cycles N of the candidate solution for the thermal cycling test and is recorded as a normal electronic device.

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