Multi-plate register dynamic offset system

Abstract

The invention relates to the technical field of computer system simulation, in particular to a multi-plate register dynamic offset system. The multi-plate register dynamic offset system comprises an instruction cache, an instruction fetching unit, a decoding unit, a transmitting unit, a plurality of functional units and a vector register file, the instruction fetching unit fetches a next instruction to be executed from the instruction cache, the decoding unit analyzes the instruction fetched by the instruction fetching unit, and the transmitting unit judges which functional unit the instruction is executed by according to the analyzed instruction and transmits the instruction to the corresponding functional unit; the multiple functional units comprise a loading storage unit, an arithmetic logic unit, a multiplication unit and a floating point arithmetic unit; and the vector register file realizes communication among the functional units and temporarily stores an intermediate result of instruction execution. According to the multi-plate register dynamic offset system, plate conflicts generated when the plate offsets of two vector registers accessed at the same time are the same can be avoided, the performance of a processor is improved, and power consumption is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of computer system architecture design, and in particular to a multi-block register dynamic offset system. Background Art

[0002] In the field of high-performance computing, parallel computing was initially widely used in scientific computing. In recent years, with the development of artificial intelligence and machine learning, the need to leverage parallel computing to broadly and efficiently utilize computing resources has become even more pressing. Vectorization is a key feature of modern computer architectures for parallel computing. It allows a single instruction to be executed on multiple data elements, known as single instruction, multiple data (SIMD). SIMD allows a processor to perform the same operation on multiple data elements simultaneously, significantly improving processing speed and efficiency.

[0003] Unlike traditional array processing instructions, vector computing instructions complete vector input and output through multiple cycles. Instructions for different functional units can be executed overlappingly through chain execution, allowing the vector processor to simultaneously exploit data-level and instruction-level parallelism. In chain execution mode, the functional units exchange data streams through vector register files, which is actually a stream processor. In order to achieve efficient computing, the register file needs to support high-concurrency access to avoid conflicts when multiple accesses to the same storage resource occur, but multi-port register files require a large amount of area, so register files are generally implemented using multi-block single-port storage units.

[0004] Multi-block register files can encounter block conflicts during application. Block conflicts can starve accessed functional units, reducing processor performance. Traditional approaches based on static block layouts can fail in certain scenarios and lack dynamic adaptability.

[0005] In order to improve the access efficiency of multi-block register files, enhance processor performance and reduce power consumption, the present invention proposes a multi-block register dynamic offset system. Summary of the Invention

[0006] In order to overcome the defects of the prior art, the present invention provides a simple and efficient multi-segment register dynamic offset system.

[0007] The present invention is achieved through the following technical solutions:

[0008] A multi-block register dynamic offset system includes an instruction cache, an instruction fetch unit, a decoding unit, an emission unit, multiple functional units and a vector register file;

[0009] The instruction cache is a high-speed cache used to cache program instructions. If a cache miss occurs in the instruction cache during the instruction fetch phase, the instruction cache is responsible for moving the instructions in the memory to the instruction cache.

[0010] The instruction fetch unit is used to fetch the next instruction to be executed from the instruction cache;

[0011] The decoding unit is used to parse the instructions fetched by the instruction fetch unit;

[0012] The transmitting unit is responsible for determining which functional unit is to execute the instruction based on the parsed instruction and transmitting the instruction to the corresponding functional unit;

[0013] The various functional units include but are not limited to a load-store unit, an arithmetic logic unit, a multiplication unit, and a floating-point unit;

[0014] The vector register file is used to implement communication between various functional units and temporarily store intermediate results of instruction execution.

[0015] The structure of the vector register file includes an arbiter, a multi-slab register storage, a crossbar switch and an operand cache;

[0016] The arbiter is used to arbitrate instructions, select instructions that can perform multi-block register storage access, and store register access tags;

[0017] The multi-block register storage is a storage array of register files, which is used to implement the data storage function;

[0018] The crossbar switch is used to cross-connect multiple blocks of register storage and multiple operand caches;

[0019] The operand cache is used to collect operands of corresponding instructions and provide them to corresponding functional units after the data are ready.

[0020] Preferably, when an instruction accesses a register, a register access mark of the arbitrator is calculated and obtained, and is used to mark the access status of each vector register.

[0021] The register access tag is also used to set an offset for the corresponding register. Every time a new vector instruction arrives, the tag of the register will be dynamically updated, thereby dynamically setting the register offset.

[0022] Preferably, the register access flag will be updated when the following conditions are met:

[0023] The current instruction's access to registers does not conflict with other active vector instructions in a read-after-write or write-after-write manner.

[0024] The corresponding vector instructions operate on the entire vector length VLEN;

[0025] The corresponding vector instructions are either unmasked or follow the mask-don't-care policy.

[0026] Furthermore, the register offset obtained based on the register access tag is stored in a lookup table of the arbitrator.

[0027] Preferably, the initial states of the offsets of the various registers in the lookup table are arranged in a staggered layout, and according to an update strategy, the offsets of the corresponding registers are updated each time a qualified instruction arrives and stored in the lookup table.

[0028] Furthermore, the arbitrator arbitrates incoming instruction access register file requests through a polling strategy, that is, when the arbitrator detects that the register block accessed by the instruction is idle, it directly allows access to the register block; when the register block accessed by the instruction is busy, the arbitrator pushes the instruction into the internal instruction queue and issues the instruction through a polling arbitration method.

[0029] The beneficial effect of the present invention is that the multi-block register dynamic offset system can avoid the block conflict caused by the same block offset of two vector registers accessed simultaneously, significantly improve the access efficiency of the multi-block register file, thereby improving processor performance and reducing power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0031] Attachment Figure 1 FIG. 1 is a schematic diagram of the architecture of the vector processor of the present invention.

[0032] Attachment Figure 2 Schematic diagram of the static sequential distribution of registers in multiple modules.

[0033] Attachment Figure 3 Schematic diagram of the static staggered distribution of registers in multiple blocks.

[0034] Attachment Figure 4 Schematic diagrams of two possible dynamic distributions of registers in multiple modules. DETAILED DESCRIPTION

[0035] In order to enable those skilled in the art to better understand the technical solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the embodiments of the present invention. Obviously, the embodiments described are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work should fall within the scope of protection of the present invention.

[0036] The vector register completes the execution of vector instructions through multiple cycles, that is, data vectors are consumed or produced in the vector processor in multiple cycles. The architectural diagram of the vector processor is as follows Figure 1 As shown in the figure, a vector processor has a variety of different processing units, such as an arithmetic logic unit, floating-point unit, and load-store unit, with the vector register file as the central node. Multiple vector instructions in a vector processor can be executed in parallel in different execution units. In addition, each processing unit in a vector processor can have multiple parallel functional unit nodes. These parallel functional units can also process data at different locations in a vector instruction in parallel, accelerating the execution of vector instructions.

[0037] Multiple functional units in a vector processor exchange data through the vector register file. Therefore, as a central node in the topology, the vector register file has extremely high throughput requirements. To enable multiple functional units to access the vector register file in parallel, the vector register file must provide multiple read and write interfaces. Implementing multiple ports on a single register file consumes a significant amount of area, so vector register files typically adopt a multi-block design. This involves using a single-port register file as a block, and combining multiple blocks to implement multi-way access.

[0038] In the existing multi-block vector register file, the registers adopt a static layout. Assume that the vector length is set to VLEN = 128 bits, there are 4 words in each vector register, each word consists of 4 bytes, and each byte is 8 bits. The simplest sequential layout is as follows Figure 2 As shown in the figure, in this layout, each vector register is arranged starting from block 0. Sequential arrangement can cause block conflicts when there are multiple instruction accesses or multiple register access requests in one instruction. For example, the instruction vadd v0, v1, v0 will be issued to the vector arithmetic logic unit for execution. This instruction needs to read vector registers v0 and v1 as source operands. When the vector arithmetic logic unit 0 reads v0_w0 and v1_w0, since these two words are in the same block, only one word can be read at a time. The other word can only be read in the next clock cycle.

[0039] To solve the above problems, a vector register architecture has proposed an interleaved layout of vector register files, such as Figure 3As shown in the figure, each vector register is assigned a bank offset. This alleviates the bank conflict problem described above. However, since the number of vector registers is generally much greater than the number of banks, it's inevitable that two vector registers may have the same offset. Bank conflicts still occur when two vector registers that need to be accessed simultaneously have the same bank offset. Furthermore, since the register numbers in the instructions are determined during the compilation phase, these bank conflicts are inevitable.

[0040] The multi-block register dynamic offset system includes an instruction cache, an instruction fetch unit, a decoding unit, an emission unit, multiple functional units and a vector register file;

[0041] The instruction cache is a high-speed cache used to cache program instructions. If a cache miss occurs in the instruction cache during the instruction fetch phase, the instruction cache is responsible for moving the instructions in the memory to the instruction cache.

[0042] The instruction fetch unit is used to fetch the next instruction to be executed from the instruction cache;

[0043] The decoding unit is used to parse the instructions fetched by the instruction fetch unit;

[0044] The transmitting unit is responsible for determining which functional unit is to execute the instruction based on the parsed instruction and transmitting the instruction to the corresponding functional unit;

[0045] The various functional units include but are not limited to a load-store unit, an arithmetic logic unit, a multiplication unit, and a floating-point unit;

[0046] The vector register file is used to implement communication between various functional units and temporarily store intermediate results of instruction execution.

[0047] The structure of the vector register file includes an arbiter, a multi-slab register storage, a crossbar switch and an operand cache;

[0048] The arbiter is used to arbitrate instructions, select instructions that can perform multi-block register storage access, and store register access tags;

[0049] The multi-block register storage is a storage array of register files, which is used to implement the data storage function;

[0050] The crossbar switch is used to cross-connect multiple blocks of register storage and multiple operand caches;

[0051] The operand cache is used to collect operands of corresponding instructions and provide them to corresponding functional units after the data are ready.

[0052] Preferably, when an instruction accesses a register, a register access mark of the arbitrator is calculated and obtained, and is used to mark the access status of each vector register.

[0053] The register access tag is also used to set an offset for the corresponding register. Every time a new vector instruction arrives, the tag of the register will be dynamically updated, thereby dynamically setting the register offset.

[0054] Preferably, the register access flag will be updated when the following conditions are met:

[0055] The current instruction's access to registers does not conflict with other active vector instructions in a read-after-write or write-after-write manner.

[0056] The corresponding vector instructions operate on the entire vector length VLEN;

[0057] The corresponding vector instructions are either unmasked or follow the mask-don't-care policy.

[0058] Furthermore, the register offset obtained based on the register access tag is stored in a lookup table of the arbitrator.

[0059] Preferably, the initial states of the offsets of the various registers in the lookup table are arranged in a staggered layout, and according to an update strategy, the offsets of the corresponding registers are updated each time a qualified instruction arrives and stored in the lookup table.

[0060] Furthermore, the arbitrator arbitrates incoming instruction access register file requests through a polling strategy, that is, when the arbitrator detects that the register block accessed by the instruction is idle, it directly allows access to the register block; when the register block accessed by the instruction is busy, the arbitrator pushes the instruction into the internal instruction queue and issues the instruction through a polling arbitration method.

[0061] Whether the register block accessed by the instruction is in an idle state is determined by the arbitrator according to custom rules.

[0062] The embodiment described above is only one specific implementation of the present invention. Common changes and substitutions made by those skilled in the art within the scope of the technical solution of the present invention should be included in the protection scope of the present invention.

Claims

1. A multi-segment register dynamic offset system, characterized by: Includes instruction cache, instruction fetch unit, decode unit, transmit unit, various functional units and vector register file; The instruction cache is a high-speed cache used to cache program instructions. If a cache miss occurs in the instruction cache during the instruction fetch phase, the instruction cache is responsible for moving the instructions in the memory to the instruction cache. The instruction fetch unit is used to fetch the next instruction to be executed from the instruction cache; The decoding unit is used to parse the instructions fetched by the instruction fetch unit; The transmitting unit is responsible for determining which functional unit is to execute the instruction based on the parsed instruction and transmitting the instruction to the corresponding functional unit; The various functional units include but are not limited to a load-store unit, an arithmetic logic unit, a multiplication unit, and a floating-point unit; The vector register file is used to implement communication between various functional units and temporarily store intermediate results of instruction execution.

2. The multi-segment register dynamic offset system according to claim 1, characterized in that: The structure of the vector register file includes an arbiter, a multi-slab register storage, a crossbar switch and an operand cache; The arbiter is used to arbitrate instructions, select instructions that can perform multi-block register storage access, and store register access tags; The multi-block register storage is a storage array of register files, which is used to implement the data storage function; The crossbar switch is used to cross-connect multiple blocks of register storage and multiple operand caches; The operand cache is used to collect operands of corresponding instructions and provide them to corresponding functional units after the data are ready.

3. The multi-segment register dynamic offset system according to claim 2, characterized in that: When an instruction accesses a register, a register access tag of the arbitrator is calculated and obtained, and is used to mark the access status of each vector register.

4. The multi-segment register dynamic offset system according to claim 3, characterized in that: The register access tag is also used to set an offset for the corresponding register. Every time a new vector instruction arrives, the tag of the register will be dynamically updated, thereby dynamically setting the register offset.

5. The multi-segment register dynamic offset system according to claim 4, characterized in that: The register access flag will be updated when the following conditions are met: The current instruction's access to registers does not conflict with other active vector instructions in a read-after-write or write-after-write manner. The corresponding vector instructions operate on the entire vector length VLEN; The corresponding vector instructions are either unmasked or follow the mask-don't-care policy.

6. The multi-segment register dynamic offset system according to claim 5, characterized in that: The register offset obtained based on the register access tag is stored in a lookup table of the arbiter.

7. The multi-segment register dynamic offset system according to claim 6, characterized in that: The initial states of the offsets of the various registers in the lookup table are arranged in an interleaved layout, and according to an update strategy, the offsets of the corresponding registers are updated each time a qualified instruction arrives and stored in the lookup table.

8. The multi-segment register dynamic offset system according to claim 7, characterized in that: The arbitrator arbitrates incoming instruction access register file requests through a polling strategy. That is, when the arbitrator detects that the register block accessed by the instruction is idle, it directly allows access to the register block; when the register block accessed by the instruction is busy, the arbitrator pushes the instruction into the internal instruction queue and issues the instruction through polling arbitration.

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